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Searched refs:phy_set_bits (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/net/phy/
H A Dnxp-tja11xx.c133 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); in tja11xx_enable_reg_write()
138 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_enable_link_control()
158 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup()
189 return phy_set_bits(phydev, MII_CFG3, MII_CFG3_PHY_EN); in tja11xx_wakeup()
343 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_config_init()
739 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST); in tja11xx_cable_test_start()
800 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_get_status()
H A Dnxp-cbtx.c89 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
105 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
H A Dintel-xway.c498 return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_EN(index)); in xway_gphy_led_hw_control_set()
524 return phy_set_bits(phydev, XWAY_MDIO_LED, XWAY_GPHY_LED_INV(index)); in xway_gphy_led_polarity_set()
H A Dsmsc.c94 return phy_set_bits(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_edpd()
214 int rc = phy_set_bits(phydev, PHY_EDPD_CONFIG, in lan95xx_config_aneg_ext()
H A Dmxl-gpy.c780 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); in gpy_set_wol()
983 return phy_set_bits(phydev, PHY_LED, PHY_LED_HWCONTROL(index)); in gpy_led_hw_control_set()
1009 return phy_set_bits(phydev, PHY_LED, PHY_LED_POLARITY(index)); in gpy_led_polarity_set()
H A Dicplus.c281 ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON); in ip101a_config_init()
H A Ddp83867.c941 phy_set_bits(phydev, DP83867_CFG2, in dp83867_link_change_notify()
H A Dbcm-phy-lib.c636 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE); in bcm_phy_enable_jumbo()
H A Dmarvell.c1341 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1583 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
H A Dphy_device.c2705 return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_suspend()
/linux/drivers/net/phy/mediatek/
H A Dmtk-2p5ge.c82 phy_set_bits(phydev, MII_BMCR, BMCR_RESET); in mt798x_2p5ge_phy_load_fw()
85 phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in mt798x_2p5ge_phy_load_fw()
96 phy_set_bits(phydev, MII_BMCR, BMCR_RESET); in mt798x_2p5ge_phy_load_fw()
H A Dmtk-ge.c81 phy_set_bits(phydev, 0x17, BIT(4)); in mt7531_phy_config_init()
/linux/drivers/net/phy/qcom/
H A Dqca83xx.c121 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); in qca83xx_config_init()
165 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); in qca83xx_resume()
H A Dqca807x.c692 phy_set_bits(phydev, in qca807x_sfp_remove()
H A Dat803x.c931 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); in at8031_config_intr()
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c515 return phy_set_bits(phydev, MII_CTRL1000, in rtl8211c_config_init()
878 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, in rtl8366rb_config_init()
/linux/include/linux/
H A Dphy.h1535 * phy_set_bits - Convenience function for setting bits in a PHY register
1540 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_set_bits() function