| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac-ingenic.c | 67 int (*set_mode)(struct ingenic_mac *mac, u8 phy_intf_sel);
72 static int jz4775_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel) in jz4775_mac_set_mode() argument
76 val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel) | in jz4775_mac_set_mode()
83 static int x1000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel) in x1000_mac_set_mode() argument
89 static int x1600_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel) in x1600_mac_set_mode() argument
93 val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel); in x1600_mac_set_mode()
99 static int x1830_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel) in x1830_mac_set_mode() argument
104 FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel); in x1830_mac_set_mode()
110 static int x2000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel) in x2000_mac_set_mode() argument
114 val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel); in x2000_mac_set_mode()
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| H A D | dwmac-imx.c | 50 int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel);
67 static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) in imx8mp_set_intf_mode() argument
71 val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | in imx8mp_set_intf_mode()
74 if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext) in imx8mp_set_intf_mode()
76 else if (phy_intf_sel == PHY_INTF_SEL_RGMII) in imx8mp_set_intf_mode()
84 imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) in imx8dxl_set_intf_mode() argument
90 static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) in imx93_set_intf_mode() argument
95 if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { in imx93_set_intf_mode()
104 val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | in imx93_set_intf_mode()
138 static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) in imx_set_phy_intf_sel() argument
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| H A D | dwmac-starfive.c | 36 int phy_intf_sel; in starfive_dwmac_set_mode() local
39 phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface); in starfive_dwmac_set_mode()
40 if (phy_intf_sel != PHY_INTF_SEL_RGMII && in starfive_dwmac_set_mode()
41 phy_intf_sel != PHY_INTF_SEL_RMII) { in starfive_dwmac_set_mode()
44 return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; in starfive_dwmac_set_mode()
56 phy_intf_sel << args[1]); in starfive_dwmac_set_mode()
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| H A D | dwmac-visconti.c | 149 int phy_intf_sel; in visconti_eth_init_hw() local
151 phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface); in visconti_eth_init_hw()
152 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in visconti_eth_init_hw()
153 phy_intf_sel != PHY_INTF_SEL_RGMII && in visconti_eth_init_hw()
154 phy_intf_sel != PHY_INTF_SEL_RMII) { in visconti_eth_init_hw()
159 writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL); in visconti_eth_init_hw()
169 phy_intf_sel |= ETHER_ETH_CONTROL_RESET; in visconti_eth_init_hw()
170 writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL); in visconti_eth_init_hw()
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| H A D | dwmac-stm32.c | 231 u8 phy_intf_sel) in stm32mp1_configure_pmcr() argument
237 val = FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, phy_intf_sel); in stm32mp1_configure_pmcr()
287 u8 phy_intf_sel) in stm32mp2_configure_syscfg() argument
293 val = FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, phy_intf_sel); in stm32mp2_configure_syscfg()
335 int phy_intf_sel, ret; in stm32mp1_set_mode() local
345 phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface); in stm32mp1_set_mode()
346 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in stm32mp1_set_mode()
347 phy_intf_sel != PHY_INTF_SEL_RGMII && in stm32mp1_set_mode()
348 phy_intf_sel != PHY_INTF_SEL_RMII) { in stm32mp1_set_mode()
351 return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; in stm32mp1_set_mode()
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| H A D | dwmac-mediatek.c | 89 u8 phy_intf_sel);
111 u8 phy_intf_sel) in mt2712_set_interface() argument
113 u32 intf_val = phy_intf_sel; in mt2712_set_interface()
115 if (phy_intf_sel == PHY_INTF_SEL_RMII) { in mt2712_set_interface()
277 u8 phy_intf_sel) in mt8195_set_interface() argument
279 u32 intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel); in mt8195_set_interface()
281 if (phy_intf_sel == PHY_INTF_SEL_RMII) { in mt8195_set_interface()
501 int phy_intf_sel, ret; in mediatek_dwmac_init() local
504 phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_mode); in mediatek_dwmac_init()
505 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in mediatek_dwmac_init()
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| H A D | dwmac-lpc18xx.c | 26 static int lpc18xx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) in lpc18xx_set_phy_intf_sel() argument
30 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in lpc18xx_set_phy_intf_sel()
31 phy_intf_sel != PHY_INTF_SEL_RMII) in lpc18xx_set_phy_intf_sel()
37 phy_intf_sel)); in lpc18xx_set_phy_intf_sel()
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| H A D | dwmac-sti.c | 149 static int sti_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) in sti_set_phy_intf_sel() argument
161 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in sti_set_phy_intf_sel()
162 phy_intf_sel != PHY_INTF_SEL_RGMII && in sti_set_phy_intf_sel()
163 phy_intf_sel != PHY_INTF_SEL_SGMII && in sti_set_phy_intf_sel()
164 phy_intf_sel != PHY_INTF_SEL_RMII) in sti_set_phy_intf_sel()
165 phy_intf_sel = PHY_INTF_SEL_GMII_MII; in sti_set_phy_intf_sel()
168 FIELD_PREP(MII_PHY_SEL_MASK, phy_intf_sel)); in sti_set_phy_intf_sel()
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| H A D | dwmac-loongson1.c | 141 int phy_intf_sel; in ls1c_dwmac_syscon_init() local
143 phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_interface); in ls1c_dwmac_syscon_init()
144 if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && in ls1c_dwmac_syscon_init()
145 phy_intf_sel != PHY_INTF_SEL_RMII) { in ls1c_dwmac_syscon_init()
152 FIELD_PREP(PHY_INTF_SELI, phy_intf_sel)); in ls1c_dwmac_syscon_init()
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| H A D | dwmac-meson8b.c | 239 int phy_intf_sel; in meson_axg_set_phy_mode() local
241 phy_intf_sel = stmmac_get_phy_intf_sel(dwmac->phy_mode); in meson_axg_set_phy_mode()
242 if (phy_intf_sel != PHY_INTF_SEL_RGMII && in meson_axg_set_phy_mode()
243 phy_intf_sel != PHY_INTF_SEL_RMII) { in meson_axg_set_phy_mode()
246 return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; in meson_axg_set_phy_mode()
251 phy_intf_sel)); in meson_axg_set_phy_mode()
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| H A D | dwmac-anarion.c | 24 uint32_t phy_intf_sel; member
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
83 gmac->phy_intf_sel = GMAC_CONFIG_INTF_RGMII; in anarion_config_dt()
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| H A D | stmmac_main.c | 3175 int phy_intf_sel = -EINVAL; in stmmac_get_phy_intf_sel() local
3179 phy_intf_sel = PHY_INTF_SEL_GMII_MII; in stmmac_get_phy_intf_sel()
3181 phy_intf_sel = PHY_INTF_SEL_RGMII; in stmmac_get_phy_intf_sel()
3183 phy_intf_sel = PHY_INTF_SEL_RMII; in stmmac_get_phy_intf_sel()
3185 phy_intf_sel = PHY_INTF_SEL_REVMII; in stmmac_get_phy_intf_sel()
3187 return phy_intf_sel; in stmmac_get_phy_intf_sel()
3196 int phy_intf_sel, ret; in stmmac_prereset_configure() local
3207 phy_intf_sel = stmmac_integrated_pcs_get_phy_intf_sel(pcs, in stmmac_prereset_configure()
3210 phy_intf_sel = stmmac_get_phy_intf_sel(interface); in stmmac_prereset_configure()
3213 if (phy_intf_sel < 0) { in stmmac_prereset_configure()
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| /linux/include/linux/ |
| H A D | stmmac.h | 256 int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel);
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