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Searched refs:phase_offset (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/dpll/zl3073x/
H A Ddpll.c57 s64 phase_offset; member
404 void *dpll_priv, s64 *phase_offset, in zl3073x_dpll_input_pin_phase_offset_get() argument
428 *phase_offset = 0; in zl3073x_dpll_input_pin_phase_offset_get()
432 ref_phase = pin->phase_offset; in zl3073x_dpll_input_pin_phase_offset_get()
454 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; in zl3073x_dpll_input_pin_phase_offset_get()
1728 s64 phase_offset; in zl3073x_dpll_pin_phase_offset_check() local
1751 rc = zl3073x_read_u48(zldev, reg, &phase_offset); in zl3073x_dpll_pin_phase_offset_check()
1760 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); in zl3073x_dpll_pin_phase_offset_check()
1763 if (phase_offset != pin->phase_offset) { in zl3073x_dpll_pin_phase_offset_check()
1765 pin->label, pin->phase_offset, phase_offset); in zl3073x_dpll_pin_phase_offset_check()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h61 s64 phase_offset; member
96 s64 phase_offset; member
H A Dice_dpll.c1907 s64 *phase_offset, struct netlink_ext_ack *extack) in ice_dpll_phase_offset_get() argument
1916 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1918 *phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1920 *phase_offset = 0; in ice_dpll_phase_offset_get()
2635 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
2636 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
2706 s64 phase_offset, tmp; in ice_dpll_pps_update_phase_offsets() local
2723 phase_offset = 0; in ice_dpll_pps_update_phase_offsets()
2725 tmp = meas[i].phase_offset[j]; in ice_dpll_pps_update_phase_offsets()
2727 phase_offset += tmp << 8 * j; in ice_dpll_pps_update_phase_offsets()
[all …]
H A Dice_ptp_hw.h365 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
H A Dice_common.h305 u8 *dpll_state, u8 *config, s64 *phase_offset,
H A Dice_common.c5522 u8 *dpll_state, u8 *config, s64 *phase_offset, in ice_aq_get_cgu_dpll_status() argument
5538 *phase_offset = le32_to_cpu(cmd->phase_offset_h); in ice_aq_get_cgu_dpll_status()
5539 *phase_offset <<= 32; in ice_aq_get_cgu_dpll_status()
5540 *phase_offset += le32_to_cpu(cmd->phase_offset_l); in ice_aq_get_cgu_dpll_status()
5541 *phase_offset = sign_extend64(*phase_offset, 47); in ice_aq_get_cgu_dpll_status()
H A Dice_ptp_hw.c5810 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, in ice_get_cgu_state() argument
5826 if (phase_offset) in ice_get_cgu_state()
5827 *phase_offset = hw_phase_offset; in ice_get_cgu_state()
H A Dice_adminq_cmd.h2209 u8 phase_offset[ICE_CGU_INPUT_PHASE_OFFSET_BYTES]; member
/linux/include/linux/
H A Ddpll.h100 s64 *phase_offset,
/linux/drivers/dpll/
H A Ddpll_netlink.c357 s64 phase_offset; in dpll_msg_add_phase_offset() local
363 dpll, dpll_priv(dpll), &phase_offset, in dpll_msg_add_phase_offset()
367 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), in dpll_msg_add_phase_offset()
368 &phase_offset, DPLL_A_PIN_PAD)) in dpll_msg_add_phase_offset()