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Searched refs:pdiv (Results 1 – 25 of 36) sorted by relevance

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/linux/drivers/clk/tegra/
H A Dclk-tegra124.c153 { .pdiv = 1, .hw_val = 0 },
154 { .pdiv = 2, .hw_val = 1 },
155 { .pdiv = 3, .hw_val = 2 },
156 { .pdiv = 4, .hw_val = 3 },
157 { .pdiv = 5, .hw_val = 4 },
158 { .pdiv = 6, .hw_val = 5 },
159 { .pdiv = 8, .hw_val = 6 },
160 { .pdiv = 10, .hw_val = 7 },
161 { .pdiv = 12, .hw_val = 8 },
162 { .pdiv = 16, .hw_val = 9 },
[all …]
H A Dclk-tegra210.c1465 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); in tegra210_pllx_dyn_ramp()
1486 u32 pdiv; in tegra210_pll_fixed_mdiv_cfg() local
1493 p = params->round_p_to_pdiv(p, &pdiv); in tegra210_pll_fixed_mdiv_cfg()
1580 { .pdiv = 1, .hw_val = 0 },
1581 { .pdiv = 2, .hw_val = 1 },
1582 { .pdiv = 3, .hw_val = 2 },
1583 { .pdiv = 4, .hw_val = 3 },
1584 { .pdiv = 5, .hw_val = 4 },
1585 { .pdiv = 6, .hw_val = 5 },
1586 { .pdiv = 8, .hw_val = 6 },
[all …]
H A Dclk-pll.c486 while (p_tohw->pdiv) { in _p_div_to_hw()
487 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
507 while (p_tohw->pdiv) { in _hw_to_p_div()
509 return p_tohw->pdiv; in _hw_to_p_div()
875 int pdiv; in clk_pll_recalc_rate() local
898 pdiv = 1; in clk_pll_recalc_rate()
900 pdiv = _hw_to_p_div(hw, cfg.p); in clk_pll_recalc_rate()
901 if (pdiv < 0) { in clk_pll_recalc_rate()
904 pdiv = 1; in clk_pll_recalc_rate()
911 cfg.m *= pdiv; in clk_pll_recalc_rate()
[all …]
/linux/drivers/clk/samsung/
H A Dclk-pll.c137 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
142 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()
146 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
170 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
175 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()
179 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
208 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
213 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; in samsung_pll35xx_recalc_rate()
217 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
230 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
H A Dclk-pll.h66 .pdiv = (_p), \
75 .pdiv = (_p), \
85 .pdiv = (_p), \
95 .pdiv = (_p), \
106 .pdiv = (_p), \
118 unsigned int pdiv; member
/linux/drivers/clk/imx/
H A Dclk-pll14xx.c106 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
113 pdiv *= 65536; in pll14xx_calc_rate()
115 do_div(fout, pdiv << sdiv); in pll14xx_calc_rate()
120 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, in pll1443x_calc_kdiv() argument
126 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
135 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
158 t->pdiv = tt->pdiv; in imx_pll14xx_calc_settings()
166 pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
171 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); in imx_pll14xx_calc_settings()
172 rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); in imx_pll14xx_calc_settings()
[all …]
H A Dclk.h59 unsigned int pdiv; member
267 .pdiv = (_p), \
275 .pdiv = (_p), \
/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c104 vco_out->pdiv = 1; in pll_calc_param()
282 unsigned int pdiv; in pll_fractional_change_only() local
296 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_fractional_change_only()
297 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in pll_fractional_change_only()
299 if (pdiv != vco->pdiv) in pll_fractional_change_only()
321 if (vco->pdiv == 0) in pll_set_rate()
324 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
411 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_set_rate()
412 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); in pll_set_rate()
413 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
[all …]
H A Dclk-iproc-armpll.c192 unsigned int pdiv; in iproc_arm_pll_recalc_rate() local
208 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & in iproc_arm_pll_recalc_rate()
210 if (pdiv == 0) in iproc_arm_pll_recalc_rate()
211 pdiv = 16; in iproc_arm_pll_recalc_rate()
220 pll->rate = (pll->rate / pdiv) / mdiv; in iproc_arm_pll_recalc_rate()
225 (unsigned int)(ndiv >> 20), pdiv, mdiv); in iproc_arm_pll_recalc_rate()
H A Dclk-sr.c43 .pdiv = REG_VAL(0x14, 0, 4),
103 .pdiv = REG_VAL(0x14, 0, 4),
162 .pdiv = REG_VAL(0x14, 0, 4),
197 .pdiv = REG_VAL(0x14, 0, 4),
251 .pdiv = REG_VAL(0x14, 0, 4),
287 .pdiv = REG_VAL(0x4, 26, 4),
332 .pdiv = REG_VAL(0x4, 26, 4),
371 .pdiv = REG_VAL(0x4, 26, 4),
H A Dclk-ns2.c37 .pdiv = REG_VAL(0x8, 0, 4),
100 .pdiv = REG_VAL(0x8, 0, 4),
162 .pdiv = REG_VAL(0x8, 0, 4),
224 .pdiv = REG_VAL(0x8, 0, 4),
H A Dclk-cygnus.c56 .pdiv = REG_VAL(0x14, 0, 4),
114 .pdiv = REG_VAL(0x4, 26, 4),
192 .pdiv = REG_VAL(0x14, 0, 4),
271 .pdiv = REG_VAL(0x44, 0, 4),
H A Dclk-iproc.h88 unsigned int pdiv; member
164 struct iproc_clk_reg_op pdiv; member
H A Dclk-nsp.c42 .pdiv = REG_VAL(0x18, 24, 3),
99 .pdiv = REG_VAL(0x4, 28, 3),
H A Dclk-bcm2835.c561 u32 ndiv, u32 fdiv, u32 pdiv) in bcm2835_pll_rate_from_divisors() argument
565 if (pdiv == 0) in bcm2835_pll_rate_from_divisors()
569 do_div(rate, pdiv); in bcm2835_pll_rate_from_divisors()
599 u32 ndiv, pdiv, fdiv; in bcm2835_pll_get_rate() local
607 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; in bcm2835_pll_get_rate()
616 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); in bcm2835_pll_get_rate()
/linux/drivers/clk/
H A Dclk-cdce925.c54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ member
276 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) in cdce925_clk_set_pdiv() argument
282 0x03, (pdiv >> 8) & 0x03); in cdce925_clk_set_pdiv()
283 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
286 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
289 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
292 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
295 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
298 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
301 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
[all …]
H A Dclk-ep93xx.c240 int div, pdiv; in ep93xx_mux_determine_rate() local
259 for (pdiv = 4; pdiv <= 6; pdiv++) { in ep93xx_mux_determine_rate()
260 div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); in ep93xx_mux_determine_rate()
264 actual_rate = DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); in ep93xx_mux_determine_rate()
288 unsigned int pdiv, div; in ep93xx_ddiv_recalc_rate() local
292 pdiv = (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0); in ep93xx_ddiv_recalc_rate()
297 return DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div); in ep93xx_ddiv_recalc_rate()
305 int pdiv, div, npdiv, ndiv; in ep93xx_ddiv_set_rate() local
312 for (pdiv = 4; pdiv <= 6; pdiv++) { in ep93xx_ddiv_set_rate()
313 div = DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); in ep93xx_ddiv_set_rate()
[all …]
/linux/drivers/thermal/tegra/
H A Dtegra132-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
H A Dtegra114-soctherm.c42 .pdiv = 10,
61 .pdiv = 10,
80 .pdiv = 10,
97 .pdiv = 10,
H A Dtegra210-soctherm.c52 .pdiv = 8,
71 .pdiv = 8,
90 .pdiv = 8,
107 .pdiv = 8,
H A Dtegra124-soctherm.c51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
H A Dsoctherm.h80 u32 pdiv, pdiv_ate, pdiv_mask; member
92 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; member
H A Dsoctherm-fuse.c140 mult = sensor_group->pdiv * sensor->config->tsample_ate; in tegra_calc_tsensor_calib()
/linux/drivers/clk/st/
H A Dclk-flexgen.c39 struct clk_divider pdiv; member
143 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
159 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
244 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
245 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
246 fgxbar->pdiv.width = 10; in clk_register_flexgen()
/linux/drivers/cpufreq/
H A Dbrcmstb-avs-cpufreq.c341 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, in brcm_avs_parse_p1() argument
345 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; in brcm_avs_parse_p1()
686 unsigned int ndiv, pdiv; in show_brcm_avs_pmap() local
692 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); in show_brcm_avs_pmap()
696 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, in show_brcm_avs_pmap()

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