1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/align.h> 6 #include <linux/bitfield.h> 7 #include <linux/pci.h> 8 #include <trace/events/pci.h> 9 10 struct pcie_tlp_log; 11 12 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 13 #define MAX_NR_DEVFNS 256 14 #define PCI_MAX_NR_DEVS 32 15 16 #define MAX_NR_LANES 16 17 18 #define PCI_FIND_CAP_TTL 48 19 20 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 21 22 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 23 24 /* 25 * Power stable to PERST# inactive. 26 * 27 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 28 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 29 * "T_PVPERL". 30 */ 31 #define PCIE_T_PVPERL_MS 100 32 33 /* 34 * REFCLK stable before PERST# inactive. 35 * 36 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 37 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 38 * "T_PERST-CLK". 39 */ 40 #define PCIE_T_PERST_CLK_US 100 41 42 /* 43 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 44 * Recommends 1ms to 10ms timeout to check L2 ready. 45 */ 46 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 47 48 /* 49 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 50 * 51 * - "With a Downstream Port that does not support Link speeds greater 52 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 53 * from a Conventional Reset before sending a Configuration Request to 54 * the device immediately below that Port." 55 * 56 * - "With a Downstream Port that supports Link speeds greater than 57 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 58 * completes before sending a Configuration Request to the device 59 * immediately below that Port." 60 */ 61 #define PCIE_RESET_CONFIG_WAIT_MS 100 62 63 /* Parameters for the waiting for link up routine */ 64 #define PCIE_LINK_WAIT_MAX_RETRIES 10 65 #define PCIE_LINK_WAIT_SLEEP_MS 90 66 67 /* Format of TLP; PCIe r7.0, sec 2.2.1 */ 68 #define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ 69 #define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */ 70 #define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */ 71 #define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */ 72 73 /* Type of TLP; PCIe r7.0, sec 2.2.1 */ 74 #define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */ 75 #define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */ 76 #define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */ 77 #define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */ 78 79 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 80 #define PCIE_MSG_TYPE_R_RC 0 81 #define PCIE_MSG_TYPE_R_ADDR 1 82 #define PCIE_MSG_TYPE_R_ID 2 83 #define PCIE_MSG_TYPE_R_BC 3 84 #define PCIE_MSG_TYPE_R_LOCAL 4 85 #define PCIE_MSG_TYPE_R_GATHER 5 86 87 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 88 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 89 90 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 91 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 92 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 93 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 94 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 95 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 96 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 97 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 98 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 99 100 /* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */ 101 #define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */ 102 103 #define PCI_BUS_BRIDGE_IO_WINDOW 0 104 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 105 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 106 107 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 108 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 109 110 extern const unsigned char pcie_link_speed[]; 111 unsigned char pcie_get_link_speed(unsigned int speed); 112 113 extern bool pci_early_dump; 114 115 extern struct mutex pci_rescan_remove_lock; 116 117 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 118 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 119 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 120 121 /* Standard Capability finder */ 122 /** 123 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 124 * @read_cfg: Function pointer for reading PCI config space 125 * @start: Starting position to begin search 126 * @cap: Capability ID to find 127 * @prev_ptr: Pointer to store position of preceding capability (optional) 128 * @args: Arguments to pass to read_cfg function 129 * 130 * Search the capability list in PCI config space to find @cap. If 131 * found, update *prev_ptr with the position of the preceding capability 132 * (if prev_ptr != NULL) 133 * Implements TTL (time-to-live) protection against infinite loops. 134 * 135 * Return: Position of the capability if found, 0 otherwise. 136 */ 137 #define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 138 ({ \ 139 int __ttl = PCI_FIND_CAP_TTL; \ 140 u8 __id, __found_pos = 0; \ 141 u8 __prev_pos = (start); \ 142 u8 __pos = (start); \ 143 u16 __ent; \ 144 \ 145 read_cfg##_byte(args, __pos, &__pos); \ 146 \ 147 while (__ttl--) { \ 148 if (__pos < PCI_STD_HEADER_SIZEOF) \ 149 break; \ 150 \ 151 __pos = ALIGN_DOWN(__pos, 4); \ 152 read_cfg##_word(args, __pos, &__ent); \ 153 \ 154 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 155 if (__id == 0xff) \ 156 break; \ 157 \ 158 if (__id == (cap)) { \ 159 __found_pos = __pos; \ 160 if (prev_ptr != NULL) \ 161 *(u8 *)prev_ptr = __prev_pos; \ 162 break; \ 163 } \ 164 \ 165 __prev_pos = __pos; \ 166 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 167 } \ 168 __found_pos; \ 169 }) 170 171 /* Extended Capability finder */ 172 /** 173 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 174 * @read_cfg: Function pointer for reading PCI config space 175 * @start: Starting position to begin search (0 for initial search) 176 * @cap: Extended capability ID to find 177 * @prev_ptr: Pointer to store position of preceding capability (optional) 178 * @args: Arguments to pass to read_cfg function 179 * 180 * Search the extended capability list in PCI config space to find @cap. 181 * If found, update *prev_ptr with the position of the preceding capability 182 * (if prev_ptr != NULL) 183 * Implements TTL protection against infinite loops using a calculated 184 * maximum search count. 185 * 186 * Return: Position of the capability if found, 0 otherwise. 187 */ 188 #define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 189 ({ \ 190 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 191 u16 __found_pos = 0; \ 192 u16 __prev_pos; \ 193 int __ttl, __ret; \ 194 u32 __header; \ 195 \ 196 __prev_pos = __pos; \ 197 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 198 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 199 __ret = read_cfg##_dword(args, __pos, &__header); \ 200 if (__ret != PCIBIOS_SUCCESSFUL) \ 201 break; \ 202 \ 203 if (__header == 0) \ 204 break; \ 205 \ 206 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 207 __found_pos = __pos; \ 208 if (prev_ptr != NULL) \ 209 *(u16 *)prev_ptr = __prev_pos; \ 210 break; \ 211 } \ 212 \ 213 __prev_pos = __pos; \ 214 __pos = PCI_EXT_CAP_NEXT(__header); \ 215 } \ 216 __found_pos; \ 217 }) 218 219 /* Functions internal to the PCI core code */ 220 221 #ifdef CONFIG_DMI 222 extern const struct attribute_group pci_dev_smbios_attr_group; 223 #endif 224 225 enum pci_mmap_api { 226 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 227 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 228 }; 229 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 230 enum pci_mmap_api mmap_api); 231 232 bool pci_reset_supported(struct pci_dev *dev); 233 void pci_init_reset_methods(struct pci_dev *dev); 234 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 235 int pci_bus_error_reset(struct pci_dev *dev); 236 int pci_try_reset_bridge(struct pci_dev *bridge); 237 238 struct pci_cap_saved_data { 239 u16 cap_nr; 240 bool cap_extended; 241 unsigned int size; 242 u32 data[]; 243 }; 244 245 struct pci_cap_saved_state { 246 struct hlist_node next; 247 struct pci_cap_saved_data cap; 248 }; 249 250 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 251 void pci_free_cap_save_buffers(struct pci_dev *dev); 252 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 253 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 254 u16 cap, unsigned int size); 255 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 256 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 257 u16 cap); 258 259 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 260 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 261 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 262 263 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 264 void pci_refresh_power_state(struct pci_dev *dev); 265 int pci_power_up(struct pci_dev *dev); 266 void pci_disable_enabled_device(struct pci_dev *dev); 267 int pci_finish_runtime_suspend(struct pci_dev *dev); 268 void pcie_clear_device_status(struct pci_dev *dev); 269 void pcie_clear_root_pme_status(struct pci_dev *dev); 270 bool pci_check_pme_status(struct pci_dev *dev); 271 void pci_pme_wakeup_bus(struct pci_bus *bus); 272 void pci_pme_restore(struct pci_dev *dev); 273 bool pci_dev_need_resume(struct pci_dev *dev); 274 void pci_dev_adjust_pme(struct pci_dev *dev); 275 void pci_dev_complete_resume(struct pci_dev *pci_dev); 276 void pci_config_pm_runtime_get(struct pci_dev *dev); 277 void pci_config_pm_runtime_put(struct pci_dev *dev); 278 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 279 void pci_pm_init(struct pci_dev *dev); 280 void pci_ea_init(struct pci_dev *dev); 281 bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); 282 void pci_msi_init(struct pci_dev *dev); 283 void pci_msix_init(struct pci_dev *dev); 284 bool pci_bridge_d3_possible(struct pci_dev *dev); 285 void pci_bridge_d3_update(struct pci_dev *dev); 286 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 287 288 static inline bool pci_bus_rrs_vendor_id(u32 l) 289 { 290 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 291 } 292 293 static inline void pci_wakeup_event(struct pci_dev *dev) 294 { 295 /* Wait 100 ms before the system can be put into a sleep state. */ 296 pm_wakeup_event(&dev->dev, 100); 297 } 298 299 /** 300 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 301 * @bar: BAR index 302 * 303 * Protects against overflowing &struct pci_dev.resource array. 304 * 305 * Return: true for valid index, false otherwise. 306 */ 307 static inline bool pci_bar_index_is_valid(int bar) 308 { 309 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 310 return true; 311 312 return false; 313 } 314 315 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 316 { 317 return !!(pci_dev->subordinate); 318 } 319 320 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 321 { 322 /* 323 * Currently we allow normal PCI devices and PCI bridges transition 324 * into D3 if their bridge_d3 is set. 325 */ 326 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 327 } 328 329 static inline bool pcie_downstream_port(const struct pci_dev *dev) 330 { 331 int type = pci_pcie_type(dev); 332 333 return type == PCI_EXP_TYPE_ROOT_PORT || 334 type == PCI_EXP_TYPE_DOWNSTREAM || 335 type == PCI_EXP_TYPE_PCIE_BRIDGE; 336 } 337 338 void pci_vpd_init(struct pci_dev *dev); 339 extern const struct attribute_group pci_dev_vpd_attr_group; 340 341 /* PCI Virtual Channel */ 342 int pci_save_vc_state(struct pci_dev *dev); 343 void pci_restore_vc_state(struct pci_dev *dev); 344 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 345 346 /* PCI /proc functions */ 347 #ifdef CONFIG_PROC_FS 348 int pci_proc_attach_device(struct pci_dev *dev); 349 int pci_proc_detach_device(struct pci_dev *dev); 350 int pci_proc_detach_bus(struct pci_bus *bus); 351 #else 352 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 353 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 354 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 355 #endif 356 357 /* Functions for PCI Hotplug drivers to use */ 358 int pci_hp_add_bridge(struct pci_dev *dev); 359 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 360 361 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 362 void pci_create_legacy_files(struct pci_bus *bus); 363 void pci_remove_legacy_files(struct pci_bus *bus); 364 #else 365 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 366 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 367 #endif 368 369 /* Lock for read/write access to pci device and bus lists */ 370 extern struct rw_semaphore pci_bus_sem; 371 extern struct mutex pci_slot_mutex; 372 373 extern raw_spinlock_t pci_lock; 374 375 extern unsigned int pci_pm_d3hot_delay; 376 377 #ifdef CONFIG_PCI_MSI 378 void pci_no_msi(void); 379 #else 380 static inline void pci_no_msi(void) { } 381 #endif 382 383 void pci_realloc_get_opt(char *); 384 385 static inline int pci_no_d1d2(struct pci_dev *dev) 386 { 387 unsigned int parent_dstates = 0; 388 389 if (dev->bus->self) 390 parent_dstates = dev->bus->self->no_d1d2; 391 return (dev->no_d1d2 || parent_dstates); 392 393 } 394 395 #ifdef CONFIG_SYSFS 396 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 397 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 398 extern const struct attribute_group *pci_dev_groups[]; 399 extern const struct attribute_group *pci_dev_attr_groups[]; 400 extern const struct attribute_group *pcibus_groups[]; 401 extern const struct attribute_group *pci_bus_groups[]; 402 extern const struct attribute_group pci_doe_sysfs_group; 403 #else 404 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 405 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 406 #define pci_dev_groups NULL 407 #define pci_dev_attr_groups NULL 408 #define pcibus_groups NULL 409 #define pci_bus_groups NULL 410 #endif 411 412 extern unsigned long pci_hotplug_io_size; 413 extern unsigned long pci_hotplug_mmio_size; 414 extern unsigned long pci_hotplug_mmio_pref_size; 415 extern unsigned long pci_hotplug_bus_size; 416 417 static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) 418 { 419 return dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 420 } 421 #ifdef CONFIG_CARDBUS 422 unsigned long pci_cardbus_resource_alignment(struct resource *res); 423 int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 424 struct list_head *realloc_head); 425 int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 426 u32 buses, int max, 427 unsigned int available_buses, int pass); 428 int pci_setup_cardbus(char *str); 429 430 #else 431 static inline unsigned long pci_cardbus_resource_alignment(struct resource *res) 432 { 433 return 0; 434 } 435 static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 436 struct list_head *realloc_head) 437 { 438 return -EOPNOTSUPP; 439 } 440 static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, 441 struct pci_dev *dev, 442 u32 buses, int max, 443 unsigned int available_buses, 444 int pass) 445 { 446 return max; 447 } 448 static inline int pci_setup_cardbus(char *str) { return -ENOENT; } 449 #endif /* CONFIG_CARDBUS */ 450 451 /** 452 * pci_match_one_device - Tell if a PCI device structure has a matching 453 * PCI device id structure 454 * @id: single PCI device id structure to match 455 * @dev: the PCI device structure to match against 456 * 457 * Returns the matching pci_device_id structure or %NULL if there is no match. 458 */ 459 static inline const struct pci_device_id * 460 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 461 { 462 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 463 (id->device == PCI_ANY_ID || id->device == dev->device) && 464 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 465 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 466 !((id->class ^ dev->class) & id->class_mask)) 467 return id; 468 return NULL; 469 } 470 471 /* PCI slot sysfs helper code */ 472 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 473 474 extern struct kset *pci_slots_kset; 475 476 struct pci_slot_attribute { 477 struct attribute attr; 478 ssize_t (*show)(struct pci_slot *, char *); 479 ssize_t (*store)(struct pci_slot *, const char *, size_t); 480 }; 481 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 482 483 enum pci_bar_type { 484 pci_bar_unknown, /* Standard PCI BAR probe */ 485 pci_bar_io, /* An I/O port BAR */ 486 pci_bar_mem32, /* A 32-bit memory BAR */ 487 pci_bar_mem64, /* A 64-bit memory BAR */ 488 }; 489 490 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 491 void pci_put_host_bridge_device(struct device *dev); 492 493 void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 494 int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 495 int exclude_bars); 496 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 497 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 498 499 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 500 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 501 int rrs_timeout); 502 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 503 int rrs_timeout); 504 505 int pci_setup_device(struct pci_dev *dev); 506 void __pci_size_stdbars(struct pci_dev *dev, int count, 507 unsigned int pos, u32 *sizes); 508 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 509 struct resource *res, unsigned int reg, u32 *sizes); 510 void pci_configure_ari(struct pci_dev *dev); 511 512 int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 513 struct resource *res, resource_size_t add_size, 514 resource_size_t min_align); 515 void __pci_bus_size_bridges(struct pci_bus *bus, 516 struct list_head *realloc_head); 517 void __pci_bus_assign_resources(const struct pci_bus *bus, 518 struct list_head *realloc_head, 519 struct list_head *fail_head); 520 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 521 void pci_walk_bus_locked(struct pci_bus *top, 522 int (*cb)(struct pci_dev *, void *), 523 void *userdata); 524 525 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 526 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 527 static inline bool pci_resource_is_bridge_win(int resno) 528 { 529 return resno >= PCI_BRIDGE_RESOURCES && 530 resno <= PCI_BRIDGE_RESOURCE_END; 531 } 532 533 /** 534 * pci_resource_num - Reverse lookup resource number from device resources 535 * @dev: PCI device 536 * @res: Resource to lookup index for (MUST be a @dev's resource) 537 * 538 * Perform reverse lookup to determine the resource number for @res within 539 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 540 * among @dev's resources! 541 * 542 * Returns: resource number. 543 */ 544 static inline int pci_resource_num(const struct pci_dev *dev, 545 const struct resource *res) 546 { 547 int resno = res - &dev->resource[0]; 548 549 /* Passing a resource that is not among dev's resources? */ 550 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 551 552 return resno; 553 } 554 555 void pbus_validate_busn(struct pci_bus *bus); 556 struct resource *pbus_select_window(struct pci_bus *bus, 557 const struct resource *res); 558 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 559 void pci_disable_bridge_window(struct pci_dev *dev); 560 struct pci_bus *pci_bus_get(struct pci_bus *bus); 561 void pci_bus_put(struct pci_bus *bus); 562 563 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 564 ({ \ 565 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 566 \ 567 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 568 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 569 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 570 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 571 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 572 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 573 PCI_SPEED_UNKNOWN); \ 574 }) 575 576 /* PCIe link information from Link Capabilities 2 */ 577 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 578 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 579 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 580 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 581 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 582 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 583 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 584 PCI_SPEED_UNKNOWN) 585 586 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 587 ({ \ 588 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 589 \ 590 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 591 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 592 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 593 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 594 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 595 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 596 PCI_SPEED_UNKNOWN); \ 597 }) 598 599 /* PCIe speed to Mb/s reduced by encoding overhead */ 600 #define PCIE_SPEED2MBS_ENC(speed) \ 601 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 602 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 603 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 604 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 605 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 606 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 607 0) 608 609 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 610 { 611 switch (speed) { 612 case PCIE_SPEED_2_5GT: 613 return 2500; 614 case PCIE_SPEED_5_0GT: 615 return 5000; 616 case PCIE_SPEED_8_0GT: 617 return 8000; 618 case PCIE_SPEED_16_0GT: 619 return 16000; 620 case PCIE_SPEED_32_0GT: 621 return 32000; 622 case PCIE_SPEED_64_0GT: 623 return 64000; 624 default: 625 break; 626 } 627 628 return -EINVAL; 629 } 630 631 u8 pcie_get_supported_speeds(struct pci_dev *dev); 632 const char *pci_speed_string(enum pci_bus_speed speed); 633 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 634 void pcie_report_downtraining(struct pci_dev *dev); 635 636 enum pcie_link_change_reason { 637 PCIE_LINK_RETRAIN, 638 PCIE_ADD_BUS, 639 PCIE_BWCTRL_ENABLE, 640 PCIE_BWCTRL_IRQ, 641 PCIE_HOTPLUG, 642 }; 643 644 static inline void __pcie_update_link_speed(struct pci_bus *bus, 645 enum pcie_link_change_reason reason, 646 u16 linksta, u16 linksta2) 647 { 648 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 649 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 650 651 trace_pcie_link_event(bus, 652 reason, 653 FIELD_GET(PCI_EXP_LNKSTA_NLW, linksta), 654 linksta & PCI_EXP_LNKSTA_LINK_STATUS_MASK); 655 } 656 657 void pcie_update_link_speed(struct pci_bus *bus, enum pcie_link_change_reason reason); 658 659 /* Single Root I/O Virtualization */ 660 struct pci_sriov { 661 int pos; /* Capability position */ 662 int nres; /* Number of resources */ 663 u32 cap; /* SR-IOV Capabilities */ 664 u16 ctrl; /* SR-IOV Control */ 665 u16 total_VFs; /* Total VFs associated with the PF */ 666 u16 initial_VFs; /* Initial VFs associated with the PF */ 667 u16 num_VFs; /* Number of VFs available */ 668 u16 offset; /* First VF Routing ID offset */ 669 u16 stride; /* Following VF stride */ 670 u16 vf_device; /* VF device ID */ 671 u32 pgsz; /* Page size for BAR alignment */ 672 u8 link; /* Function Dependency Link */ 673 u8 max_VF_buses; /* Max buses consumed by VFs */ 674 u16 driver_max_VFs; /* Max num VFs driver supports */ 675 struct pci_dev *dev; /* Lowest numbered PF */ 676 struct pci_dev *self; /* This PF */ 677 u32 class; /* VF device */ 678 u8 hdr_type; /* VF header type */ 679 u16 subsystem_vendor; /* VF subsystem vendor */ 680 u16 subsystem_device; /* VF subsystem device */ 681 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 682 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 683 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 684 }; 685 686 #ifdef CONFIG_PCI_DOE 687 void pci_doe_init(struct pci_dev *pdev); 688 void pci_doe_destroy(struct pci_dev *pdev); 689 void pci_doe_disconnected(struct pci_dev *pdev); 690 #else 691 static inline void pci_doe_init(struct pci_dev *pdev) { } 692 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 693 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 694 #endif 695 696 #ifdef CONFIG_PCI_NPEM 697 void pci_npem_create(struct pci_dev *dev); 698 void pci_npem_remove(struct pci_dev *dev); 699 #else 700 static inline void pci_npem_create(struct pci_dev *dev) { } 701 static inline void pci_npem_remove(struct pci_dev *dev) { } 702 #endif 703 704 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 705 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 706 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 707 #else 708 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 709 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 710 #endif 711 712 #ifdef CONFIG_PCI_IDE 713 void pci_ide_init(struct pci_dev *dev); 714 void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 715 void pci_ide_destroy(struct pci_dev *dev); 716 extern const struct attribute_group pci_ide_attr_group; 717 #else 718 static inline void pci_ide_init(struct pci_dev *dev) { } 719 static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 720 static inline void pci_ide_destroy(struct pci_dev *dev) { } 721 #endif 722 723 #ifdef CONFIG_PCI_TSM 724 void pci_tsm_init(struct pci_dev *pdev); 725 void pci_tsm_destroy(struct pci_dev *pdev); 726 extern const struct attribute_group pci_tsm_attr_group; 727 extern const struct attribute_group pci_tsm_auth_attr_group; 728 #else 729 static inline void pci_tsm_init(struct pci_dev *pdev) { } 730 static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 731 #endif 732 733 /** 734 * pci_dev_set_io_state - Set the new error state if possible. 735 * 736 * @dev: PCI device to set new error_state 737 * @new: the state we want dev to be in 738 * 739 * If the device is experiencing perm_failure, it has to remain in that state. 740 * Any other transition is allowed. 741 * 742 * Returns true if state has been changed to the requested state. 743 */ 744 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 745 pci_channel_state_t new) 746 { 747 pci_channel_state_t old; 748 749 switch (new) { 750 case pci_channel_io_perm_failure: 751 xchg(&dev->error_state, pci_channel_io_perm_failure); 752 return true; 753 case pci_channel_io_frozen: 754 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 755 pci_channel_io_frozen); 756 return old != pci_channel_io_perm_failure; 757 case pci_channel_io_normal: 758 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 759 pci_channel_io_normal); 760 return old != pci_channel_io_perm_failure; 761 default: 762 return false; 763 } 764 } 765 766 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 767 { 768 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 769 pci_doe_disconnected(dev); 770 771 return 0; 772 } 773 774 /* pci_dev priv_flags */ 775 #define PCI_DEV_ADDED 0 776 #define PCI_DPC_RECOVERED 1 777 #define PCI_DPC_RECOVERING 2 778 #define PCI_DEV_REMOVED 3 779 #define PCI_LINK_CHANGED 4 780 #define PCI_LINK_CHANGING 5 781 #define PCI_LINK_LBMS_SEEN 6 782 #define PCI_DEV_ALLOW_BINDING 7 783 784 static inline void pci_dev_assign_added(struct pci_dev *dev) 785 { 786 smp_mb__before_atomic(); 787 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 788 smp_mb__after_atomic(); 789 } 790 791 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 792 { 793 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 794 } 795 796 static inline bool pci_dev_is_added(const struct pci_dev *dev) 797 { 798 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 799 } 800 801 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 802 { 803 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 804 } 805 806 static inline void pci_dev_allow_binding(struct pci_dev *dev) 807 { 808 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 809 } 810 811 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 812 { 813 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 814 } 815 816 #ifdef CONFIG_PCIEAER 817 #include <linux/aer.h> 818 819 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 820 821 /** 822 * struct aer_err_info - AER Error Information 823 * @dev: Devices reporting error 824 * @ratelimit_print: Flag to log or not log the devices' error. 0=NotLog/1=Log 825 * @__pad1: Padding for alignment 826 * @error_dev_num: Number of devices reporting an error 827 * @level: printk level to use in logging 828 * @id: Value from register PCI_ERR_ROOT_ERR_SRC 829 * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR 830 * @root_ratelimit_print: Flag to log or not log the root's error. 0=NotLog/1=Log 831 * @multi_error_valid: If multiple errors are reported 832 * @first_error: First reported error 833 * @__pad2: Padding for alignment 834 * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error 835 * @tlp_header_valid: Indicates if TLP field contains error information 836 * @status: COR/UNCOR error status 837 * @mask: COR/UNCOR mask 838 * @tlp: Transaction packet information 839 */ 840 struct aer_err_info { 841 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 842 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 843 int error_dev_num; 844 const char *level; 845 846 unsigned int id:16; 847 848 unsigned int severity:2; 849 unsigned int root_ratelimit_print:1; 850 unsigned int __pad1:4; 851 unsigned int multi_error_valid:1; 852 853 unsigned int first_error:5; 854 unsigned int __pad2:1; 855 unsigned int is_cxl:1; 856 unsigned int tlp_header_valid:1; 857 858 unsigned int status; 859 unsigned int mask; 860 struct pcie_tlp_log tlp; 861 }; 862 863 int aer_get_device_error_info(struct aer_err_info *info, int i); 864 void aer_print_error(struct aer_err_info *info, int i); 865 866 static inline const char *aer_err_bus(struct aer_err_info *info) 867 { 868 return info->is_cxl ? "CXL" : "PCIe"; 869 } 870 871 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 872 unsigned int tlp_len, bool flit, 873 struct pcie_tlp_log *log); 874 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 875 void pcie_print_tlp_log(const struct pci_dev *dev, 876 const struct pcie_tlp_log *log, const char *level, 877 const char *pfx); 878 #endif /* CONFIG_PCIEAER */ 879 880 #ifdef CONFIG_PCIEPORTBUS 881 /* Cached RCEC Endpoint Association */ 882 struct rcec_ea { 883 u8 nextbusn; 884 u8 lastbusn; 885 u32 bitmap; 886 }; 887 #endif 888 889 #ifdef CONFIG_PCIE_DPC 890 void pci_save_dpc_state(struct pci_dev *dev); 891 void pci_restore_dpc_state(struct pci_dev *dev); 892 void pci_dpc_init(struct pci_dev *pdev); 893 void dpc_process_error(struct pci_dev *pdev); 894 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 895 bool pci_dpc_recovered(struct pci_dev *pdev); 896 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 897 #else 898 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 899 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 900 static inline void pci_dpc_init(struct pci_dev *pdev) { } 901 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 902 #endif 903 904 #ifdef CONFIG_PCIEPORTBUS 905 void pci_rcec_init(struct pci_dev *dev); 906 void pci_rcec_exit(struct pci_dev *dev); 907 void pcie_link_rcec(struct pci_dev *rcec); 908 void pcie_walk_rcec(struct pci_dev *rcec, 909 int (*cb)(struct pci_dev *, void *), 910 void *userdata); 911 #else 912 static inline void pci_rcec_init(struct pci_dev *dev) { } 913 static inline void pci_rcec_exit(struct pci_dev *dev) { } 914 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 915 static inline void pcie_walk_rcec(struct pci_dev *rcec, 916 int (*cb)(struct pci_dev *, void *), 917 void *userdata) { } 918 #endif 919 920 #ifdef CONFIG_PCI_ATS 921 /* Address Translation Service */ 922 void pci_ats_init(struct pci_dev *dev); 923 void pci_restore_ats_state(struct pci_dev *dev); 924 #else 925 static inline void pci_ats_init(struct pci_dev *d) { } 926 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 927 #endif /* CONFIG_PCI_ATS */ 928 929 #ifdef CONFIG_PCI_PRI 930 void pci_pri_init(struct pci_dev *dev); 931 void pci_restore_pri_state(struct pci_dev *pdev); 932 #else 933 static inline void pci_pri_init(struct pci_dev *dev) { } 934 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 935 #endif 936 937 #ifdef CONFIG_PCI_PASID 938 void pci_pasid_init(struct pci_dev *dev); 939 void pci_restore_pasid_state(struct pci_dev *pdev); 940 #else 941 static inline void pci_pasid_init(struct pci_dev *dev) { } 942 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 943 #endif 944 945 #ifdef CONFIG_PCI_IOV 946 int pci_iov_init(struct pci_dev *dev); 947 void pci_iov_release(struct pci_dev *dev); 948 void pci_iov_remove(struct pci_dev *dev); 949 void pci_iov_update_resource(struct pci_dev *dev, int resno); 950 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 951 void pci_restore_iov_state(struct pci_dev *dev); 952 int pci_iov_bus_range(struct pci_bus *bus); 953 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 954 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 955 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 956 { 957 if (!dev->is_physfn) 958 return 0; 959 960 return dev->sriov->vf_rebar_cap; 961 } 962 static inline bool pci_resource_is_iov(int resno) 963 { 964 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 965 } 966 static inline int pci_resource_num_from_vf_bar(int resno) 967 { 968 return resno + PCI_IOV_RESOURCES; 969 } 970 static inline int pci_resource_num_to_vf_bar(int resno) 971 { 972 return resno - PCI_IOV_RESOURCES; 973 } 974 extern const struct attribute_group sriov_pf_dev_attr_group; 975 extern const struct attribute_group sriov_vf_dev_attr_group; 976 #else 977 static inline int pci_iov_init(struct pci_dev *dev) 978 { 979 return -ENODEV; 980 } 981 static inline void pci_iov_release(struct pci_dev *dev) { } 982 static inline void pci_iov_remove(struct pci_dev *dev) { } 983 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 984 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 985 int resno) 986 { 987 return 0; 988 } 989 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 990 static inline int pci_iov_bus_range(struct pci_bus *bus) 991 { 992 return 0; 993 } 994 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 995 int size) { } 996 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 997 { 998 return false; 999 } 1000 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 1001 { 1002 return 0; 1003 } 1004 static inline bool pci_resource_is_iov(int resno) 1005 { 1006 return false; 1007 } 1008 static inline int pci_resource_num_from_vf_bar(int resno) 1009 { 1010 WARN_ON_ONCE(1); 1011 return -ENODEV; 1012 } 1013 static inline int pci_resource_num_to_vf_bar(int resno) 1014 { 1015 WARN_ON_ONCE(1); 1016 return -ENODEV; 1017 } 1018 #endif /* CONFIG_PCI_IOV */ 1019 1020 #ifdef CONFIG_PCIE_TPH 1021 void pci_restore_tph_state(struct pci_dev *dev); 1022 void pci_save_tph_state(struct pci_dev *dev); 1023 void pci_no_tph(void); 1024 void pci_tph_init(struct pci_dev *dev); 1025 #else 1026 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 1027 static inline void pci_save_tph_state(struct pci_dev *dev) { } 1028 static inline void pci_no_tph(void) { } 1029 static inline void pci_tph_init(struct pci_dev *dev) { } 1030 #endif 1031 1032 #ifdef CONFIG_PCIE_PTM 1033 void pci_ptm_init(struct pci_dev *dev); 1034 void pci_save_ptm_state(struct pci_dev *dev); 1035 void pci_restore_ptm_state(struct pci_dev *dev); 1036 void pci_suspend_ptm(struct pci_dev *dev); 1037 void pci_resume_ptm(struct pci_dev *dev); 1038 #else 1039 static inline void pci_ptm_init(struct pci_dev *dev) { } 1040 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 1041 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 1042 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 1043 static inline void pci_resume_ptm(struct pci_dev *dev) { } 1044 #endif 1045 1046 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 1047 struct resource *res) 1048 { 1049 int resno = pci_resource_num(dev, res); 1050 1051 if (pci_resource_is_iov(resno)) 1052 return pci_sriov_resource_alignment(dev, resno); 1053 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 1054 return pci_cardbus_resource_alignment(res); 1055 return resource_alignment(res); 1056 } 1057 1058 resource_size_t pci_min_window_alignment(struct pci_bus *bus, 1059 unsigned long type); 1060 1061 void pci_acs_init(struct pci_dev *dev); 1062 void pci_enable_acs(struct pci_dev *dev); 1063 #ifdef CONFIG_PCI_QUIRKS 1064 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1065 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1066 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 1067 void pci_disable_broken_acs_cap(struct pci_dev *pdev); 1068 int pcie_failed_link_retrain(struct pci_dev *dev); 1069 #else 1070 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1071 u16 acs_flags) 1072 { 1073 return -ENOTTY; 1074 } 1075 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1076 { 1077 return -ENOTTY; 1078 } 1079 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 1080 { 1081 return -ENOTTY; 1082 } 1083 static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } 1084 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 1085 { 1086 return -ENOTTY; 1087 } 1088 #endif 1089 1090 /* PCI error reporting and recovery */ 1091 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 1092 pci_channel_state_t state, 1093 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 1094 1095 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 1096 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 1097 1098 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 1099 void pci_save_ltr_state(struct pci_dev *dev); 1100 void pci_restore_ltr_state(struct pci_dev *dev); 1101 void pci_configure_aspm_l1ss(struct pci_dev *dev); 1102 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 1103 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 1104 1105 #ifdef CONFIG_PCIEASPM 1106 void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 1107 void pcie_aspm_init_link_state(struct pci_dev *pdev); 1108 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 1109 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 1110 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 1111 void pci_configure_ltr(struct pci_dev *pdev); 1112 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 1113 #else 1114 static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 1115 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 1116 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 1117 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 1118 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 1119 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 1120 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 1121 #endif 1122 1123 #ifdef CONFIG_PCIE_ECRC 1124 void pcie_set_ecrc_checking(struct pci_dev *dev); 1125 void pcie_ecrc_get_policy(char *str); 1126 #else 1127 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1128 static inline void pcie_ecrc_get_policy(char *str) { } 1129 #endif 1130 1131 #ifdef CONFIG_PCIEPORTBUS 1132 void pcie_reset_lbms(struct pci_dev *port); 1133 #else 1134 static inline void pcie_reset_lbms(struct pci_dev *port) {} 1135 #endif 1136 1137 struct pci_dev_reset_methods { 1138 u16 vendor; 1139 u16 device; 1140 int (*reset)(struct pci_dev *dev, bool probe); 1141 }; 1142 1143 struct pci_reset_fn_method { 1144 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1145 char *name; 1146 }; 1147 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1148 1149 #ifdef CONFIG_PCI_QUIRKS 1150 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1151 #else 1152 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1153 { 1154 return -ENOTTY; 1155 } 1156 #endif 1157 1158 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1159 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1160 struct resource *res); 1161 #else 1162 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1163 u16 segment, struct resource *res) 1164 { 1165 return -ENODEV; 1166 } 1167 #endif 1168 1169 void pci_rebar_init(struct pci_dev *pdev); 1170 void pci_restore_rebar_state(struct pci_dev *pdev); 1171 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1172 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1173 1174 struct device_node; 1175 1176 #define PCI_EQ_RESV 0xff 1177 1178 enum equalization_preset_type { 1179 EQ_PRESET_TYPE_8GTS, 1180 EQ_PRESET_TYPE_16GTS, 1181 EQ_PRESET_TYPE_32GTS, 1182 EQ_PRESET_TYPE_64GTS, 1183 EQ_PRESET_TYPE_MAX 1184 }; 1185 1186 struct pci_eq_presets { 1187 u16 eq_presets_8gts[MAX_NR_LANES]; 1188 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1189 }; 1190 1191 #ifdef CONFIG_OF 1192 int of_get_pci_domain_nr(struct device_node *node); 1193 int of_pci_get_max_link_speed(struct device_node *node); 1194 u32 of_pci_get_slot_power_limit(struct device_node *node, 1195 u8 *slot_power_limit_value, 1196 u8 *slot_power_limit_scale); 1197 bool of_pci_preserve_config(struct device_node *node); 1198 int pci_set_of_node(struct pci_dev *dev); 1199 void pci_release_of_node(struct pci_dev *dev); 1200 void pci_set_bus_of_node(struct pci_bus *bus); 1201 void pci_release_bus_of_node(struct pci_bus *bus); 1202 1203 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1204 bool of_pci_supply_present(struct device_node *np); 1205 int of_pci_get_equalization_presets(struct device *dev, 1206 struct pci_eq_presets *presets, 1207 int num_lanes); 1208 #else 1209 static inline int 1210 of_get_pci_domain_nr(struct device_node *node) 1211 { 1212 return -1; 1213 } 1214 1215 static inline int 1216 of_pci_get_max_link_speed(struct device_node *node) 1217 { 1218 return -EINVAL; 1219 } 1220 1221 static inline u32 1222 of_pci_get_slot_power_limit(struct device_node *node, 1223 u8 *slot_power_limit_value, 1224 u8 *slot_power_limit_scale) 1225 { 1226 if (slot_power_limit_value) 1227 *slot_power_limit_value = 0; 1228 if (slot_power_limit_scale) 1229 *slot_power_limit_scale = 0; 1230 return 0; 1231 } 1232 1233 static inline bool of_pci_preserve_config(struct device_node *node) 1234 { 1235 return false; 1236 } 1237 1238 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1239 static inline void pci_release_of_node(struct pci_dev *dev) { } 1240 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1241 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1242 1243 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1244 { 1245 return 0; 1246 } 1247 1248 static inline bool of_pci_supply_present(struct device_node *np) 1249 { 1250 return false; 1251 } 1252 1253 static inline int of_pci_get_equalization_presets(struct device *dev, 1254 struct pci_eq_presets *presets, 1255 int num_lanes) 1256 { 1257 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1258 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1259 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1260 1261 return 0; 1262 } 1263 #endif /* CONFIG_OF */ 1264 1265 struct of_changeset; 1266 1267 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1268 void of_pci_make_dev_node(struct pci_dev *pdev); 1269 void of_pci_remove_node(struct pci_dev *pdev); 1270 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1271 struct device_node *np); 1272 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1273 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1274 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1275 struct of_changeset *ocs, 1276 struct device_node *np); 1277 #else 1278 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1279 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1280 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1281 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1282 #endif 1283 1284 #ifdef CONFIG_PCIEAER 1285 void pci_no_aer(void); 1286 void pci_aer_init(struct pci_dev *dev); 1287 void pci_aer_exit(struct pci_dev *dev); 1288 extern const struct attribute_group aer_stats_attr_group; 1289 extern const struct attribute_group aer_attr_group; 1290 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1291 int pci_aer_clear_status(struct pci_dev *dev); 1292 int pci_aer_raw_clear_status(struct pci_dev *dev); 1293 void pci_save_aer_state(struct pci_dev *dev); 1294 void pci_restore_aer_state(struct pci_dev *dev); 1295 #else 1296 static inline void pci_no_aer(void) { } 1297 static inline void pci_aer_init(struct pci_dev *d) { } 1298 static inline void pci_aer_exit(struct pci_dev *d) { } 1299 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1300 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1301 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1302 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1303 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1304 #endif 1305 1306 #ifdef CONFIG_ACPI 1307 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1308 int pci_acpi_program_hp_params(struct pci_dev *dev); 1309 extern const struct attribute_group pci_dev_acpi_attr_group; 1310 void pci_set_acpi_fwnode(struct pci_dev *dev); 1311 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1312 bool acpi_pci_power_manageable(struct pci_dev *dev); 1313 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1314 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1315 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1316 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1317 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1318 bool acpi_pci_need_resume(struct pci_dev *dev); 1319 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1320 #else 1321 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1322 { 1323 return false; 1324 } 1325 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1326 { 1327 return -ENOTTY; 1328 } 1329 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1330 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1331 { 1332 return -ENODEV; 1333 } 1334 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1335 { 1336 return false; 1337 } 1338 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1339 { 1340 return false; 1341 } 1342 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1343 { 1344 return -ENODEV; 1345 } 1346 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1347 { 1348 return PCI_UNKNOWN; 1349 } 1350 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1351 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1352 { 1353 return -ENODEV; 1354 } 1355 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1356 { 1357 return false; 1358 } 1359 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1360 { 1361 return PCI_POWER_ERROR; 1362 } 1363 #endif 1364 1365 #ifdef CONFIG_PCIEASPM 1366 extern const struct attribute_group aspm_ctrl_attr_group; 1367 #endif 1368 1369 #ifdef CONFIG_X86_INTEL_MID 1370 bool pci_use_mid_pm(void); 1371 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1372 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1373 #else 1374 static inline bool pci_use_mid_pm(void) 1375 { 1376 return false; 1377 } 1378 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1379 { 1380 return -ENODEV; 1381 } 1382 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1383 { 1384 return PCI_UNKNOWN; 1385 } 1386 #endif 1387 1388 #ifdef CONFIG_PCI_MSI 1389 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1390 #else 1391 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1392 { 1393 return -ENODEV; 1394 } 1395 #endif 1396 1397 /* 1398 * Config Address for PCI Configuration Mechanism #1 1399 * 1400 * See PCI Local Bus Specification, Revision 3.0, 1401 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1402 */ 1403 1404 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1405 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1406 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1407 1408 #define PCI_CONF1_BUS_MASK 0xff 1409 #define PCI_CONF1_DEV_MASK 0x1f 1410 #define PCI_CONF1_FUNC_MASK 0x7 1411 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1412 1413 #define PCI_CONF1_ENABLE BIT(31) 1414 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1415 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1416 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1417 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1418 1419 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1420 (PCI_CONF1_ENABLE | \ 1421 PCI_CONF1_BUS(bus) | \ 1422 PCI_CONF1_DEV(dev) | \ 1423 PCI_CONF1_FUNC(func) | \ 1424 PCI_CONF1_REG(reg)) 1425 1426 /* 1427 * Extension of PCI Config Address for accessing extended PCIe registers 1428 * 1429 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1430 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1431 * are used for specifying additional 4 high bits of PCI Express register. 1432 */ 1433 1434 #define PCI_CONF1_EXT_REG_SHIFT 16 1435 #define PCI_CONF1_EXT_REG_MASK 0xf00 1436 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1437 1438 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1439 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1440 PCI_CONF1_EXT_REG(reg)) 1441 1442 #endif /* DRIVERS_PCI_H */ 1443