Searched refs:output_mask (Results 1 – 12 of 12) sorted by relevance
626 u16 output_mask = channel->output_mask; in idtcm_sync_pps_output() local652 qn = output_mask & 0x1; in idtcm_sync_pps_output()653 output_mask = output_mask >> 1; in idtcm_sync_pps_output()654 qn_plus_1 = output_mask & 0x1; in idtcm_sync_pps_output()655 output_mask = output_mask >> 1; in idtcm_sync_pps_output()658 qn = output_mask & 0x1; in idtcm_sync_pps_output()659 output_mask = output_mask >> 1; in idtcm_sync_pps_output()663 qn_plus_1 = output_mask & 0x1; in idtcm_sync_pps_output()664 output_mask = output_mask >> 1; in idtcm_sync_pps_output()666 qn = output_mask & 0x1; in idtcm_sync_pps_output()[all …]
69 u8 output_mask; member
110 u16 output_mask; member
809 idt82p33->channel[0].output_mask = val; in idt82p33_check_and_set_masks()812 idt82p33->channel[1].output_mask = val; in idt82p33_check_and_set_masks()831 i, idt82p33->channel[i].output_mask); in idt82p33_display_masks()1392 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0; in idt82p33_probe()1393 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1; in idt82p33_probe()
25 u8 output_mask; member
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()528 our_chip->variant.output_mask |= BIT(val); in pwm_samsung_parse_dt()579 if (our_chip->variant.output_mask & BIT(chan)) in pwm_samsung_probe()613 if (our_chip->variant.output_mask & BIT(i)) in pwm_samsung_resume()
132 u64 output_mask; member
667 if (pt->output_mask != reg) { in pt_config_buffer()668 pt->output_mask = reg; in pt_config_buffer()995 rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); in pt_read_offset()997 buf->output_off = pt->output_mask >> 32; in pt_read_offset()1000 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7; in pt_read_offset()
171 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in s3c64xx_set_timer_source()172 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); in s3c64xx_set_timer_source()
380 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); in _samsung_pwm_clocksource_init()433 pwm.variant.output_mask |= 1 << val; in samsung_pwm_alloc()
56 u64 output_mask; member
1265 wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_load_msr()1279 rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); in pt_save_msr()2247 msr_info->data = vmx->pt_desc.guest.output_mask; in vmx_get_msr()2571 vmx->pt_desc.guest.output_mask = data; in vmx_set_msr()5038 vmx->pt_desc.guest.output_mask = 0x7F; in init_vmcs()