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Searched refs:optimization_phase_params (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/
H A Ddml2_internal_shared_types.h892 struct optimization_phase_params { struct
913 struct optimization_phase_params min_clock_for_latency_phase; argument
914 struct optimization_phase_params mcache_phase;
915 struct optimization_phase_params uclk_pstate_phase;
916 struct optimization_phase_params vmin_phase;
917 struct optimization_phase_params stutter_phase;
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
H A Ddml2_top_soc15.c206 …ion_phase(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params) in dml2_top_optimization_perform_optimization_phase()
282 …n_phase_1(struct dml2_optimization_phase_locals *l, const struct optimization_phase_params *params) in dml2_top_optimization_perform_optimization_phase_1()
795 struct optimization_phase_params mcache_phase = { in dml2_top_soc15_check_mode_supported()
872 memset(&l->min_clock_for_latency_phase, 0, sizeof(struct optimization_phase_params)); in dml2_top_soc15_build_mode_programming()
889 memset(&l->mcache_phase, 0, sizeof(struct optimization_phase_params)); in dml2_top_soc15_build_mode_programming()
915 memset(&l->uclk_pstate_phase, 0, sizeof(struct optimization_phase_params)); in dml2_top_soc15_build_mode_programming()
934 memset(&l->vmin_phase, 0, sizeof(struct optimization_phase_params)); in dml2_top_soc15_build_mode_programming()
962 memset(&l->stutter_phase, 0, sizeof(struct optimization_phase_params)); in dml2_top_soc15_build_mode_programming()