1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 forward_vhca_rx[0x1]; 473 u8 reserved_at_1b[0x1]; 474 u8 ipsec_encrypt[0x1]; 475 u8 ipsec_decrypt[0x1]; 476 u8 sw_owner_v2[0x1]; 477 u8 reserved_at_1f[0x1]; 478 479 u8 termination_table_raw_traffic[0x1]; 480 u8 reserved_at_21[0x1]; 481 u8 log_max_ft_size[0x6]; 482 u8 log_max_modify_header_context[0x8]; 483 u8 max_modify_header_actions[0x8]; 484 u8 max_ft_level[0x8]; 485 486 u8 reformat_add_esp_trasport[0x1]; 487 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 488 u8 reformat_add_esp_transport_over_udp[0x1]; 489 u8 reformat_del_esp_trasport[0x1]; 490 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 491 u8 reformat_del_esp_transport_over_udp[0x1]; 492 u8 execute_aso[0x1]; 493 u8 reserved_at_47[0x19]; 494 495 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 496 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 497 u8 reformat_insert[0x1]; 498 u8 reformat_remove[0x1]; 499 u8 macsec_encrypt[0x1]; 500 u8 macsec_decrypt[0x1]; 501 u8 psp_encrypt[0x1]; 502 u8 psp_decrypt[0x1]; 503 u8 reformat_add_macsec[0x1]; 504 u8 reformat_remove_macsec[0x1]; 505 u8 reparse[0x1]; 506 u8 reserved_at_6b[0x1]; 507 u8 cross_vhca_object[0x1]; 508 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 509 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 510 u8 ignore_flow_level_rtc_valid[0x1]; 511 u8 reserved_at_70[0x8]; 512 u8 log_max_ft_num[0x8]; 513 514 u8 reserved_at_80[0x10]; 515 u8 log_max_flow_counter[0x8]; 516 u8 log_max_destination[0x8]; 517 518 u8 reserved_at_a0[0x18]; 519 u8 log_max_flow[0x8]; 520 521 u8 reserved_at_c0[0x40]; 522 523 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 524 525 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 526 }; 527 528 struct mlx5_ifc_odp_per_transport_service_cap_bits { 529 u8 send[0x1]; 530 u8 receive[0x1]; 531 u8 write[0x1]; 532 u8 read[0x1]; 533 u8 atomic[0x1]; 534 u8 srq_receive[0x1]; 535 u8 reserved_at_6[0x1a]; 536 }; 537 538 struct mlx5_ifc_ipv4_layout_bits { 539 u8 reserved_at_0[0x60]; 540 541 u8 ipv4[0x20]; 542 }; 543 544 struct mlx5_ifc_ipv6_layout_bits { 545 u8 ipv6[16][0x8]; 546 }; 547 548 struct mlx5_ifc_ipv6_simple_layout_bits { 549 u8 ipv6_127_96[0x20]; 550 u8 ipv6_95_64[0x20]; 551 u8 ipv6_63_32[0x20]; 552 u8 ipv6_31_0[0x20]; 553 }; 554 555 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 556 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 557 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 558 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 559 u8 reserved_at_0[0x80]; 560 }; 561 562 enum { 563 MLX5_PACKET_L4_TYPE_NONE, 564 MLX5_PACKET_L4_TYPE_TCP, 565 MLX5_PACKET_L4_TYPE_UDP, 566 }; 567 568 enum { 569 MLX5_PACKET_L4_TYPE_EXT_NONE, 570 MLX5_PACKET_L4_TYPE_EXT_TCP, 571 MLX5_PACKET_L4_TYPE_EXT_UDP, 572 MLX5_PACKET_L4_TYPE_EXT_ICMP, 573 }; 574 575 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 576 u8 smac_47_16[0x20]; 577 578 u8 smac_15_0[0x10]; 579 u8 ethertype[0x10]; 580 581 u8 dmac_47_16[0x20]; 582 583 u8 dmac_15_0[0x10]; 584 u8 first_prio[0x3]; 585 u8 first_cfi[0x1]; 586 u8 first_vid[0xc]; 587 588 u8 ip_protocol[0x8]; 589 u8 ip_dscp[0x6]; 590 u8 ip_ecn[0x2]; 591 u8 cvlan_tag[0x1]; 592 u8 svlan_tag[0x1]; 593 u8 frag[0x1]; 594 u8 ip_version[0x4]; 595 u8 tcp_flags[0x9]; 596 597 u8 tcp_sport[0x10]; 598 u8 tcp_dport[0x10]; 599 600 u8 l4_type[0x2]; 601 u8 l4_type_ext[0x4]; 602 u8 reserved_at_c6[0xa]; 603 u8 ipv4_ihl[0x4]; 604 u8 reserved_at_d4[0x4]; 605 u8 ttl_hoplimit[0x8]; 606 607 u8 udp_sport[0x10]; 608 u8 udp_dport[0x10]; 609 610 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 611 612 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 613 }; 614 615 struct mlx5_ifc_nvgre_key_bits { 616 u8 hi[0x18]; 617 u8 lo[0x8]; 618 }; 619 620 union mlx5_ifc_gre_key_bits { 621 struct mlx5_ifc_nvgre_key_bits nvgre; 622 u8 key[0x20]; 623 }; 624 625 struct mlx5_ifc_fte_match_set_misc_bits { 626 u8 gre_c_present[0x1]; 627 u8 reserved_at_1[0x1]; 628 u8 gre_k_present[0x1]; 629 u8 gre_s_present[0x1]; 630 u8 source_vhca_port[0x4]; 631 u8 source_sqn[0x18]; 632 633 u8 source_eswitch_owner_vhca_id[0x10]; 634 u8 source_port[0x10]; 635 636 u8 outer_second_prio[0x3]; 637 u8 outer_second_cfi[0x1]; 638 u8 outer_second_vid[0xc]; 639 u8 inner_second_prio[0x3]; 640 u8 inner_second_cfi[0x1]; 641 u8 inner_second_vid[0xc]; 642 643 u8 outer_second_cvlan_tag[0x1]; 644 u8 inner_second_cvlan_tag[0x1]; 645 u8 outer_second_svlan_tag[0x1]; 646 u8 inner_second_svlan_tag[0x1]; 647 u8 reserved_at_64[0xc]; 648 u8 gre_protocol[0x10]; 649 650 union mlx5_ifc_gre_key_bits gre_key; 651 652 u8 vxlan_vni[0x18]; 653 u8 bth_opcode[0x8]; 654 655 u8 geneve_vni[0x18]; 656 u8 reserved_at_d8[0x6]; 657 u8 geneve_tlv_option_0_exist[0x1]; 658 u8 geneve_oam[0x1]; 659 660 u8 reserved_at_e0[0xc]; 661 u8 outer_ipv6_flow_label[0x14]; 662 663 u8 reserved_at_100[0xc]; 664 u8 inner_ipv6_flow_label[0x14]; 665 666 u8 reserved_at_120[0xa]; 667 u8 geneve_opt_len[0x6]; 668 u8 geneve_protocol_type[0x10]; 669 670 u8 reserved_at_140[0x8]; 671 u8 bth_dst_qp[0x18]; 672 u8 inner_esp_spi[0x20]; 673 u8 outer_esp_spi[0x20]; 674 u8 reserved_at_1a0[0x60]; 675 }; 676 677 struct mlx5_ifc_fte_match_mpls_bits { 678 u8 mpls_label[0x14]; 679 u8 mpls_exp[0x3]; 680 u8 mpls_s_bos[0x1]; 681 u8 mpls_ttl[0x8]; 682 }; 683 684 struct mlx5_ifc_fte_match_set_misc2_bits { 685 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 686 687 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 688 689 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 690 691 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 692 693 u8 metadata_reg_c_7[0x20]; 694 695 u8 metadata_reg_c_6[0x20]; 696 697 u8 metadata_reg_c_5[0x20]; 698 699 u8 metadata_reg_c_4[0x20]; 700 701 u8 metadata_reg_c_3[0x20]; 702 703 u8 metadata_reg_c_2[0x20]; 704 705 u8 metadata_reg_c_1[0x20]; 706 707 u8 metadata_reg_c_0[0x20]; 708 709 u8 metadata_reg_a[0x20]; 710 711 u8 psp_syndrome[0x8]; 712 u8 macsec_syndrome[0x8]; 713 u8 ipsec_syndrome[0x8]; 714 u8 ipsec_next_header[0x8]; 715 716 u8 reserved_at_1c0[0x40]; 717 }; 718 719 struct mlx5_ifc_fte_match_set_misc3_bits { 720 u8 inner_tcp_seq_num[0x20]; 721 722 u8 outer_tcp_seq_num[0x20]; 723 724 u8 inner_tcp_ack_num[0x20]; 725 726 u8 outer_tcp_ack_num[0x20]; 727 728 u8 reserved_at_80[0x8]; 729 u8 outer_vxlan_gpe_vni[0x18]; 730 731 u8 outer_vxlan_gpe_next_protocol[0x8]; 732 u8 outer_vxlan_gpe_flags[0x8]; 733 u8 reserved_at_b0[0x10]; 734 735 u8 icmp_header_data[0x20]; 736 737 u8 icmpv6_header_data[0x20]; 738 739 u8 icmp_type[0x8]; 740 u8 icmp_code[0x8]; 741 u8 icmpv6_type[0x8]; 742 u8 icmpv6_code[0x8]; 743 744 u8 geneve_tlv_option_0_data[0x20]; 745 746 u8 gtpu_teid[0x20]; 747 748 u8 gtpu_msg_type[0x8]; 749 u8 gtpu_msg_flags[0x8]; 750 u8 reserved_at_170[0x10]; 751 752 u8 gtpu_dw_2[0x20]; 753 754 u8 gtpu_first_ext_dw_0[0x20]; 755 756 u8 gtpu_dw_0[0x20]; 757 758 u8 reserved_at_1e0[0x20]; 759 }; 760 761 struct mlx5_ifc_fte_match_set_misc4_bits { 762 u8 prog_sample_field_value_0[0x20]; 763 764 u8 prog_sample_field_id_0[0x20]; 765 766 u8 prog_sample_field_value_1[0x20]; 767 768 u8 prog_sample_field_id_1[0x20]; 769 770 u8 prog_sample_field_value_2[0x20]; 771 772 u8 prog_sample_field_id_2[0x20]; 773 774 u8 prog_sample_field_value_3[0x20]; 775 776 u8 prog_sample_field_id_3[0x20]; 777 778 u8 reserved_at_100[0x100]; 779 }; 780 781 struct mlx5_ifc_fte_match_set_misc5_bits { 782 u8 macsec_tag_0[0x20]; 783 784 u8 macsec_tag_1[0x20]; 785 786 u8 macsec_tag_2[0x20]; 787 788 u8 macsec_tag_3[0x20]; 789 790 u8 tunnel_header_0[0x20]; 791 792 u8 tunnel_header_1[0x20]; 793 794 u8 tunnel_header_2[0x20]; 795 796 u8 tunnel_header_3[0x20]; 797 798 u8 reserved_at_100[0x100]; 799 }; 800 801 struct mlx5_ifc_cmd_pas_bits { 802 u8 pa_h[0x20]; 803 804 u8 pa_l[0x14]; 805 u8 reserved_at_34[0xc]; 806 }; 807 808 struct mlx5_ifc_uint64_bits { 809 u8 hi[0x20]; 810 811 u8 lo[0x20]; 812 }; 813 814 enum { 815 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 816 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 817 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 818 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 819 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 820 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 821 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 822 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 823 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 824 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 825 }; 826 827 struct mlx5_ifc_ads_bits { 828 u8 fl[0x1]; 829 u8 free_ar[0x1]; 830 u8 reserved_at_2[0xe]; 831 u8 pkey_index[0x10]; 832 833 u8 plane_index[0x8]; 834 u8 grh[0x1]; 835 u8 mlid[0x7]; 836 u8 rlid[0x10]; 837 838 u8 ack_timeout[0x5]; 839 u8 reserved_at_45[0x3]; 840 u8 src_addr_index[0x8]; 841 u8 reserved_at_50[0x4]; 842 u8 stat_rate[0x4]; 843 u8 hop_limit[0x8]; 844 845 u8 reserved_at_60[0x4]; 846 u8 tclass[0x8]; 847 u8 flow_label[0x14]; 848 849 u8 rgid_rip[16][0x8]; 850 851 u8 reserved_at_100[0x4]; 852 u8 f_dscp[0x1]; 853 u8 f_ecn[0x1]; 854 u8 reserved_at_106[0x1]; 855 u8 f_eth_prio[0x1]; 856 u8 ecn[0x2]; 857 u8 dscp[0x6]; 858 u8 udp_sport[0x10]; 859 860 u8 dei_cfi[0x1]; 861 u8 eth_prio[0x3]; 862 u8 sl[0x4]; 863 u8 vhca_port_num[0x8]; 864 u8 rmac_47_32[0x10]; 865 866 u8 rmac_31_0[0x20]; 867 }; 868 869 struct mlx5_ifc_flow_table_nic_cap_bits { 870 u8 nic_rx_multi_path_tirs[0x1]; 871 u8 nic_rx_multi_path_tirs_fts[0x1]; 872 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 873 u8 reserved_at_3[0x4]; 874 u8 sw_owner_reformat_supported[0x1]; 875 u8 reserved_at_8[0x18]; 876 877 u8 encap_general_header[0x1]; 878 u8 reserved_at_21[0xa]; 879 u8 log_max_packet_reformat_context[0x5]; 880 u8 reserved_at_30[0x6]; 881 u8 max_encap_header_size[0xa]; 882 u8 reserved_at_40[0x1c0]; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 885 886 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 887 888 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 889 890 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 891 892 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 893 894 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 895 896 u8 reserved_at_e00[0x600]; 897 898 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 899 900 u8 reserved_at_1480[0x80]; 901 902 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 903 904 u8 reserved_at_1580[0x280]; 905 906 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 907 908 u8 reserved_at_1880[0x780]; 909 910 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 911 912 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 913 914 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 915 916 u8 reserved_at_20c0[0x5f40]; 917 }; 918 919 struct mlx5_ifc_port_selection_cap_bits { 920 u8 reserved_at_0[0x10]; 921 u8 port_select_flow_table[0x1]; 922 u8 reserved_at_11[0x1]; 923 u8 port_select_flow_table_bypass[0x1]; 924 u8 reserved_at_13[0xd]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 929 930 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 931 932 u8 reserved_at_480[0x7b80]; 933 }; 934 935 enum { 936 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 937 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 938 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 939 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 940 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 941 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 942 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 943 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 944 }; 945 946 struct mlx5_ifc_flow_table_eswitch_cap_bits { 947 u8 fdb_to_vport_reg_c_id[0x8]; 948 u8 reserved_at_8[0x5]; 949 u8 fdb_uplink_hairpin[0x1]; 950 u8 fdb_multi_path_any_table_limit_regc[0x1]; 951 u8 reserved_at_f[0x1]; 952 u8 fdb_dynamic_tunnel[0x1]; 953 u8 reserved_at_11[0x1]; 954 u8 fdb_multi_path_any_table[0x1]; 955 u8 reserved_at_13[0x2]; 956 u8 fdb_modify_header_fwd_to_table[0x1]; 957 u8 fdb_ipv4_ttl_modify[0x1]; 958 u8 flow_source[0x1]; 959 u8 reserved_at_18[0x2]; 960 u8 multi_fdb_encap[0x1]; 961 u8 egress_acl_forward_to_vport[0x1]; 962 u8 fdb_multi_path_to_table[0x1]; 963 u8 reserved_at_1d[0x3]; 964 965 u8 reserved_at_20[0x1e0]; 966 967 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 968 969 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 970 971 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 972 973 u8 reserved_at_800[0xC00]; 974 975 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 976 977 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 978 979 u8 reserved_at_1500[0x300]; 980 981 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 982 983 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 984 985 u8 sw_steering_uplink_icm_address_rx[0x40]; 986 987 u8 sw_steering_uplink_icm_address_tx[0x40]; 988 989 u8 reserved_at_1900[0x6700]; 990 }; 991 992 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 993 u8 reserved_at_0[0x3]; 994 u8 log_max_num_ste[0x5]; 995 u8 reserved_at_8[0x3]; 996 u8 log_max_num_stc[0x5]; 997 u8 reserved_at_10[0x3]; 998 u8 log_max_num_rtc[0x5]; 999 u8 reserved_at_18[0x3]; 1000 u8 log_max_num_header_modify_pattern[0x5]; 1001 1002 u8 rtc_hash_split_table[0x1]; 1003 u8 rtc_linear_lookup_table[0x1]; 1004 u8 reserved_at_22[0x1]; 1005 u8 stc_alloc_log_granularity[0x5]; 1006 u8 reserved_at_28[0x3]; 1007 u8 stc_alloc_log_max[0x5]; 1008 u8 reserved_at_30[0x3]; 1009 u8 ste_alloc_log_granularity[0x5]; 1010 u8 reserved_at_38[0x3]; 1011 u8 ste_alloc_log_max[0x5]; 1012 1013 u8 reserved_at_40[0xb]; 1014 u8 rtc_reparse_mode[0x5]; 1015 u8 reserved_at_50[0x3]; 1016 u8 rtc_index_mode[0x5]; 1017 u8 reserved_at_58[0x3]; 1018 u8 rtc_log_depth_max[0x5]; 1019 1020 u8 reserved_at_60[0x10]; 1021 u8 ste_format[0x10]; 1022 1023 u8 stc_action_type[0x80]; 1024 1025 u8 header_insert_type[0x10]; 1026 u8 header_remove_type[0x10]; 1027 1028 u8 trivial_match_definer[0x20]; 1029 1030 u8 reserved_at_140[0x1b]; 1031 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1032 1033 u8 reserved_at_160[0x18]; 1034 u8 access_index_mode[0x8]; 1035 1036 u8 reserved_at_180[0x10]; 1037 u8 ste_format_gen_wqe[0x10]; 1038 1039 u8 linear_match_definer_reg_c3[0x20]; 1040 1041 u8 fdb_jump_to_tir_stc[0x1]; 1042 u8 reserved_at_1c1[0x1f]; 1043 }; 1044 1045 struct mlx5_ifc_esw_cap_bits { 1046 u8 reserved_at_0[0x1d]; 1047 u8 merged_eswitch[0x1]; 1048 u8 reserved_at_1e[0x2]; 1049 1050 u8 reserved_at_20[0x40]; 1051 1052 u8 esw_manager_vport_number_valid[0x1]; 1053 u8 reserved_at_61[0xf]; 1054 u8 esw_manager_vport_number[0x10]; 1055 1056 u8 reserved_at_80[0x780]; 1057 }; 1058 1059 enum { 1060 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1061 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1062 }; 1063 1064 struct mlx5_ifc_e_switch_cap_bits { 1065 u8 vport_svlan_strip[0x1]; 1066 u8 vport_cvlan_strip[0x1]; 1067 u8 vport_svlan_insert[0x1]; 1068 u8 vport_cvlan_insert_if_not_exist[0x1]; 1069 u8 vport_cvlan_insert_overwrite[0x1]; 1070 u8 reserved_at_5[0x1]; 1071 u8 vport_cvlan_insert_always[0x1]; 1072 u8 esw_shared_ingress_acl[0x1]; 1073 u8 esw_uplink_ingress_acl[0x1]; 1074 u8 root_ft_on_other_esw[0x1]; 1075 u8 reserved_at_a[0x1]; 1076 u8 esw_vport_state_max_tx_speed[0x1]; 1077 u8 reserved_at_c[0xd]; 1078 u8 esw_functions_changed[0x1]; 1079 u8 reserved_at_1a[0x1]; 1080 u8 ecpf_vport_exists[0x1]; 1081 u8 counter_eswitch_affinity[0x1]; 1082 u8 merged_eswitch[0x1]; 1083 u8 nic_vport_node_guid_modify[0x1]; 1084 u8 nic_vport_port_guid_modify[0x1]; 1085 1086 u8 vxlan_encap_decap[0x1]; 1087 u8 nvgre_encap_decap[0x1]; 1088 u8 reserved_at_22[0x1]; 1089 u8 log_max_fdb_encap_uplink[0x5]; 1090 u8 reserved_at_21[0x3]; 1091 u8 log_max_packet_reformat_context[0x5]; 1092 u8 reserved_2b[0x6]; 1093 u8 max_encap_header_size[0xa]; 1094 1095 u8 reserved_at_40[0xb]; 1096 u8 log_max_esw_sf[0x5]; 1097 u8 esw_sf_base_id[0x10]; 1098 1099 u8 reserved_at_60[0x7a0]; 1100 1101 }; 1102 1103 struct mlx5_ifc_qos_cap_bits { 1104 u8 packet_pacing[0x1]; 1105 u8 esw_scheduling[0x1]; 1106 u8 esw_bw_share[0x1]; 1107 u8 esw_rate_limit[0x1]; 1108 u8 reserved_at_4[0x1]; 1109 u8 packet_pacing_burst_bound[0x1]; 1110 u8 packet_pacing_typical_size[0x1]; 1111 u8 reserved_at_7[0x1]; 1112 u8 nic_sq_scheduling[0x1]; 1113 u8 nic_bw_share[0x1]; 1114 u8 nic_rate_limit[0x1]; 1115 u8 packet_pacing_uid[0x1]; 1116 u8 log_esw_max_sched_depth[0x4]; 1117 u8 reserved_at_10[0x10]; 1118 1119 u8 reserved_at_20[0x9]; 1120 u8 esw_cross_esw_sched[0x1]; 1121 u8 reserved_at_2a[0x1]; 1122 u8 log_max_qos_nic_queue_group[0x5]; 1123 u8 reserved_at_30[0x10]; 1124 1125 u8 packet_pacing_max_rate[0x20]; 1126 1127 u8 packet_pacing_min_rate[0x20]; 1128 1129 u8 reserved_at_80[0xb]; 1130 u8 log_esw_max_rate_limit[0x5]; 1131 u8 packet_pacing_rate_table_size[0x10]; 1132 1133 u8 esw_element_type[0x10]; 1134 u8 esw_tsar_type[0x10]; 1135 1136 u8 reserved_at_c0[0x10]; 1137 u8 max_qos_para_vport[0x10]; 1138 1139 u8 max_tsar_bw_share[0x20]; 1140 1141 u8 nic_element_type[0x10]; 1142 u8 nic_tsar_type[0x10]; 1143 1144 u8 reserved_at_120[0x3]; 1145 u8 log_meter_aso_granularity[0x5]; 1146 u8 reserved_at_128[0x3]; 1147 u8 log_meter_aso_max_alloc[0x5]; 1148 u8 reserved_at_130[0x3]; 1149 u8 log_max_num_meter_aso[0x5]; 1150 u8 reserved_at_138[0x8]; 1151 1152 u8 reserved_at_140[0x6c0]; 1153 }; 1154 1155 struct mlx5_ifc_debug_cap_bits { 1156 u8 core_dump_general[0x1]; 1157 u8 core_dump_qp[0x1]; 1158 u8 reserved_at_2[0x7]; 1159 u8 resource_dump[0x1]; 1160 u8 reserved_at_a[0x16]; 1161 1162 u8 reserved_at_20[0x2]; 1163 u8 stall_detect[0x1]; 1164 u8 reserved_at_23[0x1d]; 1165 1166 u8 reserved_at_40[0x7c0]; 1167 }; 1168 1169 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1170 u8 csum_cap[0x1]; 1171 u8 vlan_cap[0x1]; 1172 u8 lro_cap[0x1]; 1173 u8 lro_psh_flag[0x1]; 1174 u8 lro_time_stamp[0x1]; 1175 u8 reserved_at_5[0x2]; 1176 u8 wqe_vlan_insert[0x1]; 1177 u8 self_lb_en_modifiable[0x1]; 1178 u8 reserved_at_9[0x2]; 1179 u8 max_lso_cap[0x5]; 1180 u8 multi_pkt_send_wqe[0x2]; 1181 u8 wqe_inline_mode[0x2]; 1182 u8 rss_ind_tbl_cap[0x4]; 1183 u8 reg_umr_sq[0x1]; 1184 u8 scatter_fcs[0x1]; 1185 u8 enhanced_multi_pkt_send_wqe[0x1]; 1186 u8 tunnel_lso_const_out_ip_id[0x1]; 1187 u8 tunnel_lro_gre[0x1]; 1188 u8 tunnel_lro_vxlan[0x1]; 1189 u8 tunnel_stateless_gre[0x1]; 1190 u8 tunnel_stateless_vxlan[0x1]; 1191 1192 u8 swp[0x1]; 1193 u8 swp_csum[0x1]; 1194 u8 swp_lso[0x1]; 1195 u8 cqe_checksum_full[0x1]; 1196 u8 tunnel_stateless_geneve_tx[0x1]; 1197 u8 tunnel_stateless_mpls_over_udp[0x1]; 1198 u8 tunnel_stateless_mpls_over_gre[0x1]; 1199 u8 tunnel_stateless_vxlan_gpe[0x1]; 1200 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1201 u8 tunnel_stateless_ip_over_ip[0x1]; 1202 u8 insert_trailer[0x1]; 1203 u8 reserved_at_2b[0x1]; 1204 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1205 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1206 u8 reserved_at_2e[0x2]; 1207 u8 max_vxlan_udp_ports[0x8]; 1208 u8 swp_csum_l4_partial[0x1]; 1209 u8 reserved_at_39[0x5]; 1210 u8 max_geneve_opt_len[0x1]; 1211 u8 tunnel_stateless_geneve_rx[0x1]; 1212 1213 u8 reserved_at_40[0x10]; 1214 u8 lro_min_mss_size[0x10]; 1215 1216 u8 reserved_at_60[0x120]; 1217 1218 u8 lro_timer_supported_periods[4][0x20]; 1219 1220 u8 reserved_at_200[0x600]; 1221 }; 1222 1223 enum { 1224 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1225 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1226 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1227 }; 1228 1229 struct mlx5_ifc_roce_cap_bits { 1230 u8 roce_apm[0x1]; 1231 u8 reserved_at_1[0x3]; 1232 u8 sw_r_roce_src_udp_port[0x1]; 1233 u8 fl_rc_qp_when_roce_disabled[0x1]; 1234 u8 fl_rc_qp_when_roce_enabled[0x1]; 1235 u8 roce_cc_general[0x1]; 1236 u8 qp_ooo_transmit_default[0x1]; 1237 u8 reserved_at_9[0x15]; 1238 u8 qp_ts_format[0x2]; 1239 1240 u8 reserved_at_20[0x60]; 1241 1242 u8 reserved_at_80[0xc]; 1243 u8 l3_type[0x4]; 1244 u8 reserved_at_90[0x8]; 1245 u8 roce_version[0x8]; 1246 1247 u8 reserved_at_a0[0x10]; 1248 u8 r_roce_dest_udp_port[0x10]; 1249 1250 u8 r_roce_max_src_udp_port[0x10]; 1251 u8 r_roce_min_src_udp_port[0x10]; 1252 1253 u8 reserved_at_e0[0x10]; 1254 u8 roce_address_table_size[0x10]; 1255 1256 u8 reserved_at_100[0x700]; 1257 }; 1258 1259 struct mlx5_ifc_sync_steering_in_bits { 1260 u8 opcode[0x10]; 1261 u8 uid[0x10]; 1262 1263 u8 reserved_at_20[0x10]; 1264 u8 op_mod[0x10]; 1265 1266 u8 reserved_at_40[0xc0]; 1267 }; 1268 1269 struct mlx5_ifc_sync_steering_out_bits { 1270 u8 status[0x8]; 1271 u8 reserved_at_8[0x18]; 1272 1273 u8 syndrome[0x20]; 1274 1275 u8 reserved_at_40[0x40]; 1276 }; 1277 1278 struct mlx5_ifc_sync_crypto_in_bits { 1279 u8 opcode[0x10]; 1280 u8 uid[0x10]; 1281 1282 u8 reserved_at_20[0x10]; 1283 u8 op_mod[0x10]; 1284 1285 u8 reserved_at_40[0x20]; 1286 1287 u8 reserved_at_60[0x10]; 1288 u8 crypto_type[0x10]; 1289 1290 u8 reserved_at_80[0x80]; 1291 }; 1292 1293 struct mlx5_ifc_sync_crypto_out_bits { 1294 u8 status[0x8]; 1295 u8 reserved_at_8[0x18]; 1296 1297 u8 syndrome[0x20]; 1298 1299 u8 reserved_at_40[0x40]; 1300 }; 1301 1302 struct mlx5_ifc_device_mem_cap_bits { 1303 u8 memic[0x1]; 1304 u8 reserved_at_1[0x1f]; 1305 1306 u8 reserved_at_20[0xb]; 1307 u8 log_min_memic_alloc_size[0x5]; 1308 u8 reserved_at_30[0x8]; 1309 u8 log_max_memic_addr_alignment[0x8]; 1310 1311 u8 memic_bar_start_addr[0x40]; 1312 1313 u8 memic_bar_size[0x20]; 1314 1315 u8 max_memic_size[0x20]; 1316 1317 u8 steering_sw_icm_start_address[0x40]; 1318 1319 u8 reserved_at_100[0x8]; 1320 u8 log_header_modify_sw_icm_size[0x8]; 1321 u8 reserved_at_110[0x2]; 1322 u8 log_sw_icm_alloc_granularity[0x6]; 1323 u8 log_steering_sw_icm_size[0x8]; 1324 1325 u8 log_indirect_encap_sw_icm_size[0x8]; 1326 u8 reserved_at_128[0x10]; 1327 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1328 1329 u8 header_modify_sw_icm_start_address[0x40]; 1330 1331 u8 reserved_at_180[0x40]; 1332 1333 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1334 1335 u8 memic_operations[0x20]; 1336 1337 u8 reserved_at_220[0x20]; 1338 1339 u8 indirect_encap_sw_icm_start_address[0x40]; 1340 1341 u8 reserved_at_280[0x580]; 1342 }; 1343 1344 struct mlx5_ifc_device_event_cap_bits { 1345 u8 user_affiliated_events[4][0x40]; 1346 1347 u8 user_unaffiliated_events[4][0x40]; 1348 }; 1349 1350 struct mlx5_ifc_virtio_emulation_cap_bits { 1351 u8 desc_tunnel_offload_type[0x1]; 1352 u8 eth_frame_offload_type[0x1]; 1353 u8 virtio_version_1_0[0x1]; 1354 u8 device_features_bits_mask[0xd]; 1355 u8 event_mode[0x8]; 1356 u8 virtio_queue_type[0x8]; 1357 1358 u8 max_tunnel_desc[0x10]; 1359 u8 reserved_at_30[0x3]; 1360 u8 log_doorbell_stride[0x5]; 1361 u8 reserved_at_38[0x3]; 1362 u8 log_doorbell_bar_size[0x5]; 1363 1364 u8 doorbell_bar_offset[0x40]; 1365 1366 u8 max_emulated_devices[0x8]; 1367 u8 max_num_virtio_queues[0x18]; 1368 1369 u8 reserved_at_a0[0x20]; 1370 1371 u8 reserved_at_c0[0x13]; 1372 u8 desc_group_mkey_supported[0x1]; 1373 u8 freeze_to_rdy_supported[0x1]; 1374 u8 reserved_at_d5[0xb]; 1375 1376 u8 reserved_at_e0[0x20]; 1377 1378 u8 umem_1_buffer_param_a[0x20]; 1379 1380 u8 umem_1_buffer_param_b[0x20]; 1381 1382 u8 umem_2_buffer_param_a[0x20]; 1383 1384 u8 umem_2_buffer_param_b[0x20]; 1385 1386 u8 umem_3_buffer_param_a[0x20]; 1387 1388 u8 umem_3_buffer_param_b[0x20]; 1389 1390 u8 reserved_at_1c0[0x640]; 1391 }; 1392 1393 struct mlx5_ifc_tlp_dev_emu_capabilities_bits { 1394 u8 reserved_at_0[0x20]; 1395 1396 u8 reserved_at_20[0x13]; 1397 u8 log_tlp_rsp_gw_page_stride[0x5]; 1398 u8 reserved_at_38[0x8]; 1399 1400 u8 reserved_at_40[0xc0]; 1401 1402 u8 reserved_at_100[0xc]; 1403 u8 tlp_rsp_gw_num_pages[0x4]; 1404 u8 reserved_at_110[0x10]; 1405 1406 u8 reserved_at_120[0xa0]; 1407 1408 u8 tlp_rsp_gw_pages_bar_offset[0x40]; 1409 1410 u8 reserved_at_200[0x600]; 1411 }; 1412 1413 enum { 1414 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1415 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1416 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1417 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1418 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1419 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1420 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1421 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1422 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1423 }; 1424 1425 enum { 1426 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1427 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1428 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1429 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1430 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1431 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1432 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1433 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1434 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1435 }; 1436 1437 struct mlx5_ifc_atomic_caps_bits { 1438 u8 reserved_at_0[0x40]; 1439 1440 u8 atomic_req_8B_endianness_mode[0x2]; 1441 u8 reserved_at_42[0x4]; 1442 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1443 1444 u8 reserved_at_47[0x19]; 1445 1446 u8 reserved_at_60[0x20]; 1447 1448 u8 reserved_at_80[0x10]; 1449 u8 atomic_operations[0x10]; 1450 1451 u8 reserved_at_a0[0x10]; 1452 u8 atomic_size_qp[0x10]; 1453 1454 u8 reserved_at_c0[0x10]; 1455 u8 atomic_size_dc[0x10]; 1456 1457 u8 reserved_at_e0[0x720]; 1458 }; 1459 1460 struct mlx5_ifc_odp_scheme_cap_bits { 1461 u8 reserved_at_0[0x40]; 1462 1463 u8 sig[0x1]; 1464 u8 reserved_at_41[0x4]; 1465 u8 page_prefetch[0x1]; 1466 u8 reserved_at_46[0x1a]; 1467 1468 u8 reserved_at_60[0x20]; 1469 1470 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1471 1472 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1473 1474 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1475 1476 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1477 1478 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1479 1480 u8 reserved_at_120[0xe0]; 1481 }; 1482 1483 struct mlx5_ifc_odp_cap_bits { 1484 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1485 1486 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1487 1488 u8 reserved_at_400[0x200]; 1489 1490 u8 mem_page_fault[0x1]; 1491 u8 reserved_at_601[0x1f]; 1492 1493 u8 reserved_at_620[0x1e0]; 1494 }; 1495 1496 struct mlx5_ifc_tls_cap_bits { 1497 u8 tls_1_2_aes_gcm_128[0x1]; 1498 u8 tls_1_3_aes_gcm_128[0x1]; 1499 u8 tls_1_2_aes_gcm_256[0x1]; 1500 u8 tls_1_3_aes_gcm_256[0x1]; 1501 u8 reserved_at_4[0x1c]; 1502 1503 u8 reserved_at_20[0x7e0]; 1504 }; 1505 1506 struct mlx5_ifc_ipsec_cap_bits { 1507 u8 ipsec_full_offload[0x1]; 1508 u8 ipsec_crypto_offload[0x1]; 1509 u8 ipsec_esn[0x1]; 1510 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1511 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1512 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1513 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1514 u8 reserved_at_7[0x4]; 1515 u8 log_max_ipsec_offload[0x5]; 1516 u8 reserved_at_10[0x10]; 1517 1518 u8 min_log_ipsec_full_replay_window[0x8]; 1519 u8 max_log_ipsec_full_replay_window[0x8]; 1520 u8 reserved_at_30[0x7d0]; 1521 }; 1522 1523 struct mlx5_ifc_macsec_cap_bits { 1524 u8 macsec_epn[0x1]; 1525 u8 reserved_at_1[0x2]; 1526 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1527 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1528 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1529 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1530 u8 reserved_at_7[0x4]; 1531 u8 log_max_macsec_offload[0x5]; 1532 u8 reserved_at_10[0x10]; 1533 1534 u8 min_log_macsec_full_replay_window[0x8]; 1535 u8 max_log_macsec_full_replay_window[0x8]; 1536 u8 reserved_at_30[0x10]; 1537 1538 u8 reserved_at_40[0x7c0]; 1539 }; 1540 1541 struct mlx5_ifc_psp_cap_bits { 1542 u8 reserved_at_0[0x1]; 1543 u8 psp_crypto_offload[0x1]; 1544 u8 reserved_at_2[0x1]; 1545 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1546 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1547 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1548 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1549 u8 reserved_at_7[0x4]; 1550 u8 log_max_num_of_psp_spi[0x5]; 1551 u8 reserved_at_10[0x10]; 1552 1553 u8 reserved_at_20[0x7e0]; 1554 }; 1555 1556 enum { 1557 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1558 MLX5_WQ_TYPE_CYCLIC = 0x1, 1559 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1560 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1561 }; 1562 1563 enum { 1564 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1565 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1566 }; 1567 1568 enum { 1569 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1570 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1571 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1572 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1573 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1574 }; 1575 1576 enum { 1577 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1578 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1579 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1580 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1581 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1583 }; 1584 1585 enum { 1586 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1587 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1588 }; 1589 1590 enum { 1591 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1592 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1593 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1594 }; 1595 1596 enum { 1597 MLX5_CAP_PORT_TYPE_IB = 0x0, 1598 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1599 }; 1600 1601 enum { 1602 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1603 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1604 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1605 }; 1606 1607 enum { 1608 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1609 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1610 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1611 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1612 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1613 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1614 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1615 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1616 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1617 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1618 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1619 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1620 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1621 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1622 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1623 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1624 }; 1625 1626 enum { 1627 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1628 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1629 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1630 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1631 }; 1632 1633 #define MLX5_FC_BULK_SIZE_FACTOR 128 1634 1635 enum mlx5_fc_bulk_alloc_bitmask { 1636 MLX5_FC_BULK_128 = (1 << 0), 1637 MLX5_FC_BULK_256 = (1 << 1), 1638 MLX5_FC_BULK_512 = (1 << 2), 1639 MLX5_FC_BULK_1024 = (1 << 3), 1640 MLX5_FC_BULK_2048 = (1 << 4), 1641 MLX5_FC_BULK_4096 = (1 << 5), 1642 MLX5_FC_BULK_8192 = (1 << 6), 1643 MLX5_FC_BULK_16384 = (1 << 7), 1644 }; 1645 1646 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1647 1648 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1649 1650 enum { 1651 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1652 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1653 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1654 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1655 }; 1656 1657 enum { 1658 MLX5_ID_MODE_FUNCTION_INDEX = 0, 1659 MLX5_ID_MODE_FUNCTION_VHCA_ID = 1, 1660 }; 1661 1662 struct mlx5_ifc_cmd_hca_cap_bits { 1663 u8 reserved_at_0[0x6]; 1664 u8 page_request_disable[0x1]; 1665 u8 abs_native_port_num[0x1]; 1666 u8 reserved_at_8[0x8]; 1667 u8 shared_object_to_user_object_allowed[0x1]; 1668 u8 reserved_at_13[0xe]; 1669 u8 vhca_resource_manager[0x1]; 1670 1671 u8 hca_cap_2[0x1]; 1672 u8 create_lag_when_not_master_up[0x1]; 1673 u8 dtor[0x1]; 1674 u8 event_on_vhca_state_teardown_request[0x1]; 1675 u8 event_on_vhca_state_in_use[0x1]; 1676 u8 event_on_vhca_state_active[0x1]; 1677 u8 event_on_vhca_state_allocated[0x1]; 1678 u8 event_on_vhca_state_invalid[0x1]; 1679 u8 reserved_at_28[0x8]; 1680 u8 vhca_id[0x10]; 1681 1682 u8 reserved_at_40[0x40]; 1683 1684 u8 log_max_srq_sz[0x8]; 1685 u8 log_max_qp_sz[0x8]; 1686 u8 event_cap[0x1]; 1687 u8 reserved_at_91[0x2]; 1688 u8 isolate_vl_tc_new[0x1]; 1689 u8 reserved_at_94[0x4]; 1690 u8 prio_tag_required[0x1]; 1691 u8 reserved_at_99[0x2]; 1692 u8 log_max_qp[0x5]; 1693 1694 u8 reserved_at_a0[0x3]; 1695 u8 ece_support[0x1]; 1696 u8 reserved_at_a4[0x5]; 1697 u8 reg_c_preserve[0x1]; 1698 u8 reserved_at_aa[0x1]; 1699 u8 log_max_srq[0x5]; 1700 u8 reserved_at_b0[0x1]; 1701 u8 uplink_follow[0x1]; 1702 u8 ts_cqe_to_dest_cqn[0x1]; 1703 u8 reserved_at_b3[0x6]; 1704 u8 go_back_n[0x1]; 1705 u8 reserved_at_ba[0x6]; 1706 1707 u8 max_sgl_for_optimized_performance[0x8]; 1708 u8 log_max_cq_sz[0x8]; 1709 u8 relaxed_ordering_write_umr[0x1]; 1710 u8 relaxed_ordering_read_umr[0x1]; 1711 u8 reserved_at_d2[0x7]; 1712 u8 virtio_net_device_emualtion_manager[0x1]; 1713 u8 virtio_blk_device_emualtion_manager[0x1]; 1714 u8 log_max_cq[0x5]; 1715 1716 u8 log_max_eq_sz[0x8]; 1717 u8 relaxed_ordering_write[0x1]; 1718 u8 relaxed_ordering_read_pci_enabled[0x1]; 1719 u8 log_max_mkey[0x6]; 1720 u8 reserved_at_f0[0x6]; 1721 u8 terminate_scatter_list_mkey[0x1]; 1722 u8 repeated_mkey[0x1]; 1723 u8 dump_fill_mkey[0x1]; 1724 u8 reserved_at_f9[0x2]; 1725 u8 fast_teardown[0x1]; 1726 u8 log_max_eq[0x4]; 1727 1728 u8 max_indirection[0x8]; 1729 u8 fixed_buffer_size[0x1]; 1730 u8 log_max_mrw_sz[0x7]; 1731 u8 force_teardown[0x1]; 1732 u8 reserved_at_111[0x1]; 1733 u8 log_max_bsf_list_size[0x6]; 1734 u8 umr_extended_translation_offset[0x1]; 1735 u8 null_mkey[0x1]; 1736 u8 log_max_klm_list_size[0x6]; 1737 1738 u8 reserved_at_120[0x2]; 1739 u8 qpc_extension[0x1]; 1740 u8 reserved_at_123[0x7]; 1741 u8 log_max_ra_req_dc[0x6]; 1742 u8 reserved_at_130[0x2]; 1743 u8 eth_wqe_too_small[0x1]; 1744 u8 reserved_at_133[0x6]; 1745 u8 vnic_env_cq_overrun[0x1]; 1746 u8 log_max_ra_res_dc[0x6]; 1747 1748 u8 reserved_at_140[0x5]; 1749 u8 release_all_pages[0x1]; 1750 u8 must_not_use[0x1]; 1751 u8 reserved_at_147[0x2]; 1752 u8 roce_accl[0x1]; 1753 u8 log_max_ra_req_qp[0x6]; 1754 u8 reserved_at_150[0xa]; 1755 u8 log_max_ra_res_qp[0x6]; 1756 1757 u8 end_pad[0x1]; 1758 u8 cc_query_allowed[0x1]; 1759 u8 cc_modify_allowed[0x1]; 1760 u8 start_pad[0x1]; 1761 u8 cache_line_128byte[0x1]; 1762 u8 reserved_at_165[0x4]; 1763 u8 rts2rts_qp_counters_set_id[0x1]; 1764 u8 reserved_at_16a[0x2]; 1765 u8 vnic_env_int_rq_oob[0x1]; 1766 u8 sbcam_reg[0x1]; 1767 u8 reserved_at_16e[0x1]; 1768 u8 qcam_reg[0x1]; 1769 u8 gid_table_size[0x10]; 1770 1771 u8 out_of_seq_cnt[0x1]; 1772 u8 vport_counters[0x1]; 1773 u8 retransmission_q_counters[0x1]; 1774 u8 debug[0x1]; 1775 u8 modify_rq_counter_set_id[0x1]; 1776 u8 rq_delay_drop[0x1]; 1777 u8 max_qp_cnt[0xa]; 1778 u8 pkey_table_size[0x10]; 1779 1780 u8 vport_group_manager[0x1]; 1781 u8 vhca_group_manager[0x1]; 1782 u8 ib_virt[0x1]; 1783 u8 eth_virt[0x1]; 1784 u8 vnic_env_queue_counters[0x1]; 1785 u8 ets[0x1]; 1786 u8 nic_flow_table[0x1]; 1787 u8 eswitch_manager[0x1]; 1788 u8 device_memory[0x1]; 1789 u8 mcam_reg[0x1]; 1790 u8 pcam_reg[0x1]; 1791 u8 local_ca_ack_delay[0x5]; 1792 u8 port_module_event[0x1]; 1793 u8 enhanced_error_q_counters[0x1]; 1794 u8 ports_check[0x1]; 1795 u8 reserved_at_1b3[0x1]; 1796 u8 disable_link_up[0x1]; 1797 u8 beacon_led[0x1]; 1798 u8 port_type[0x2]; 1799 u8 num_ports[0x8]; 1800 1801 u8 reserved_at_1c0[0x1]; 1802 u8 pps[0x1]; 1803 u8 pps_modify[0x1]; 1804 u8 log_max_msg[0x5]; 1805 u8 reserved_at_1c8[0x4]; 1806 u8 max_tc[0x4]; 1807 u8 temp_warn_event[0x1]; 1808 u8 dcbx[0x1]; 1809 u8 general_notification_event[0x1]; 1810 u8 reserved_at_1d3[0x2]; 1811 u8 fpga[0x1]; 1812 u8 rol_s[0x1]; 1813 u8 rol_g[0x1]; 1814 u8 reserved_at_1d8[0x1]; 1815 u8 wol_s[0x1]; 1816 u8 wol_g[0x1]; 1817 u8 wol_a[0x1]; 1818 u8 wol_b[0x1]; 1819 u8 wol_m[0x1]; 1820 u8 wol_u[0x1]; 1821 u8 wol_p[0x1]; 1822 1823 u8 stat_rate_support[0x10]; 1824 u8 reserved_at_1f0[0x1]; 1825 u8 pci_sync_for_fw_update_event[0x1]; 1826 u8 reserved_at_1f2[0x6]; 1827 u8 init2_lag_tx_port_affinity[0x1]; 1828 u8 reserved_at_1fa[0x2]; 1829 u8 wqe_based_flow_table_update_cap[0x1]; 1830 u8 cqe_version[0x4]; 1831 1832 u8 compact_address_vector[0x1]; 1833 u8 striding_rq[0x1]; 1834 u8 reserved_at_202[0x1]; 1835 u8 ipoib_enhanced_offloads[0x1]; 1836 u8 ipoib_basic_offloads[0x1]; 1837 u8 reserved_at_205[0x1]; 1838 u8 repeated_block_disabled[0x1]; 1839 u8 umr_modify_entity_size_disabled[0x1]; 1840 u8 umr_modify_atomic_disabled[0x1]; 1841 u8 umr_indirect_mkey_disabled[0x1]; 1842 u8 umr_fence[0x2]; 1843 u8 dc_req_scat_data_cqe[0x1]; 1844 u8 reserved_at_20d[0x2]; 1845 u8 drain_sigerr[0x1]; 1846 u8 cmdif_checksum[0x2]; 1847 u8 sigerr_cqe[0x1]; 1848 u8 reserved_at_213[0x1]; 1849 u8 wq_signature[0x1]; 1850 u8 sctr_data_cqe[0x1]; 1851 u8 reserved_at_216[0x1]; 1852 u8 sho[0x1]; 1853 u8 tph[0x1]; 1854 u8 rf[0x1]; 1855 u8 dct[0x1]; 1856 u8 qos[0x1]; 1857 u8 eth_net_offloads[0x1]; 1858 u8 roce[0x1]; 1859 u8 atomic[0x1]; 1860 u8 reserved_at_21f[0x1]; 1861 1862 u8 cq_oi[0x1]; 1863 u8 cq_resize[0x1]; 1864 u8 cq_moderation[0x1]; 1865 u8 cq_period_mode_modify[0x1]; 1866 u8 reserved_at_224[0x2]; 1867 u8 cq_eq_remap[0x1]; 1868 u8 pg[0x1]; 1869 u8 block_lb_mc[0x1]; 1870 u8 reserved_at_229[0x1]; 1871 u8 scqe_break_moderation[0x1]; 1872 u8 cq_period_start_from_cqe[0x1]; 1873 u8 cd[0x1]; 1874 u8 reserved_at_22d[0x1]; 1875 u8 apm[0x1]; 1876 u8 vector_calc[0x1]; 1877 u8 umr_ptr_rlky[0x1]; 1878 u8 imaicl[0x1]; 1879 u8 qp_packet_based[0x1]; 1880 u8 reserved_at_233[0x3]; 1881 u8 qkv[0x1]; 1882 u8 pkv[0x1]; 1883 u8 set_deth_sqpn[0x1]; 1884 u8 reserved_at_239[0x3]; 1885 u8 xrc[0x1]; 1886 u8 ud[0x1]; 1887 u8 uc[0x1]; 1888 u8 rc[0x1]; 1889 1890 u8 uar_4k[0x1]; 1891 u8 reserved_at_241[0x7]; 1892 u8 fl_rc_qp_when_roce_disabled[0x1]; 1893 u8 regexp_params[0x1]; 1894 u8 uar_sz[0x6]; 1895 u8 port_selection_cap[0x1]; 1896 u8 nic_cap_reg[0x1]; 1897 u8 umem_uid_0[0x1]; 1898 u8 reserved_at_253[0x5]; 1899 u8 log_pg_sz[0x8]; 1900 1901 u8 bf[0x1]; 1902 u8 driver_version[0x1]; 1903 u8 pad_tx_eth_packet[0x1]; 1904 u8 reserved_at_263[0x3]; 1905 u8 mkey_by_name[0x1]; 1906 u8 reserved_at_267[0x4]; 1907 1908 u8 log_bf_reg_size[0x5]; 1909 1910 u8 disciplined_fr_counter[0x1]; 1911 u8 reserved_at_271[0x2]; 1912 u8 qp_error_syndrome[0x1]; 1913 u8 reserved_at_274[0x2]; 1914 u8 lag_dct[0x2]; 1915 u8 lag_tx_port_affinity[0x1]; 1916 u8 lag_native_fdb_selection[0x1]; 1917 u8 reserved_at_27a[0x1]; 1918 u8 lag_master[0x1]; 1919 u8 num_lag_ports[0x4]; 1920 1921 u8 reserved_at_280[0x10]; 1922 u8 max_wqe_sz_sq[0x10]; 1923 1924 u8 icm_mng_function_id_mode[0x1]; 1925 u8 reserved_at_2a1[0x6]; 1926 u8 mkey_pcie_tph[0x1]; 1927 u8 reserved_at_2a8[0x1]; 1928 u8 tis_tir_td_order[0x1]; 1929 1930 u8 psp[0x1]; 1931 u8 shampo[0x1]; 1932 u8 reserved_at_2ac[0x4]; 1933 u8 max_wqe_sz_rq[0x10]; 1934 1935 u8 max_flow_counter_31_16[0x10]; 1936 u8 max_wqe_sz_sq_dc[0x10]; 1937 1938 u8 reserved_at_2e0[0x7]; 1939 u8 max_qp_mcg[0x19]; 1940 1941 u8 reserved_at_300[0x10]; 1942 u8 flow_counter_bulk_alloc[0x8]; 1943 u8 log_max_mcg[0x8]; 1944 1945 u8 reserved_at_320[0x3]; 1946 u8 log_max_transport_domain[0x5]; 1947 u8 reserved_at_328[0x2]; 1948 u8 relaxed_ordering_read[0x1]; 1949 u8 log_max_pd[0x5]; 1950 u8 dp_ordering_ooo_all_ud[0x1]; 1951 u8 dp_ordering_ooo_all_uc[0x1]; 1952 u8 dp_ordering_ooo_all_xrc[0x1]; 1953 u8 dp_ordering_ooo_all_dc[0x1]; 1954 u8 dp_ordering_ooo_all_rc[0x1]; 1955 u8 pcie_reset_using_hotreset_method[0x1]; 1956 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1957 u8 vnic_env_cnt_steering_fail[0x1]; 1958 u8 vport_counter_local_loopback[0x1]; 1959 u8 q_counter_aggregation[0x1]; 1960 u8 q_counter_other_vport[0x1]; 1961 u8 log_max_xrcd[0x5]; 1962 1963 u8 nic_receive_steering_discard[0x1]; 1964 u8 receive_discard_vport_down[0x1]; 1965 u8 transmit_discard_vport_down[0x1]; 1966 u8 eq_overrun_count[0x1]; 1967 u8 reserved_at_344[0x1]; 1968 u8 invalid_command_count[0x1]; 1969 u8 quota_exceeded_count[0x1]; 1970 u8 reserved_at_347[0x1]; 1971 u8 log_max_flow_counter_bulk[0x8]; 1972 u8 max_flow_counter_15_0[0x10]; 1973 1974 1975 u8 reserved_at_360[0x3]; 1976 u8 log_max_rq[0x5]; 1977 u8 ft_alias_sw_vhca_id[0x1]; 1978 u8 reserved_at_369[0x2]; 1979 u8 log_max_sq[0x5]; 1980 u8 reserved_at_370[0x3]; 1981 u8 log_max_tir[0x5]; 1982 u8 reserved_at_378[0x3]; 1983 u8 log_max_tis[0x5]; 1984 1985 u8 basic_cyclic_rcv_wqe[0x1]; 1986 u8 reserved_at_381[0x2]; 1987 u8 log_max_rmp[0x5]; 1988 u8 reserved_at_388[0x3]; 1989 u8 log_max_rqt[0x5]; 1990 u8 reserved_at_390[0x3]; 1991 u8 log_max_rqt_size[0x5]; 1992 u8 tlp_device_emulation_manager[0x1]; 1993 u8 vnic_env_cnt_bar_uar_access[0x1]; 1994 u8 vnic_env_cnt_odp_page_fault[0x1]; 1995 u8 log_max_tis_per_sq[0x5]; 1996 1997 u8 ext_stride_num_range[0x1]; 1998 u8 roce_rw_supported[0x1]; 1999 u8 log_max_current_uc_list_wr_supported[0x1]; 2000 u8 log_max_stride_sz_rq[0x5]; 2001 u8 reserved_at_3a8[0x3]; 2002 u8 log_min_stride_sz_rq[0x5]; 2003 u8 reserved_at_3b0[0x3]; 2004 u8 log_max_stride_sz_sq[0x5]; 2005 u8 reserved_at_3b8[0x3]; 2006 u8 log_min_stride_sz_sq[0x5]; 2007 2008 u8 hairpin[0x1]; 2009 u8 reserved_at_3c1[0x2]; 2010 u8 log_max_hairpin_queues[0x5]; 2011 u8 reserved_at_3c8[0x3]; 2012 u8 log_max_hairpin_wq_data_sz[0x5]; 2013 u8 reserved_at_3d0[0x3]; 2014 u8 log_max_hairpin_num_packets[0x5]; 2015 u8 reserved_at_3d8[0x3]; 2016 u8 log_max_wq_sz[0x5]; 2017 2018 u8 nic_vport_change_event[0x1]; 2019 u8 disable_local_lb_uc[0x1]; 2020 u8 disable_local_lb_mc[0x1]; 2021 u8 log_min_hairpin_wq_data_sz[0x5]; 2022 u8 reserved_at_3e8[0x1]; 2023 u8 silent_mode_set[0x1]; 2024 u8 vhca_state[0x1]; 2025 u8 log_max_vlan_list[0x5]; 2026 u8 reserved_at_3f0[0x3]; 2027 u8 log_max_current_mc_list[0x5]; 2028 u8 reserved_at_3f8[0x1]; 2029 u8 silent_mode_query[0x1]; 2030 u8 reserved_at_3fa[0x1]; 2031 u8 log_max_current_uc_list[0x5]; 2032 2033 u8 general_obj_types[0x40]; 2034 2035 u8 sq_ts_format[0x2]; 2036 u8 rq_ts_format[0x2]; 2037 u8 steering_format_version[0x4]; 2038 u8 create_qp_start_hint[0x18]; 2039 2040 u8 reserved_at_460[0x1]; 2041 u8 ats[0x1]; 2042 u8 cross_vhca_rqt[0x1]; 2043 u8 log_max_uctx[0x5]; 2044 u8 reserved_at_468[0x1]; 2045 u8 crypto[0x1]; 2046 u8 ipsec_offload[0x1]; 2047 u8 log_max_umem[0x5]; 2048 u8 max_num_eqs[0x10]; 2049 2050 u8 reserved_at_480[0x1]; 2051 u8 tls_tx[0x1]; 2052 u8 tls_rx[0x1]; 2053 u8 log_max_l2_table[0x5]; 2054 u8 reserved_at_488[0x8]; 2055 u8 log_uar_page_sz[0x10]; 2056 2057 u8 reserved_at_4a0[0x20]; 2058 u8 device_frequency_mhz[0x20]; 2059 u8 device_frequency_khz[0x20]; 2060 2061 u8 reserved_at_500[0x20]; 2062 u8 num_of_uars_per_page[0x20]; 2063 2064 u8 flex_parser_protocols[0x20]; 2065 2066 u8 max_geneve_tlv_options[0x8]; 2067 u8 reserved_at_568[0x3]; 2068 u8 max_geneve_tlv_option_data_len[0x5]; 2069 u8 reserved_at_570[0x1]; 2070 u8 adv_rdma[0x1]; 2071 u8 reserved_at_572[0x7]; 2072 u8 adv_virtualization[0x1]; 2073 u8 reserved_at_57a[0x6]; 2074 2075 u8 reserved_at_580[0xb]; 2076 u8 log_max_dci_stream_channels[0x5]; 2077 u8 reserved_at_590[0x3]; 2078 u8 log_max_dci_errored_streams[0x5]; 2079 u8 reserved_at_598[0x8]; 2080 2081 u8 reserved_at_5a0[0x10]; 2082 u8 enhanced_cqe_compression[0x1]; 2083 u8 reserved_at_5b1[0x1]; 2084 u8 crossing_vhca_mkey[0x1]; 2085 u8 log_max_dek[0x5]; 2086 u8 reserved_at_5b8[0x4]; 2087 u8 mini_cqe_resp_stride_index[0x1]; 2088 u8 cqe_128_always[0x1]; 2089 u8 cqe_compression_128[0x1]; 2090 u8 cqe_compression[0x1]; 2091 2092 u8 cqe_compression_timeout[0x10]; 2093 u8 cqe_compression_max_num[0x10]; 2094 2095 u8 reserved_at_5e0[0x8]; 2096 u8 flex_parser_id_gtpu_dw_0[0x4]; 2097 u8 reserved_at_5ec[0x4]; 2098 u8 tag_matching[0x1]; 2099 u8 rndv_offload_rc[0x1]; 2100 u8 rndv_offload_dc[0x1]; 2101 u8 log_tag_matching_list_sz[0x5]; 2102 u8 reserved_at_5f8[0x3]; 2103 u8 log_max_xrq[0x5]; 2104 2105 u8 affiliate_nic_vport_criteria[0x8]; 2106 u8 native_port_num[0x8]; 2107 u8 num_vhca_ports[0x8]; 2108 u8 flex_parser_id_gtpu_teid[0x4]; 2109 u8 reserved_at_61c[0x2]; 2110 u8 sw_owner_id[0x1]; 2111 u8 reserved_at_61f[0x1]; 2112 2113 u8 max_num_of_monitor_counters[0x10]; 2114 u8 num_ppcnt_monitor_counters[0x10]; 2115 2116 u8 max_num_sf[0x10]; 2117 u8 num_q_monitor_counters[0x10]; 2118 2119 u8 reserved_at_660[0x20]; 2120 2121 u8 sf[0x1]; 2122 u8 sf_set_partition[0x1]; 2123 u8 reserved_at_682[0x1]; 2124 u8 log_max_sf[0x5]; 2125 u8 apu[0x1]; 2126 u8 reserved_at_689[0x4]; 2127 u8 migration[0x1]; 2128 u8 reserved_at_68e[0x2]; 2129 u8 log_min_sf_size[0x8]; 2130 u8 max_num_sf_partitions[0x8]; 2131 2132 u8 uctx_cap[0x20]; 2133 2134 u8 reserved_at_6c0[0x4]; 2135 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2136 u8 flex_parser_id_icmp_dw1[0x4]; 2137 u8 flex_parser_id_icmp_dw0[0x4]; 2138 u8 flex_parser_id_icmpv6_dw1[0x4]; 2139 u8 flex_parser_id_icmpv6_dw0[0x4]; 2140 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2141 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2142 2143 u8 max_num_match_definer[0x10]; 2144 u8 sf_base_id[0x10]; 2145 2146 u8 flex_parser_id_gtpu_dw_2[0x4]; 2147 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2148 u8 num_total_dynamic_vf_msix[0x18]; 2149 u8 reserved_at_720[0x14]; 2150 u8 dynamic_msix_table_size[0xc]; 2151 u8 reserved_at_740[0xc]; 2152 u8 min_dynamic_vf_msix_table_size[0x4]; 2153 u8 reserved_at_750[0x2]; 2154 u8 data_direct[0x1]; 2155 u8 reserved_at_753[0x1]; 2156 u8 max_dynamic_vf_msix_table_size[0xc]; 2157 2158 u8 reserved_at_760[0x3]; 2159 u8 log_max_num_header_modify_argument[0x5]; 2160 u8 log_header_modify_argument_granularity_offset[0x4]; 2161 u8 log_header_modify_argument_granularity[0x4]; 2162 u8 reserved_at_770[0x3]; 2163 u8 log_header_modify_argument_max_alloc[0x5]; 2164 u8 reserved_at_778[0x8]; 2165 2166 u8 vhca_tunnel_commands[0x40]; 2167 u8 match_definer_format_supported[0x40]; 2168 }; 2169 2170 enum { 2171 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2172 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2173 }; 2174 2175 enum { 2176 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2177 }; 2178 2179 struct mlx5_ifc_cmd_hca_cap_2_bits { 2180 u8 reserved_at_0[0x80]; 2181 2182 u8 migratable[0x1]; 2183 u8 reserved_at_81[0x7]; 2184 u8 dp_ordering_force[0x1]; 2185 u8 reserved_at_89[0x9]; 2186 u8 query_vuid[0x1]; 2187 u8 reserved_at_93[0x5]; 2188 u8 umr_log_entity_size_5[0x1]; 2189 u8 reserved_at_99[0x7]; 2190 2191 u8 max_reformat_insert_size[0x8]; 2192 u8 max_reformat_insert_offset[0x8]; 2193 u8 max_reformat_remove_size[0x8]; 2194 u8 max_reformat_remove_offset[0x8]; 2195 2196 u8 reserved_at_c0[0x8]; 2197 u8 migration_multi_load[0x1]; 2198 u8 migration_tracking_state[0x1]; 2199 u8 multiplane_qp_ud[0x1]; 2200 u8 reserved_at_cb[0x5]; 2201 u8 migration_in_chunks[0x1]; 2202 u8 reserved_at_d1[0x1]; 2203 u8 sf_eq_usage[0x1]; 2204 u8 reserved_at_d3[0x5]; 2205 u8 multiplane[0x1]; 2206 u8 reserved_at_d9[0x7]; 2207 2208 u8 cross_vhca_object_to_object_supported[0x20]; 2209 2210 u8 allowed_object_for_other_vhca_access[0x40]; 2211 2212 u8 reserved_at_140[0x60]; 2213 2214 u8 flow_table_type_2_type[0x8]; 2215 u8 reserved_at_1a8[0x2]; 2216 u8 format_select_dw_8_6_ext[0x1]; 2217 u8 log_min_mkey_entity_size[0x5]; 2218 u8 reserved_at_1b0[0x10]; 2219 2220 u8 general_obj_types_127_64[0x40]; 2221 u8 reserved_at_200[0x20]; 2222 2223 u8 reserved_at_220[0x1]; 2224 u8 sw_vhca_id_valid[0x1]; 2225 u8 sw_vhca_id[0xe]; 2226 u8 reserved_at_230[0x10]; 2227 2228 u8 reserved_at_240[0xb]; 2229 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2230 u8 reserved_at_250[0x10]; 2231 2232 u8 reserved_at_260[0x20]; 2233 2234 u8 format_select_dw_gtpu_dw_0[0x8]; 2235 u8 format_select_dw_gtpu_dw_1[0x8]; 2236 u8 format_select_dw_gtpu_dw_2[0x8]; 2237 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2238 2239 u8 generate_wqe_type[0x20]; 2240 2241 u8 reserved_at_2c0[0xc0]; 2242 2243 u8 reserved_at_380[0xb]; 2244 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2245 u8 ec_vf_vport_base[0x10]; 2246 2247 u8 reserved_at_3a0[0x2]; 2248 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2249 u8 reserved_at_3a8[0x2]; 2250 u8 max_mkey_log_entity_size_mtt[0x6]; 2251 u8 max_rqt_vhca_id[0x10]; 2252 2253 u8 reserved_at_3c0[0x20]; 2254 2255 u8 reserved_at_3e0[0x10]; 2256 u8 pcc_ifa2[0x1]; 2257 u8 reserved_at_3f1[0xf]; 2258 2259 u8 reserved_at_400[0x1]; 2260 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2261 u8 reserved_at_402[0xe]; 2262 u8 return_reg_id[0x10]; 2263 2264 u8 reserved_at_420[0x1c]; 2265 u8 flow_table_hash_type[0x4]; 2266 2267 u8 reserved_at_440[0x8]; 2268 u8 max_num_eqs_24b[0x18]; 2269 2270 u8 reserved_at_460[0x144]; 2271 u8 load_balance_id[0x4]; 2272 u8 reserved_at_5a8[0x18]; 2273 2274 u8 query_adjacent_functions_id[0x1]; 2275 u8 ingress_egress_esw_vport_connect[0x1]; 2276 u8 function_id_type_vhca_id[0x1]; 2277 u8 reserved_at_5c3[0x1]; 2278 u8 lag_per_mp_group[0x1]; 2279 u8 reserved_at_5c5[0xb]; 2280 u8 delegate_vhca_management_profiles[0x10]; 2281 2282 u8 delegated_vhca_max[0x10]; 2283 u8 delegate_vhca_max[0x10]; 2284 2285 u8 reserved_at_600[0x200]; 2286 }; 2287 2288 enum mlx5_ifc_flow_destination_type { 2289 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2290 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2291 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2292 MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX = 0x4, 2293 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2294 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2295 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2296 }; 2297 2298 enum mlx5_flow_table_miss_action { 2299 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2300 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2301 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2302 }; 2303 2304 struct mlx5_ifc_dest_format_struct_bits { 2305 u8 destination_type[0x8]; 2306 u8 destination_id[0x18]; 2307 2308 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2309 u8 packet_reformat[0x1]; 2310 u8 reserved_at_22[0x6]; 2311 u8 destination_table_type[0x8]; 2312 u8 destination_eswitch_owner_vhca_id[0x10]; 2313 }; 2314 2315 struct mlx5_ifc_flow_counter_list_bits { 2316 u8 flow_counter_id[0x20]; 2317 2318 u8 reserved_at_20[0x20]; 2319 }; 2320 2321 struct mlx5_ifc_extended_dest_format_bits { 2322 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2323 2324 u8 packet_reformat_id[0x20]; 2325 2326 u8 reserved_at_60[0x20]; 2327 }; 2328 2329 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2330 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2331 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2332 }; 2333 2334 struct mlx5_ifc_fte_match_param_bits { 2335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2336 2337 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2338 2339 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2340 2341 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2342 2343 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2344 2345 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2346 2347 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2348 2349 u8 reserved_at_e00[0x200]; 2350 }; 2351 2352 enum { 2353 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2354 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2355 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2356 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2357 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2358 }; 2359 2360 struct mlx5_ifc_rx_hash_field_select_bits { 2361 u8 l3_prot_type[0x1]; 2362 u8 l4_prot_type[0x1]; 2363 u8 selected_fields[0x1e]; 2364 }; 2365 2366 enum { 2367 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2368 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2369 }; 2370 2371 enum { 2372 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2373 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2374 }; 2375 2376 struct mlx5_ifc_wq_bits { 2377 u8 wq_type[0x4]; 2378 u8 wq_signature[0x1]; 2379 u8 end_padding_mode[0x2]; 2380 u8 cd_slave[0x1]; 2381 u8 reserved_at_8[0x18]; 2382 2383 u8 hds_skip_first_sge[0x1]; 2384 u8 log2_hds_buf_size[0x3]; 2385 u8 reserved_at_24[0x7]; 2386 u8 page_offset[0x5]; 2387 u8 lwm[0x10]; 2388 2389 u8 reserved_at_40[0x8]; 2390 u8 pd[0x18]; 2391 2392 u8 reserved_at_60[0x8]; 2393 u8 uar_page[0x18]; 2394 2395 u8 dbr_addr[0x40]; 2396 2397 u8 hw_counter[0x20]; 2398 2399 u8 sw_counter[0x20]; 2400 2401 u8 reserved_at_100[0xc]; 2402 u8 log_wq_stride[0x4]; 2403 u8 reserved_at_110[0x3]; 2404 u8 log_wq_pg_sz[0x5]; 2405 u8 reserved_at_118[0x3]; 2406 u8 log_wq_sz[0x5]; 2407 2408 u8 dbr_umem_valid[0x1]; 2409 u8 wq_umem_valid[0x1]; 2410 u8 reserved_at_122[0x1]; 2411 u8 log_hairpin_num_packets[0x5]; 2412 u8 reserved_at_128[0x3]; 2413 u8 log_hairpin_data_sz[0x5]; 2414 2415 u8 reserved_at_130[0x4]; 2416 u8 log_wqe_num_of_strides[0x4]; 2417 u8 two_byte_shift_en[0x1]; 2418 u8 reserved_at_139[0x4]; 2419 u8 log_wqe_stride_size[0x3]; 2420 2421 u8 dbr_umem_id[0x20]; 2422 u8 wq_umem_id[0x20]; 2423 2424 u8 wq_umem_offset[0x40]; 2425 2426 u8 headers_mkey[0x20]; 2427 2428 u8 shampo_enable[0x1]; 2429 u8 reserved_at_1e1[0x1]; 2430 u8 shampo_mode[0x2]; 2431 u8 reserved_at_1e4[0x1]; 2432 u8 log_reservation_size[0x3]; 2433 u8 reserved_at_1e8[0x5]; 2434 u8 log_max_num_of_packets_per_reservation[0x3]; 2435 u8 reserved_at_1f0[0x6]; 2436 u8 log_headers_entry_size[0x2]; 2437 u8 reserved_at_1f8[0x4]; 2438 u8 log_headers_buffer_entry_num[0x4]; 2439 2440 u8 reserved_at_200[0x400]; 2441 2442 struct mlx5_ifc_cmd_pas_bits pas[]; 2443 }; 2444 2445 struct mlx5_ifc_rq_num_bits { 2446 u8 reserved_at_0[0x8]; 2447 u8 rq_num[0x18]; 2448 }; 2449 2450 struct mlx5_ifc_rq_vhca_bits { 2451 u8 reserved_at_0[0x8]; 2452 u8 rq_num[0x18]; 2453 u8 reserved_at_20[0x10]; 2454 u8 rq_vhca_id[0x10]; 2455 }; 2456 2457 struct mlx5_ifc_mac_address_layout_bits { 2458 u8 reserved_at_0[0x10]; 2459 u8 mac_addr_47_32[0x10]; 2460 2461 u8 mac_addr_31_0[0x20]; 2462 }; 2463 2464 struct mlx5_ifc_vlan_layout_bits { 2465 u8 reserved_at_0[0x14]; 2466 u8 vlan[0x0c]; 2467 2468 u8 reserved_at_20[0x20]; 2469 }; 2470 2471 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2472 u8 reserved_at_0[0xa0]; 2473 2474 u8 min_time_between_cnps[0x20]; 2475 2476 u8 reserved_at_c0[0x12]; 2477 u8 cnp_dscp[0x6]; 2478 u8 reserved_at_d8[0x4]; 2479 u8 cnp_prio_mode[0x1]; 2480 u8 cnp_802p_prio[0x3]; 2481 2482 u8 reserved_at_e0[0x720]; 2483 }; 2484 2485 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2486 u8 reserved_at_0[0x60]; 2487 2488 u8 reserved_at_60[0x4]; 2489 u8 clamp_tgt_rate[0x1]; 2490 u8 reserved_at_65[0x3]; 2491 u8 clamp_tgt_rate_after_time_inc[0x1]; 2492 u8 reserved_at_69[0x17]; 2493 2494 u8 reserved_at_80[0x20]; 2495 2496 u8 rpg_time_reset[0x20]; 2497 2498 u8 rpg_byte_reset[0x20]; 2499 2500 u8 rpg_threshold[0x20]; 2501 2502 u8 rpg_max_rate[0x20]; 2503 2504 u8 rpg_ai_rate[0x20]; 2505 2506 u8 rpg_hai_rate[0x20]; 2507 2508 u8 rpg_gd[0x20]; 2509 2510 u8 rpg_min_dec_fac[0x20]; 2511 2512 u8 rpg_min_rate[0x20]; 2513 2514 u8 reserved_at_1c0[0xe0]; 2515 2516 u8 rate_to_set_on_first_cnp[0x20]; 2517 2518 u8 dce_tcp_g[0x20]; 2519 2520 u8 dce_tcp_rtt[0x20]; 2521 2522 u8 rate_reduce_monitor_period[0x20]; 2523 2524 u8 reserved_at_320[0x20]; 2525 2526 u8 initial_alpha_value[0x20]; 2527 2528 u8 reserved_at_360[0x4a0]; 2529 }; 2530 2531 struct mlx5_ifc_cong_control_r_roce_general_bits { 2532 u8 reserved_at_0[0x80]; 2533 2534 u8 reserved_at_80[0x10]; 2535 u8 rtt_resp_dscp_valid[0x1]; 2536 u8 reserved_at_91[0x9]; 2537 u8 rtt_resp_dscp[0x6]; 2538 2539 u8 reserved_at_a0[0x760]; 2540 }; 2541 2542 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2543 u8 reserved_at_0[0x80]; 2544 2545 u8 rppp_max_rps[0x20]; 2546 2547 u8 rpg_time_reset[0x20]; 2548 2549 u8 rpg_byte_reset[0x20]; 2550 2551 u8 rpg_threshold[0x20]; 2552 2553 u8 rpg_max_rate[0x20]; 2554 2555 u8 rpg_ai_rate[0x20]; 2556 2557 u8 rpg_hai_rate[0x20]; 2558 2559 u8 rpg_gd[0x20]; 2560 2561 u8 rpg_min_dec_fac[0x20]; 2562 2563 u8 rpg_min_rate[0x20]; 2564 2565 u8 reserved_at_1c0[0x640]; 2566 }; 2567 2568 enum { 2569 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2570 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2571 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2572 }; 2573 2574 struct mlx5_ifc_resize_field_select_bits { 2575 u8 resize_field_select[0x20]; 2576 }; 2577 2578 struct mlx5_ifc_resource_dump_bits { 2579 u8 more_dump[0x1]; 2580 u8 inline_dump[0x1]; 2581 u8 reserved_at_2[0xa]; 2582 u8 seq_num[0x4]; 2583 u8 segment_type[0x10]; 2584 2585 u8 reserved_at_20[0x10]; 2586 u8 vhca_id[0x10]; 2587 2588 u8 index1[0x20]; 2589 2590 u8 index2[0x20]; 2591 2592 u8 num_of_obj1[0x10]; 2593 u8 num_of_obj2[0x10]; 2594 2595 u8 reserved_at_a0[0x20]; 2596 2597 u8 device_opaque[0x40]; 2598 2599 u8 mkey[0x20]; 2600 2601 u8 size[0x20]; 2602 2603 u8 address[0x40]; 2604 2605 u8 inline_data[52][0x20]; 2606 }; 2607 2608 struct mlx5_ifc_resource_dump_menu_record_bits { 2609 u8 reserved_at_0[0x4]; 2610 u8 num_of_obj2_supports_active[0x1]; 2611 u8 num_of_obj2_supports_all[0x1]; 2612 u8 must_have_num_of_obj2[0x1]; 2613 u8 support_num_of_obj2[0x1]; 2614 u8 num_of_obj1_supports_active[0x1]; 2615 u8 num_of_obj1_supports_all[0x1]; 2616 u8 must_have_num_of_obj1[0x1]; 2617 u8 support_num_of_obj1[0x1]; 2618 u8 must_have_index2[0x1]; 2619 u8 support_index2[0x1]; 2620 u8 must_have_index1[0x1]; 2621 u8 support_index1[0x1]; 2622 u8 segment_type[0x10]; 2623 2624 u8 segment_name[4][0x20]; 2625 2626 u8 index1_name[4][0x20]; 2627 2628 u8 index2_name[4][0x20]; 2629 }; 2630 2631 struct mlx5_ifc_resource_dump_segment_header_bits { 2632 u8 length_dw[0x10]; 2633 u8 segment_type[0x10]; 2634 }; 2635 2636 struct mlx5_ifc_resource_dump_command_segment_bits { 2637 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2638 2639 u8 segment_called[0x10]; 2640 u8 vhca_id[0x10]; 2641 2642 u8 index1[0x20]; 2643 2644 u8 index2[0x20]; 2645 2646 u8 num_of_obj1[0x10]; 2647 u8 num_of_obj2[0x10]; 2648 }; 2649 2650 struct mlx5_ifc_resource_dump_error_segment_bits { 2651 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2652 2653 u8 reserved_at_20[0x10]; 2654 u8 syndrome_id[0x10]; 2655 2656 u8 reserved_at_40[0x40]; 2657 2658 u8 error[8][0x20]; 2659 }; 2660 2661 struct mlx5_ifc_resource_dump_info_segment_bits { 2662 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2663 2664 u8 reserved_at_20[0x18]; 2665 u8 dump_version[0x8]; 2666 2667 u8 hw_version[0x20]; 2668 2669 u8 fw_version[0x20]; 2670 }; 2671 2672 struct mlx5_ifc_resource_dump_menu_segment_bits { 2673 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2674 2675 u8 reserved_at_20[0x10]; 2676 u8 num_of_records[0x10]; 2677 2678 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2679 }; 2680 2681 struct mlx5_ifc_resource_dump_resource_segment_bits { 2682 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2683 2684 u8 reserved_at_20[0x20]; 2685 2686 u8 index1[0x20]; 2687 2688 u8 index2[0x20]; 2689 2690 u8 payload[][0x20]; 2691 }; 2692 2693 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2694 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2695 }; 2696 2697 struct mlx5_ifc_menu_resource_dump_response_bits { 2698 struct mlx5_ifc_resource_dump_info_segment_bits info; 2699 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2700 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2701 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2702 }; 2703 2704 enum { 2705 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2706 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2707 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2708 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2709 }; 2710 2711 struct mlx5_ifc_modify_field_select_bits { 2712 u8 modify_field_select[0x20]; 2713 }; 2714 2715 struct mlx5_ifc_field_select_r_roce_np_bits { 2716 u8 field_select_r_roce_np[0x20]; 2717 }; 2718 2719 struct mlx5_ifc_field_select_r_roce_rp_bits { 2720 u8 field_select_r_roce_rp[0x20]; 2721 }; 2722 2723 enum { 2724 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2725 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2726 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2727 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2728 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2729 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2730 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2731 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2732 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2733 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2734 }; 2735 2736 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2737 u8 field_select_8021qaurp[0x20]; 2738 }; 2739 2740 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2741 u8 total_successful_recovery_events[0x20]; 2742 2743 u8 reserved_at_20[0x7a0]; 2744 }; 2745 2746 struct mlx5_ifc_phys_layer_cntrs_bits { 2747 u8 time_since_last_clear_high[0x20]; 2748 2749 u8 time_since_last_clear_low[0x20]; 2750 2751 u8 symbol_errors_high[0x20]; 2752 2753 u8 symbol_errors_low[0x20]; 2754 2755 u8 sync_headers_errors_high[0x20]; 2756 2757 u8 sync_headers_errors_low[0x20]; 2758 2759 u8 edpl_bip_errors_lane0_high[0x20]; 2760 2761 u8 edpl_bip_errors_lane0_low[0x20]; 2762 2763 u8 edpl_bip_errors_lane1_high[0x20]; 2764 2765 u8 edpl_bip_errors_lane1_low[0x20]; 2766 2767 u8 edpl_bip_errors_lane2_high[0x20]; 2768 2769 u8 edpl_bip_errors_lane2_low[0x20]; 2770 2771 u8 edpl_bip_errors_lane3_high[0x20]; 2772 2773 u8 edpl_bip_errors_lane3_low[0x20]; 2774 2775 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2776 2777 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2778 2779 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2780 2781 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2782 2783 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2784 2785 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2786 2787 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2788 2789 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2790 2791 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2792 2793 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2794 2795 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2796 2797 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2798 2799 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2800 2801 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2802 2803 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2804 2805 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2806 2807 u8 rs_fec_corrected_blocks_high[0x20]; 2808 2809 u8 rs_fec_corrected_blocks_low[0x20]; 2810 2811 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2812 2813 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2814 2815 u8 rs_fec_no_errors_blocks_high[0x20]; 2816 2817 u8 rs_fec_no_errors_blocks_low[0x20]; 2818 2819 u8 rs_fec_single_error_blocks_high[0x20]; 2820 2821 u8 rs_fec_single_error_blocks_low[0x20]; 2822 2823 u8 rs_fec_corrected_symbols_total_high[0x20]; 2824 2825 u8 rs_fec_corrected_symbols_total_low[0x20]; 2826 2827 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2828 2829 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2830 2831 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2832 2833 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2834 2835 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2836 2837 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2838 2839 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2840 2841 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2842 2843 u8 link_down_events[0x20]; 2844 2845 u8 successful_recovery_events[0x20]; 2846 2847 u8 reserved_at_640[0x180]; 2848 }; 2849 2850 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2851 u8 time_since_last_clear_high[0x20]; 2852 2853 u8 time_since_last_clear_low[0x20]; 2854 2855 u8 phy_received_bits_high[0x20]; 2856 2857 u8 phy_received_bits_low[0x20]; 2858 2859 u8 phy_symbol_errors_high[0x20]; 2860 2861 u8 phy_symbol_errors_low[0x20]; 2862 2863 u8 phy_corrected_bits_high[0x20]; 2864 2865 u8 phy_corrected_bits_low[0x20]; 2866 2867 u8 phy_corrected_bits_lane0_high[0x20]; 2868 2869 u8 phy_corrected_bits_lane0_low[0x20]; 2870 2871 u8 phy_corrected_bits_lane1_high[0x20]; 2872 2873 u8 phy_corrected_bits_lane1_low[0x20]; 2874 2875 u8 phy_corrected_bits_lane2_high[0x20]; 2876 2877 u8 phy_corrected_bits_lane2_low[0x20]; 2878 2879 u8 phy_corrected_bits_lane3_high[0x20]; 2880 2881 u8 phy_corrected_bits_lane3_low[0x20]; 2882 2883 u8 reserved_at_200[0x5c0]; 2884 }; 2885 2886 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2887 u8 symbol_error_counter[0x10]; 2888 2889 u8 link_error_recovery_counter[0x8]; 2890 2891 u8 link_downed_counter[0x8]; 2892 2893 u8 port_rcv_errors[0x10]; 2894 2895 u8 port_rcv_remote_physical_errors[0x10]; 2896 2897 u8 port_rcv_switch_relay_errors[0x10]; 2898 2899 u8 port_xmit_discards[0x10]; 2900 2901 u8 port_xmit_constraint_errors[0x8]; 2902 2903 u8 port_rcv_constraint_errors[0x8]; 2904 2905 u8 reserved_at_70[0x8]; 2906 2907 u8 link_overrun_errors[0x8]; 2908 2909 u8 reserved_at_80[0x10]; 2910 2911 u8 vl_15_dropped[0x10]; 2912 2913 u8 reserved_at_a0[0x80]; 2914 2915 u8 port_xmit_wait[0x20]; 2916 }; 2917 2918 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2919 u8 reserved_at_0[0x300]; 2920 2921 u8 port_xmit_data_high[0x20]; 2922 2923 u8 port_xmit_data_low[0x20]; 2924 2925 u8 port_rcv_data_high[0x20]; 2926 2927 u8 port_rcv_data_low[0x20]; 2928 2929 u8 port_xmit_pkts_high[0x20]; 2930 2931 u8 port_xmit_pkts_low[0x20]; 2932 2933 u8 port_rcv_pkts_high[0x20]; 2934 2935 u8 port_rcv_pkts_low[0x20]; 2936 2937 u8 reserved_at_400[0x80]; 2938 2939 u8 port_unicast_xmit_pkts_high[0x20]; 2940 2941 u8 port_unicast_xmit_pkts_low[0x20]; 2942 2943 u8 port_multicast_xmit_pkts_high[0x20]; 2944 2945 u8 port_multicast_xmit_pkts_low[0x20]; 2946 2947 u8 port_unicast_rcv_pkts_high[0x20]; 2948 2949 u8 port_unicast_rcv_pkts_low[0x20]; 2950 2951 u8 port_multicast_rcv_pkts_high[0x20]; 2952 2953 u8 port_multicast_rcv_pkts_low[0x20]; 2954 2955 u8 reserved_at_580[0x240]; 2956 }; 2957 2958 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2959 u8 transmit_queue_high[0x20]; 2960 2961 u8 transmit_queue_low[0x20]; 2962 2963 u8 no_buffer_discard_uc_high[0x20]; 2964 2965 u8 no_buffer_discard_uc_low[0x20]; 2966 2967 u8 reserved_at_80[0x740]; 2968 }; 2969 2970 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2971 u8 wred_discard_high[0x20]; 2972 2973 u8 wred_discard_low[0x20]; 2974 2975 u8 ecn_marked_tc_high[0x20]; 2976 2977 u8 ecn_marked_tc_low[0x20]; 2978 2979 u8 reserved_at_80[0x740]; 2980 }; 2981 2982 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2983 u8 rx_octets_high[0x20]; 2984 2985 u8 rx_octets_low[0x20]; 2986 2987 u8 reserved_at_40[0xc0]; 2988 2989 u8 rx_frames_high[0x20]; 2990 2991 u8 rx_frames_low[0x20]; 2992 2993 u8 tx_octets_high[0x20]; 2994 2995 u8 tx_octets_low[0x20]; 2996 2997 u8 reserved_at_180[0xc0]; 2998 2999 u8 tx_frames_high[0x20]; 3000 3001 u8 tx_frames_low[0x20]; 3002 3003 u8 rx_pause_high[0x20]; 3004 3005 u8 rx_pause_low[0x20]; 3006 3007 u8 rx_pause_duration_high[0x20]; 3008 3009 u8 rx_pause_duration_low[0x20]; 3010 3011 u8 tx_pause_high[0x20]; 3012 3013 u8 tx_pause_low[0x20]; 3014 3015 u8 tx_pause_duration_high[0x20]; 3016 3017 u8 tx_pause_duration_low[0x20]; 3018 3019 u8 rx_pause_transition_high[0x20]; 3020 3021 u8 rx_pause_transition_low[0x20]; 3022 3023 u8 rx_discards_high[0x20]; 3024 3025 u8 rx_discards_low[0x20]; 3026 3027 u8 device_stall_minor_watermark_cnt_high[0x20]; 3028 3029 u8 device_stall_minor_watermark_cnt_low[0x20]; 3030 3031 u8 device_stall_critical_watermark_cnt_high[0x20]; 3032 3033 u8 device_stall_critical_watermark_cnt_low[0x20]; 3034 3035 u8 reserved_at_480[0x340]; 3036 }; 3037 3038 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 3039 u8 port_transmit_wait_high[0x20]; 3040 3041 u8 port_transmit_wait_low[0x20]; 3042 3043 u8 reserved_at_40[0x100]; 3044 3045 u8 rx_buffer_almost_full_high[0x20]; 3046 3047 u8 rx_buffer_almost_full_low[0x20]; 3048 3049 u8 rx_buffer_full_high[0x20]; 3050 3051 u8 rx_buffer_full_low[0x20]; 3052 3053 u8 rx_icrc_encapsulated_high[0x20]; 3054 3055 u8 rx_icrc_encapsulated_low[0x20]; 3056 3057 u8 reserved_at_200[0x5c0]; 3058 }; 3059 3060 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3061 u8 dot3stats_alignment_errors_high[0x20]; 3062 3063 u8 dot3stats_alignment_errors_low[0x20]; 3064 3065 u8 dot3stats_fcs_errors_high[0x20]; 3066 3067 u8 dot3stats_fcs_errors_low[0x20]; 3068 3069 u8 dot3stats_single_collision_frames_high[0x20]; 3070 3071 u8 dot3stats_single_collision_frames_low[0x20]; 3072 3073 u8 dot3stats_multiple_collision_frames_high[0x20]; 3074 3075 u8 dot3stats_multiple_collision_frames_low[0x20]; 3076 3077 u8 dot3stats_sqe_test_errors_high[0x20]; 3078 3079 u8 dot3stats_sqe_test_errors_low[0x20]; 3080 3081 u8 dot3stats_deferred_transmissions_high[0x20]; 3082 3083 u8 dot3stats_deferred_transmissions_low[0x20]; 3084 3085 u8 dot3stats_late_collisions_high[0x20]; 3086 3087 u8 dot3stats_late_collisions_low[0x20]; 3088 3089 u8 dot3stats_excessive_collisions_high[0x20]; 3090 3091 u8 dot3stats_excessive_collisions_low[0x20]; 3092 3093 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3094 3095 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3096 3097 u8 dot3stats_carrier_sense_errors_high[0x20]; 3098 3099 u8 dot3stats_carrier_sense_errors_low[0x20]; 3100 3101 u8 dot3stats_frame_too_longs_high[0x20]; 3102 3103 u8 dot3stats_frame_too_longs_low[0x20]; 3104 3105 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3106 3107 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3108 3109 u8 dot3stats_symbol_errors_high[0x20]; 3110 3111 u8 dot3stats_symbol_errors_low[0x20]; 3112 3113 u8 dot3control_in_unknown_opcodes_high[0x20]; 3114 3115 u8 dot3control_in_unknown_opcodes_low[0x20]; 3116 3117 u8 dot3in_pause_frames_high[0x20]; 3118 3119 u8 dot3in_pause_frames_low[0x20]; 3120 3121 u8 dot3out_pause_frames_high[0x20]; 3122 3123 u8 dot3out_pause_frames_low[0x20]; 3124 3125 u8 reserved_at_400[0x3c0]; 3126 }; 3127 3128 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3129 u8 ether_stats_drop_events_high[0x20]; 3130 3131 u8 ether_stats_drop_events_low[0x20]; 3132 3133 u8 ether_stats_octets_high[0x20]; 3134 3135 u8 ether_stats_octets_low[0x20]; 3136 3137 u8 ether_stats_pkts_high[0x20]; 3138 3139 u8 ether_stats_pkts_low[0x20]; 3140 3141 u8 ether_stats_broadcast_pkts_high[0x20]; 3142 3143 u8 ether_stats_broadcast_pkts_low[0x20]; 3144 3145 u8 ether_stats_multicast_pkts_high[0x20]; 3146 3147 u8 ether_stats_multicast_pkts_low[0x20]; 3148 3149 u8 ether_stats_crc_align_errors_high[0x20]; 3150 3151 u8 ether_stats_crc_align_errors_low[0x20]; 3152 3153 u8 ether_stats_undersize_pkts_high[0x20]; 3154 3155 u8 ether_stats_undersize_pkts_low[0x20]; 3156 3157 u8 ether_stats_oversize_pkts_high[0x20]; 3158 3159 u8 ether_stats_oversize_pkts_low[0x20]; 3160 3161 u8 ether_stats_fragments_high[0x20]; 3162 3163 u8 ether_stats_fragments_low[0x20]; 3164 3165 u8 ether_stats_jabbers_high[0x20]; 3166 3167 u8 ether_stats_jabbers_low[0x20]; 3168 3169 u8 ether_stats_collisions_high[0x20]; 3170 3171 u8 ether_stats_collisions_low[0x20]; 3172 3173 u8 ether_stats_pkts64octets_high[0x20]; 3174 3175 u8 ether_stats_pkts64octets_low[0x20]; 3176 3177 u8 ether_stats_pkts65to127octets_high[0x20]; 3178 3179 u8 ether_stats_pkts65to127octets_low[0x20]; 3180 3181 u8 ether_stats_pkts128to255octets_high[0x20]; 3182 3183 u8 ether_stats_pkts128to255octets_low[0x20]; 3184 3185 u8 ether_stats_pkts256to511octets_high[0x20]; 3186 3187 u8 ether_stats_pkts256to511octets_low[0x20]; 3188 3189 u8 ether_stats_pkts512to1023octets_high[0x20]; 3190 3191 u8 ether_stats_pkts512to1023octets_low[0x20]; 3192 3193 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3194 3195 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3196 3197 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3198 3199 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3200 3201 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3202 3203 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3204 3205 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3206 3207 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3208 3209 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3210 3211 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3212 3213 u8 reserved_at_540[0x280]; 3214 }; 3215 3216 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3217 u8 if_in_octets_high[0x20]; 3218 3219 u8 if_in_octets_low[0x20]; 3220 3221 u8 if_in_ucast_pkts_high[0x20]; 3222 3223 u8 if_in_ucast_pkts_low[0x20]; 3224 3225 u8 if_in_discards_high[0x20]; 3226 3227 u8 if_in_discards_low[0x20]; 3228 3229 u8 if_in_errors_high[0x20]; 3230 3231 u8 if_in_errors_low[0x20]; 3232 3233 u8 if_in_unknown_protos_high[0x20]; 3234 3235 u8 if_in_unknown_protos_low[0x20]; 3236 3237 u8 if_out_octets_high[0x20]; 3238 3239 u8 if_out_octets_low[0x20]; 3240 3241 u8 if_out_ucast_pkts_high[0x20]; 3242 3243 u8 if_out_ucast_pkts_low[0x20]; 3244 3245 u8 if_out_discards_high[0x20]; 3246 3247 u8 if_out_discards_low[0x20]; 3248 3249 u8 if_out_errors_high[0x20]; 3250 3251 u8 if_out_errors_low[0x20]; 3252 3253 u8 if_in_multicast_pkts_high[0x20]; 3254 3255 u8 if_in_multicast_pkts_low[0x20]; 3256 3257 u8 if_in_broadcast_pkts_high[0x20]; 3258 3259 u8 if_in_broadcast_pkts_low[0x20]; 3260 3261 u8 if_out_multicast_pkts_high[0x20]; 3262 3263 u8 if_out_multicast_pkts_low[0x20]; 3264 3265 u8 if_out_broadcast_pkts_high[0x20]; 3266 3267 u8 if_out_broadcast_pkts_low[0x20]; 3268 3269 u8 reserved_at_340[0x480]; 3270 }; 3271 3272 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3273 u8 a_frames_transmitted_ok_high[0x20]; 3274 3275 u8 a_frames_transmitted_ok_low[0x20]; 3276 3277 u8 a_frames_received_ok_high[0x20]; 3278 3279 u8 a_frames_received_ok_low[0x20]; 3280 3281 u8 a_frame_check_sequence_errors_high[0x20]; 3282 3283 u8 a_frame_check_sequence_errors_low[0x20]; 3284 3285 u8 a_alignment_errors_high[0x20]; 3286 3287 u8 a_alignment_errors_low[0x20]; 3288 3289 u8 a_octets_transmitted_ok_high[0x20]; 3290 3291 u8 a_octets_transmitted_ok_low[0x20]; 3292 3293 u8 a_octets_received_ok_high[0x20]; 3294 3295 u8 a_octets_received_ok_low[0x20]; 3296 3297 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3298 3299 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3300 3301 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3302 3303 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3304 3305 u8 a_multicast_frames_received_ok_high[0x20]; 3306 3307 u8 a_multicast_frames_received_ok_low[0x20]; 3308 3309 u8 a_broadcast_frames_received_ok_high[0x20]; 3310 3311 u8 a_broadcast_frames_received_ok_low[0x20]; 3312 3313 u8 a_in_range_length_errors_high[0x20]; 3314 3315 u8 a_in_range_length_errors_low[0x20]; 3316 3317 u8 a_out_of_range_length_field_high[0x20]; 3318 3319 u8 a_out_of_range_length_field_low[0x20]; 3320 3321 u8 a_frame_too_long_errors_high[0x20]; 3322 3323 u8 a_frame_too_long_errors_low[0x20]; 3324 3325 u8 a_symbol_error_during_carrier_high[0x20]; 3326 3327 u8 a_symbol_error_during_carrier_low[0x20]; 3328 3329 u8 a_mac_control_frames_transmitted_high[0x20]; 3330 3331 u8 a_mac_control_frames_transmitted_low[0x20]; 3332 3333 u8 a_mac_control_frames_received_high[0x20]; 3334 3335 u8 a_mac_control_frames_received_low[0x20]; 3336 3337 u8 a_unsupported_opcodes_received_high[0x20]; 3338 3339 u8 a_unsupported_opcodes_received_low[0x20]; 3340 3341 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3342 3343 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3344 3345 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3346 3347 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3348 3349 u8 reserved_at_4c0[0x300]; 3350 }; 3351 3352 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3353 u8 life_time_counter_high[0x20]; 3354 3355 u8 life_time_counter_low[0x20]; 3356 3357 u8 rx_errors[0x20]; 3358 3359 u8 tx_errors[0x20]; 3360 3361 u8 l0_to_recovery_eieos[0x20]; 3362 3363 u8 l0_to_recovery_ts[0x20]; 3364 3365 u8 l0_to_recovery_framing[0x20]; 3366 3367 u8 l0_to_recovery_retrain[0x20]; 3368 3369 u8 crc_error_dllp[0x20]; 3370 3371 u8 crc_error_tlp[0x20]; 3372 3373 u8 tx_overflow_buffer_pkt_high[0x20]; 3374 3375 u8 tx_overflow_buffer_pkt_low[0x20]; 3376 3377 u8 outbound_stalled_reads[0x20]; 3378 3379 u8 outbound_stalled_writes[0x20]; 3380 3381 u8 outbound_stalled_reads_events[0x20]; 3382 3383 u8 outbound_stalled_writes_events[0x20]; 3384 3385 u8 reserved_at_200[0x5c0]; 3386 }; 3387 3388 struct mlx5_ifc_cmd_inter_comp_event_bits { 3389 u8 command_completion_vector[0x20]; 3390 3391 u8 reserved_at_20[0xc0]; 3392 }; 3393 3394 struct mlx5_ifc_stall_vl_event_bits { 3395 u8 reserved_at_0[0x18]; 3396 u8 port_num[0x1]; 3397 u8 reserved_at_19[0x3]; 3398 u8 vl[0x4]; 3399 3400 u8 reserved_at_20[0xa0]; 3401 }; 3402 3403 struct mlx5_ifc_db_bf_congestion_event_bits { 3404 u8 event_subtype[0x8]; 3405 u8 reserved_at_8[0x8]; 3406 u8 congestion_level[0x8]; 3407 u8 reserved_at_18[0x8]; 3408 3409 u8 reserved_at_20[0xa0]; 3410 }; 3411 3412 struct mlx5_ifc_gpio_event_bits { 3413 u8 reserved_at_0[0x60]; 3414 3415 u8 gpio_event_hi[0x20]; 3416 3417 u8 gpio_event_lo[0x20]; 3418 3419 u8 reserved_at_a0[0x40]; 3420 }; 3421 3422 struct mlx5_ifc_port_state_change_event_bits { 3423 u8 reserved_at_0[0x40]; 3424 3425 u8 port_num[0x4]; 3426 u8 reserved_at_44[0x1c]; 3427 3428 u8 reserved_at_60[0x80]; 3429 }; 3430 3431 struct mlx5_ifc_dropped_packet_logged_bits { 3432 u8 reserved_at_0[0xe0]; 3433 }; 3434 3435 struct mlx5_ifc_nic_cap_reg_bits { 3436 u8 reserved_at_0[0x1a]; 3437 u8 vhca_icm_ctrl[0x1]; 3438 u8 reserved_at_1b[0x5]; 3439 3440 u8 reserved_at_20[0x60]; 3441 }; 3442 3443 struct mlx5_ifc_default_timeout_bits { 3444 u8 to_multiplier[0x3]; 3445 u8 reserved_at_3[0x9]; 3446 u8 to_value[0x14]; 3447 }; 3448 3449 struct mlx5_ifc_dtor_reg_bits { 3450 u8 reserved_at_0[0x20]; 3451 3452 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3453 3454 u8 reserved_at_40[0x60]; 3455 3456 struct mlx5_ifc_default_timeout_bits health_poll_to; 3457 3458 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3459 3460 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3461 3462 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3463 3464 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3465 3466 struct mlx5_ifc_default_timeout_bits tear_down_to; 3467 3468 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3469 3470 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3471 3472 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3473 3474 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3475 3476 u8 reserved_at_1c0[0x20]; 3477 }; 3478 3479 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3480 u8 vhca_id_valid[0x1]; 3481 u8 reserved_at_1[0xf]; 3482 u8 vhca_id[0x10]; 3483 3484 u8 reserved_at_20[0xa0]; 3485 3486 u8 cur_alloc_icm[0x20]; 3487 3488 u8 reserved_at_e0[0x120]; 3489 }; 3490 3491 enum { 3492 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3493 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3494 }; 3495 3496 struct mlx5_ifc_cq_error_bits { 3497 u8 reserved_at_0[0x8]; 3498 u8 cqn[0x18]; 3499 3500 u8 reserved_at_20[0x20]; 3501 3502 u8 reserved_at_40[0x18]; 3503 u8 syndrome[0x8]; 3504 3505 u8 reserved_at_60[0x80]; 3506 }; 3507 3508 struct mlx5_ifc_rdma_page_fault_event_bits { 3509 u8 bytes_committed[0x20]; 3510 3511 u8 r_key[0x20]; 3512 3513 u8 reserved_at_40[0x10]; 3514 u8 packet_len[0x10]; 3515 3516 u8 rdma_op_len[0x20]; 3517 3518 u8 rdma_va[0x40]; 3519 3520 u8 reserved_at_c0[0x5]; 3521 u8 rdma[0x1]; 3522 u8 write[0x1]; 3523 u8 requestor[0x1]; 3524 u8 qp_number[0x18]; 3525 }; 3526 3527 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3528 u8 bytes_committed[0x20]; 3529 3530 u8 reserved_at_20[0x10]; 3531 u8 wqe_index[0x10]; 3532 3533 u8 reserved_at_40[0x10]; 3534 u8 len[0x10]; 3535 3536 u8 reserved_at_60[0x60]; 3537 3538 u8 reserved_at_c0[0x5]; 3539 u8 rdma[0x1]; 3540 u8 write_read[0x1]; 3541 u8 requestor[0x1]; 3542 u8 qpn[0x18]; 3543 }; 3544 3545 struct mlx5_ifc_qp_events_bits { 3546 u8 reserved_at_0[0xa0]; 3547 3548 u8 type[0x8]; 3549 u8 reserved_at_a8[0x18]; 3550 3551 u8 reserved_at_c0[0x8]; 3552 u8 qpn_rqn_sqn[0x18]; 3553 }; 3554 3555 struct mlx5_ifc_dct_events_bits { 3556 u8 reserved_at_0[0xc0]; 3557 3558 u8 reserved_at_c0[0x8]; 3559 u8 dct_number[0x18]; 3560 }; 3561 3562 struct mlx5_ifc_comp_event_bits { 3563 u8 reserved_at_0[0xc0]; 3564 3565 u8 reserved_at_c0[0x8]; 3566 u8 cq_number[0x18]; 3567 }; 3568 3569 enum { 3570 MLX5_QPC_STATE_RST = 0x0, 3571 MLX5_QPC_STATE_INIT = 0x1, 3572 MLX5_QPC_STATE_RTR = 0x2, 3573 MLX5_QPC_STATE_RTS = 0x3, 3574 MLX5_QPC_STATE_SQER = 0x4, 3575 MLX5_QPC_STATE_ERR = 0x6, 3576 MLX5_QPC_STATE_SQD = 0x7, 3577 MLX5_QPC_STATE_SUSPENDED = 0x9, 3578 }; 3579 3580 enum { 3581 MLX5_QPC_ST_RC = 0x0, 3582 MLX5_QPC_ST_UC = 0x1, 3583 MLX5_QPC_ST_UD = 0x2, 3584 MLX5_QPC_ST_XRC = 0x3, 3585 MLX5_QPC_ST_DCI = 0x5, 3586 MLX5_QPC_ST_QP0 = 0x7, 3587 MLX5_QPC_ST_QP1 = 0x8, 3588 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3589 MLX5_QPC_ST_REG_UMR = 0xc, 3590 }; 3591 3592 enum { 3593 MLX5_QPC_PM_STATE_ARMED = 0x0, 3594 MLX5_QPC_PM_STATE_REARM = 0x1, 3595 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3596 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3597 }; 3598 3599 enum { 3600 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3601 }; 3602 3603 enum { 3604 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3605 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3606 }; 3607 3608 enum { 3609 MLX5_QPC_MTU_256_BYTES = 0x1, 3610 MLX5_QPC_MTU_512_BYTES = 0x2, 3611 MLX5_QPC_MTU_1K_BYTES = 0x3, 3612 MLX5_QPC_MTU_2K_BYTES = 0x4, 3613 MLX5_QPC_MTU_4K_BYTES = 0x5, 3614 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3615 }; 3616 3617 enum { 3618 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3619 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3620 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3621 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3622 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3623 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3624 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3625 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3626 }; 3627 3628 enum { 3629 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3630 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3631 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3632 }; 3633 3634 enum { 3635 MLX5_QPC_CS_RES_DISABLE = 0x0, 3636 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3637 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3638 }; 3639 3640 enum { 3641 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3642 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3643 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3644 }; 3645 3646 struct mlx5_ifc_qpc_bits { 3647 u8 state[0x4]; 3648 u8 lag_tx_port_affinity[0x4]; 3649 u8 st[0x8]; 3650 u8 reserved_at_10[0x2]; 3651 u8 isolate_vl_tc[0x1]; 3652 u8 pm_state[0x2]; 3653 u8 reserved_at_15[0x1]; 3654 u8 req_e2e_credit_mode[0x2]; 3655 u8 offload_type[0x4]; 3656 u8 end_padding_mode[0x2]; 3657 u8 reserved_at_1e[0x2]; 3658 3659 u8 wq_signature[0x1]; 3660 u8 block_lb_mc[0x1]; 3661 u8 atomic_like_write_en[0x1]; 3662 u8 latency_sensitive[0x1]; 3663 u8 reserved_at_24[0x1]; 3664 u8 drain_sigerr[0x1]; 3665 u8 reserved_at_26[0x1]; 3666 u8 dp_ordering_force[0x1]; 3667 u8 pd[0x18]; 3668 3669 u8 mtu[0x3]; 3670 u8 log_msg_max[0x5]; 3671 u8 reserved_at_48[0x1]; 3672 u8 log_rq_size[0x4]; 3673 u8 log_rq_stride[0x3]; 3674 u8 no_sq[0x1]; 3675 u8 log_sq_size[0x4]; 3676 u8 reserved_at_55[0x1]; 3677 u8 retry_mode[0x2]; 3678 u8 ts_format[0x2]; 3679 u8 reserved_at_5a[0x1]; 3680 u8 rlky[0x1]; 3681 u8 ulp_stateless_offload_mode[0x4]; 3682 3683 u8 counter_set_id[0x8]; 3684 u8 uar_page[0x18]; 3685 3686 u8 reserved_at_80[0x8]; 3687 u8 user_index[0x18]; 3688 3689 u8 reserved_at_a0[0x3]; 3690 u8 log_page_size[0x5]; 3691 u8 remote_qpn[0x18]; 3692 3693 struct mlx5_ifc_ads_bits primary_address_path; 3694 3695 struct mlx5_ifc_ads_bits secondary_address_path; 3696 3697 u8 log_ack_req_freq[0x4]; 3698 u8 reserved_at_384[0x4]; 3699 u8 log_sra_max[0x3]; 3700 u8 reserved_at_38b[0x2]; 3701 u8 retry_count[0x3]; 3702 u8 rnr_retry[0x3]; 3703 u8 reserved_at_393[0x1]; 3704 u8 fre[0x1]; 3705 u8 cur_rnr_retry[0x3]; 3706 u8 cur_retry_count[0x3]; 3707 u8 reserved_at_39b[0x5]; 3708 3709 u8 reserved_at_3a0[0x20]; 3710 3711 u8 reserved_at_3c0[0x8]; 3712 u8 next_send_psn[0x18]; 3713 3714 u8 reserved_at_3e0[0x3]; 3715 u8 log_num_dci_stream_channels[0x5]; 3716 u8 cqn_snd[0x18]; 3717 3718 u8 reserved_at_400[0x3]; 3719 u8 log_num_dci_errored_streams[0x5]; 3720 u8 deth_sqpn[0x18]; 3721 3722 u8 reserved_at_420[0x20]; 3723 3724 u8 reserved_at_440[0x8]; 3725 u8 last_acked_psn[0x18]; 3726 3727 u8 reserved_at_460[0x8]; 3728 u8 ssn[0x18]; 3729 3730 u8 reserved_at_480[0x8]; 3731 u8 log_rra_max[0x3]; 3732 u8 reserved_at_48b[0x1]; 3733 u8 atomic_mode[0x4]; 3734 u8 rre[0x1]; 3735 u8 rwe[0x1]; 3736 u8 rae[0x1]; 3737 u8 reserved_at_493[0x1]; 3738 u8 page_offset[0x6]; 3739 u8 reserved_at_49a[0x2]; 3740 u8 dp_ordering_1[0x1]; 3741 u8 cd_slave_receive[0x1]; 3742 u8 cd_slave_send[0x1]; 3743 u8 cd_master[0x1]; 3744 3745 u8 reserved_at_4a0[0x3]; 3746 u8 min_rnr_nak[0x5]; 3747 u8 next_rcv_psn[0x18]; 3748 3749 u8 reserved_at_4c0[0x8]; 3750 u8 xrcd[0x18]; 3751 3752 u8 reserved_at_4e0[0x8]; 3753 u8 cqn_rcv[0x18]; 3754 3755 u8 dbr_addr[0x40]; 3756 3757 u8 q_key[0x20]; 3758 3759 u8 reserved_at_560[0x5]; 3760 u8 rq_type[0x3]; 3761 u8 srqn_rmpn_xrqn[0x18]; 3762 3763 u8 reserved_at_580[0x8]; 3764 u8 rmsn[0x18]; 3765 3766 u8 hw_sq_wqebb_counter[0x10]; 3767 u8 sw_sq_wqebb_counter[0x10]; 3768 3769 u8 hw_rq_counter[0x20]; 3770 3771 u8 sw_rq_counter[0x20]; 3772 3773 u8 reserved_at_600[0x20]; 3774 3775 u8 reserved_at_620[0xf]; 3776 u8 cgs[0x1]; 3777 u8 cs_req[0x8]; 3778 u8 cs_res[0x8]; 3779 3780 u8 dc_access_key[0x40]; 3781 3782 u8 reserved_at_680[0x3]; 3783 u8 dbr_umem_valid[0x1]; 3784 3785 u8 reserved_at_684[0xbc]; 3786 }; 3787 3788 struct mlx5_ifc_roce_addr_layout_bits { 3789 u8 source_l3_address[16][0x8]; 3790 3791 u8 reserved_at_80[0x3]; 3792 u8 vlan_valid[0x1]; 3793 u8 vlan_id[0xc]; 3794 u8 source_mac_47_32[0x10]; 3795 3796 u8 source_mac_31_0[0x20]; 3797 3798 u8 reserved_at_c0[0x14]; 3799 u8 roce_l3_type[0x4]; 3800 u8 roce_version[0x8]; 3801 3802 u8 reserved_at_e0[0x20]; 3803 }; 3804 3805 struct mlx5_ifc_crypto_cap_bits { 3806 u8 reserved_at_0[0x3]; 3807 u8 synchronize_dek[0x1]; 3808 u8 int_kek_manual[0x1]; 3809 u8 int_kek_auto[0x1]; 3810 u8 reserved_at_6[0x1a]; 3811 3812 u8 reserved_at_20[0x3]; 3813 u8 log_dek_max_alloc[0x5]; 3814 u8 reserved_at_28[0x3]; 3815 u8 log_max_num_deks[0x5]; 3816 u8 reserved_at_30[0x10]; 3817 3818 u8 reserved_at_40[0x20]; 3819 3820 u8 reserved_at_60[0x3]; 3821 u8 log_dek_granularity[0x5]; 3822 u8 reserved_at_68[0x3]; 3823 u8 log_max_num_int_kek[0x5]; 3824 u8 sw_wrapped_dek[0x10]; 3825 3826 u8 reserved_at_80[0x780]; 3827 }; 3828 3829 struct mlx5_ifc_shampo_cap_bits { 3830 u8 reserved_at_0[0x3]; 3831 u8 shampo_log_max_reservation_size[0x5]; 3832 u8 reserved_at_8[0x3]; 3833 u8 shampo_log_min_reservation_size[0x5]; 3834 u8 shampo_min_mss_size[0x10]; 3835 3836 u8 shampo_header_split[0x1]; 3837 u8 shampo_header_split_data_merge[0x1]; 3838 u8 reserved_at_22[0x1]; 3839 u8 shampo_log_max_headers_entry_size[0x5]; 3840 u8 reserved_at_28[0x18]; 3841 3842 u8 reserved_at_40[0x7c0]; 3843 }; 3844 3845 union mlx5_ifc_hca_cap_union_bits { 3846 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3847 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3848 struct mlx5_ifc_odp_cap_bits odp_cap; 3849 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3850 struct mlx5_ifc_roce_cap_bits roce_cap; 3851 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3852 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3853 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3854 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3855 struct mlx5_ifc_esw_cap_bits esw_cap; 3856 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3857 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3858 struct mlx5_ifc_qos_cap_bits qos_cap; 3859 struct mlx5_ifc_debug_cap_bits debug_cap; 3860 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3861 struct mlx5_ifc_tls_cap_bits tls_cap; 3862 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3863 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3864 struct mlx5_ifc_tlp_dev_emu_capabilities_bits tlp_dev_emu_capabilities; 3865 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3866 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3867 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3868 struct mlx5_ifc_psp_cap_bits psp_cap; 3869 u8 reserved_at_0[0x8000]; 3870 }; 3871 3872 enum { 3873 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3874 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3875 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3876 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3877 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3878 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3879 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3880 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3881 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3882 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3883 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3884 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3885 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3886 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3887 }; 3888 3889 enum { 3890 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3891 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3892 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3893 }; 3894 3895 enum { 3896 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3897 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3898 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3899 }; 3900 3901 struct mlx5_ifc_vlan_bits { 3902 u8 ethtype[0x10]; 3903 u8 prio[0x3]; 3904 u8 cfi[0x1]; 3905 u8 vid[0xc]; 3906 }; 3907 3908 enum { 3909 MLX5_FLOW_METER_COLOR_RED = 0x0, 3910 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3911 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3912 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3913 }; 3914 3915 enum { 3916 MLX5_EXE_ASO_FLOW_METER = 0x2, 3917 }; 3918 3919 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3920 u8 return_reg_id[0x4]; 3921 u8 aso_type[0x4]; 3922 u8 reserved_at_8[0x14]; 3923 u8 action[0x1]; 3924 u8 init_color[0x2]; 3925 u8 meter_id[0x1]; 3926 }; 3927 3928 union mlx5_ifc_exe_aso_ctrl { 3929 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3930 }; 3931 3932 struct mlx5_ifc_execute_aso_bits { 3933 u8 valid[0x1]; 3934 u8 reserved_at_1[0x7]; 3935 u8 aso_object_id[0x18]; 3936 3937 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3938 }; 3939 3940 struct mlx5_ifc_flow_context_bits { 3941 struct mlx5_ifc_vlan_bits push_vlan; 3942 3943 u8 group_id[0x20]; 3944 3945 u8 reserved_at_40[0x8]; 3946 u8 flow_tag[0x18]; 3947 3948 u8 reserved_at_60[0x10]; 3949 u8 action[0x10]; 3950 3951 u8 extended_destination[0x1]; 3952 u8 uplink_hairpin_en[0x1]; 3953 u8 flow_source[0x2]; 3954 u8 encrypt_decrypt_type[0x4]; 3955 u8 destination_list_size[0x18]; 3956 3957 u8 reserved_at_a0[0x8]; 3958 u8 flow_counter_list_size[0x18]; 3959 3960 u8 packet_reformat_id[0x20]; 3961 3962 u8 modify_header_id[0x20]; 3963 3964 struct mlx5_ifc_vlan_bits push_vlan_2; 3965 3966 u8 encrypt_decrypt_obj_id[0x20]; 3967 u8 reserved_at_140[0xc0]; 3968 3969 struct mlx5_ifc_fte_match_param_bits match_value; 3970 3971 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3972 3973 u8 reserved_at_1300[0x500]; 3974 3975 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3976 }; 3977 3978 enum { 3979 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3980 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3981 }; 3982 3983 struct mlx5_ifc_xrc_srqc_bits { 3984 u8 state[0x4]; 3985 u8 log_xrc_srq_size[0x4]; 3986 u8 reserved_at_8[0x18]; 3987 3988 u8 wq_signature[0x1]; 3989 u8 cont_srq[0x1]; 3990 u8 reserved_at_22[0x1]; 3991 u8 rlky[0x1]; 3992 u8 basic_cyclic_rcv_wqe[0x1]; 3993 u8 log_rq_stride[0x3]; 3994 u8 xrcd[0x18]; 3995 3996 u8 page_offset[0x6]; 3997 u8 reserved_at_46[0x1]; 3998 u8 dbr_umem_valid[0x1]; 3999 u8 cqn[0x18]; 4000 4001 u8 reserved_at_60[0x20]; 4002 4003 u8 user_index_equal_xrc_srqn[0x1]; 4004 u8 reserved_at_81[0x1]; 4005 u8 log_page_size[0x6]; 4006 u8 user_index[0x18]; 4007 4008 u8 reserved_at_a0[0x20]; 4009 4010 u8 reserved_at_c0[0x8]; 4011 u8 pd[0x18]; 4012 4013 u8 lwm[0x10]; 4014 u8 wqe_cnt[0x10]; 4015 4016 u8 reserved_at_100[0x40]; 4017 4018 u8 db_record_addr_h[0x20]; 4019 4020 u8 db_record_addr_l[0x1e]; 4021 u8 reserved_at_17e[0x2]; 4022 4023 u8 reserved_at_180[0x80]; 4024 }; 4025 4026 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 4027 u8 counter_error_queues[0x20]; 4028 4029 u8 total_error_queues[0x20]; 4030 4031 u8 send_queue_priority_update_flow[0x20]; 4032 4033 u8 reserved_at_60[0x20]; 4034 4035 u8 nic_receive_steering_discard[0x40]; 4036 4037 u8 receive_discard_vport_down[0x40]; 4038 4039 u8 transmit_discard_vport_down[0x40]; 4040 4041 u8 async_eq_overrun[0x20]; 4042 4043 u8 comp_eq_overrun[0x20]; 4044 4045 u8 reserved_at_180[0x20]; 4046 4047 u8 invalid_command[0x20]; 4048 4049 u8 quota_exceeded_command[0x20]; 4050 4051 u8 internal_rq_out_of_buffer[0x20]; 4052 4053 u8 cq_overrun[0x20]; 4054 4055 u8 eth_wqe_too_small[0x20]; 4056 4057 u8 reserved_at_220[0xc0]; 4058 4059 u8 generated_pkt_steering_fail[0x40]; 4060 4061 u8 handled_pkt_steering_fail[0x40]; 4062 4063 u8 bar_uar_access[0x20]; 4064 4065 u8 odp_local_triggered_page_fault[0x20]; 4066 4067 u8 odp_remote_triggered_page_fault[0x20]; 4068 4069 u8 reserved_at_3c0[0xc20]; 4070 }; 4071 4072 struct mlx5_ifc_traffic_counter_bits { 4073 u8 packets[0x40]; 4074 4075 u8 octets[0x40]; 4076 }; 4077 4078 struct mlx5_ifc_tisc_bits { 4079 u8 strict_lag_tx_port_affinity[0x1]; 4080 u8 tls_en[0x1]; 4081 u8 reserved_at_2[0x2]; 4082 u8 lag_tx_port_affinity[0x04]; 4083 4084 u8 reserved_at_8[0x4]; 4085 u8 prio[0x4]; 4086 u8 reserved_at_10[0x10]; 4087 4088 u8 reserved_at_20[0x100]; 4089 4090 u8 reserved_at_120[0x8]; 4091 u8 transport_domain[0x18]; 4092 4093 u8 reserved_at_140[0x8]; 4094 u8 underlay_qpn[0x18]; 4095 4096 u8 reserved_at_160[0x8]; 4097 u8 pd[0x18]; 4098 4099 u8 reserved_at_180[0x380]; 4100 }; 4101 4102 enum { 4103 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4104 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4105 }; 4106 4107 enum { 4108 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4109 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4110 }; 4111 4112 enum { 4113 MLX5_RX_HASH_FN_NONE = 0x0, 4114 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4115 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4116 }; 4117 4118 enum { 4119 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4120 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4121 }; 4122 4123 struct mlx5_ifc_tirc_bits { 4124 u8 reserved_at_0[0x20]; 4125 4126 u8 disp_type[0x4]; 4127 u8 tls_en[0x1]; 4128 u8 reserved_at_25[0x1b]; 4129 4130 u8 reserved_at_40[0x40]; 4131 4132 u8 reserved_at_80[0x4]; 4133 u8 lro_timeout_period_usecs[0x10]; 4134 u8 packet_merge_mask[0x4]; 4135 u8 lro_max_ip_payload_size[0x8]; 4136 4137 u8 reserved_at_a0[0x40]; 4138 4139 u8 reserved_at_e0[0x8]; 4140 u8 inline_rqn[0x18]; 4141 4142 u8 rx_hash_symmetric[0x1]; 4143 u8 reserved_at_101[0x1]; 4144 u8 tunneled_offload_en[0x1]; 4145 u8 reserved_at_103[0x5]; 4146 u8 indirect_table[0x18]; 4147 4148 u8 rx_hash_fn[0x4]; 4149 u8 reserved_at_124[0x2]; 4150 u8 self_lb_block[0x2]; 4151 u8 transport_domain[0x18]; 4152 4153 u8 rx_hash_toeplitz_key[10][0x20]; 4154 4155 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4156 4157 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4158 4159 u8 reserved_at_2c0[0x4c0]; 4160 }; 4161 4162 enum { 4163 MLX5_SRQC_STATE_GOOD = 0x0, 4164 MLX5_SRQC_STATE_ERROR = 0x1, 4165 }; 4166 4167 struct mlx5_ifc_srqc_bits { 4168 u8 state[0x4]; 4169 u8 log_srq_size[0x4]; 4170 u8 reserved_at_8[0x18]; 4171 4172 u8 wq_signature[0x1]; 4173 u8 cont_srq[0x1]; 4174 u8 reserved_at_22[0x1]; 4175 u8 rlky[0x1]; 4176 u8 reserved_at_24[0x1]; 4177 u8 log_rq_stride[0x3]; 4178 u8 xrcd[0x18]; 4179 4180 u8 page_offset[0x6]; 4181 u8 reserved_at_46[0x2]; 4182 u8 cqn[0x18]; 4183 4184 u8 reserved_at_60[0x20]; 4185 4186 u8 reserved_at_80[0x2]; 4187 u8 log_page_size[0x6]; 4188 u8 reserved_at_88[0x18]; 4189 4190 u8 reserved_at_a0[0x20]; 4191 4192 u8 reserved_at_c0[0x8]; 4193 u8 pd[0x18]; 4194 4195 u8 lwm[0x10]; 4196 u8 wqe_cnt[0x10]; 4197 4198 u8 reserved_at_100[0x40]; 4199 4200 u8 dbr_addr[0x40]; 4201 4202 u8 reserved_at_180[0x80]; 4203 }; 4204 4205 enum { 4206 MLX5_SQC_STATE_RST = 0x0, 4207 MLX5_SQC_STATE_RDY = 0x1, 4208 MLX5_SQC_STATE_ERR = 0x3, 4209 }; 4210 4211 struct mlx5_ifc_sqc_bits { 4212 u8 rlky[0x1]; 4213 u8 cd_master[0x1]; 4214 u8 fre[0x1]; 4215 u8 flush_in_error_en[0x1]; 4216 u8 allow_multi_pkt_send_wqe[0x1]; 4217 u8 min_wqe_inline_mode[0x3]; 4218 u8 state[0x4]; 4219 u8 reg_umr[0x1]; 4220 u8 allow_swp[0x1]; 4221 u8 hairpin[0x1]; 4222 u8 non_wire[0x1]; 4223 u8 reserved_at_10[0xa]; 4224 u8 ts_format[0x2]; 4225 u8 reserved_at_1c[0x4]; 4226 4227 u8 reserved_at_20[0x8]; 4228 u8 user_index[0x18]; 4229 4230 u8 reserved_at_40[0x8]; 4231 u8 cqn[0x18]; 4232 4233 u8 reserved_at_60[0x8]; 4234 u8 hairpin_peer_rq[0x18]; 4235 4236 u8 reserved_at_80[0x10]; 4237 u8 hairpin_peer_vhca[0x10]; 4238 4239 u8 reserved_at_a0[0x20]; 4240 4241 u8 reserved_at_c0[0x8]; 4242 u8 ts_cqe_to_dest_cqn[0x18]; 4243 4244 u8 reserved_at_e0[0x10]; 4245 u8 packet_pacing_rate_limit_index[0x10]; 4246 u8 tis_lst_sz[0x10]; 4247 u8 qos_queue_group_id[0x10]; 4248 4249 u8 reserved_at_120[0x40]; 4250 4251 u8 reserved_at_160[0x8]; 4252 u8 tis_num_0[0x18]; 4253 4254 struct mlx5_ifc_wq_bits wq; 4255 }; 4256 4257 enum { 4258 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4259 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4260 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4261 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4262 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4263 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4264 }; 4265 4266 enum { 4267 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4268 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4269 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4270 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4271 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4272 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4273 }; 4274 4275 enum { 4276 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4277 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4278 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4279 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4280 }; 4281 4282 enum { 4283 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4284 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4285 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4286 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4287 }; 4288 4289 struct mlx5_ifc_tsar_element_bits { 4290 u8 traffic_class[0x4]; 4291 u8 reserved_at_4[0x4]; 4292 u8 tsar_type[0x8]; 4293 u8 reserved_at_10[0x10]; 4294 }; 4295 4296 struct mlx5_ifc_vport_element_bits { 4297 u8 reserved_at_0[0x4]; 4298 u8 eswitch_owner_vhca_id_valid[0x1]; 4299 u8 eswitch_owner_vhca_id[0xb]; 4300 u8 vport_number[0x10]; 4301 }; 4302 4303 struct mlx5_ifc_vport_tc_element_bits { 4304 u8 traffic_class[0x4]; 4305 u8 eswitch_owner_vhca_id_valid[0x1]; 4306 u8 eswitch_owner_vhca_id[0xb]; 4307 u8 vport_number[0x10]; 4308 }; 4309 4310 union mlx5_ifc_element_attributes_bits { 4311 struct mlx5_ifc_tsar_element_bits tsar; 4312 struct mlx5_ifc_vport_element_bits vport; 4313 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4314 u8 reserved_at_0[0x20]; 4315 }; 4316 4317 struct mlx5_ifc_scheduling_context_bits { 4318 u8 element_type[0x8]; 4319 u8 reserved_at_8[0x18]; 4320 4321 union mlx5_ifc_element_attributes_bits element_attributes; 4322 4323 u8 parent_element_id[0x20]; 4324 4325 u8 reserved_at_60[0x40]; 4326 4327 u8 bw_share[0x20]; 4328 4329 u8 max_average_bw[0x20]; 4330 4331 u8 max_bw_obj_id[0x20]; 4332 4333 u8 reserved_at_100[0x100]; 4334 }; 4335 4336 struct mlx5_ifc_rqtc_bits { 4337 u8 reserved_at_0[0xa0]; 4338 4339 u8 reserved_at_a0[0x5]; 4340 u8 list_q_type[0x3]; 4341 u8 reserved_at_a8[0x8]; 4342 u8 rqt_max_size[0x10]; 4343 4344 u8 rq_vhca_id_format[0x1]; 4345 u8 reserved_at_c1[0xf]; 4346 u8 rqt_actual_size[0x10]; 4347 4348 u8 reserved_at_e0[0x6a0]; 4349 4350 union { 4351 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4352 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4353 }; 4354 }; 4355 4356 enum { 4357 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4358 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4359 }; 4360 4361 enum { 4362 MLX5_RQC_STATE_RST = 0x0, 4363 MLX5_RQC_STATE_RDY = 0x1, 4364 MLX5_RQC_STATE_ERR = 0x3, 4365 }; 4366 4367 enum { 4368 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4369 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4370 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4371 }; 4372 4373 enum { 4374 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4375 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4376 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4377 }; 4378 4379 struct mlx5_ifc_rqc_bits { 4380 u8 rlky[0x1]; 4381 u8 delay_drop_en[0x1]; 4382 u8 scatter_fcs[0x1]; 4383 u8 vsd[0x1]; 4384 u8 mem_rq_type[0x4]; 4385 u8 state[0x4]; 4386 u8 reserved_at_c[0x1]; 4387 u8 flush_in_error_en[0x1]; 4388 u8 hairpin[0x1]; 4389 u8 reserved_at_f[0xb]; 4390 u8 ts_format[0x2]; 4391 u8 reserved_at_1c[0x4]; 4392 4393 u8 reserved_at_20[0x8]; 4394 u8 user_index[0x18]; 4395 4396 u8 reserved_at_40[0x8]; 4397 u8 cqn[0x18]; 4398 4399 u8 counter_set_id[0x8]; 4400 u8 reserved_at_68[0x18]; 4401 4402 u8 reserved_at_80[0x8]; 4403 u8 rmpn[0x18]; 4404 4405 u8 reserved_at_a0[0x8]; 4406 u8 hairpin_peer_sq[0x18]; 4407 4408 u8 reserved_at_c0[0x10]; 4409 u8 hairpin_peer_vhca[0x10]; 4410 4411 u8 reserved_at_e0[0x46]; 4412 u8 shampo_no_match_alignment_granularity[0x2]; 4413 u8 reserved_at_128[0x6]; 4414 u8 shampo_match_criteria_type[0x2]; 4415 u8 reservation_timeout[0x10]; 4416 4417 u8 reserved_at_140[0x40]; 4418 4419 struct mlx5_ifc_wq_bits wq; 4420 }; 4421 4422 enum { 4423 MLX5_RMPC_STATE_RDY = 0x1, 4424 MLX5_RMPC_STATE_ERR = 0x3, 4425 }; 4426 4427 struct mlx5_ifc_rmpc_bits { 4428 u8 reserved_at_0[0x8]; 4429 u8 state[0x4]; 4430 u8 reserved_at_c[0x14]; 4431 4432 u8 basic_cyclic_rcv_wqe[0x1]; 4433 u8 reserved_at_21[0x1f]; 4434 4435 u8 reserved_at_40[0x140]; 4436 4437 struct mlx5_ifc_wq_bits wq; 4438 }; 4439 4440 enum { 4441 VHCA_ID_TYPE_HW = 0, 4442 VHCA_ID_TYPE_SW = 1, 4443 }; 4444 4445 struct mlx5_ifc_nic_vport_context_bits { 4446 u8 reserved_at_0[0x5]; 4447 u8 min_wqe_inline_mode[0x3]; 4448 u8 reserved_at_8[0x15]; 4449 u8 disable_mc_local_lb[0x1]; 4450 u8 disable_uc_local_lb[0x1]; 4451 u8 roce_en[0x1]; 4452 4453 u8 arm_change_event[0x1]; 4454 u8 reserved_at_21[0x1a]; 4455 u8 event_on_mtu[0x1]; 4456 u8 event_on_promisc_change[0x1]; 4457 u8 event_on_vlan_change[0x1]; 4458 u8 event_on_mc_address_change[0x1]; 4459 u8 event_on_uc_address_change[0x1]; 4460 4461 u8 vhca_id_type[0x1]; 4462 u8 reserved_at_41[0xb]; 4463 u8 affiliation_criteria[0x4]; 4464 u8 affiliated_vhca_id[0x10]; 4465 4466 u8 reserved_at_60[0xa0]; 4467 4468 u8 reserved_at_100[0x1]; 4469 u8 sd_group[0x3]; 4470 u8 reserved_at_104[0x1c]; 4471 4472 u8 reserved_at_120[0x10]; 4473 u8 mtu[0x10]; 4474 4475 u8 system_image_guid[0x40]; 4476 u8 port_guid[0x40]; 4477 u8 node_guid[0x40]; 4478 4479 u8 reserved_at_200[0x140]; 4480 u8 qkey_violation_counter[0x10]; 4481 u8 reserved_at_350[0x430]; 4482 4483 u8 promisc_uc[0x1]; 4484 u8 promisc_mc[0x1]; 4485 u8 promisc_all[0x1]; 4486 u8 reserved_at_783[0x2]; 4487 u8 allowed_list_type[0x3]; 4488 u8 reserved_at_788[0xc]; 4489 u8 allowed_list_size[0xc]; 4490 4491 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4492 4493 u8 reserved_at_7e0[0x20]; 4494 4495 u8 current_uc_mac_address[][0x40]; 4496 }; 4497 4498 enum { 4499 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4500 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4501 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4502 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4503 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4504 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4505 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4506 }; 4507 4508 enum { 4509 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4510 }; 4511 4512 struct mlx5_ifc_mkc_bits { 4513 u8 reserved_at_0[0x1]; 4514 u8 free[0x1]; 4515 u8 reserved_at_2[0x1]; 4516 u8 access_mode_4_2[0x3]; 4517 u8 reserved_at_6[0x7]; 4518 u8 relaxed_ordering_write[0x1]; 4519 u8 reserved_at_e[0x1]; 4520 u8 small_fence_on_rdma_read_response[0x1]; 4521 u8 umr_en[0x1]; 4522 u8 a[0x1]; 4523 u8 rw[0x1]; 4524 u8 rr[0x1]; 4525 u8 lw[0x1]; 4526 u8 lr[0x1]; 4527 u8 access_mode_1_0[0x2]; 4528 u8 reserved_at_18[0x2]; 4529 u8 ma_translation_mode[0x2]; 4530 u8 reserved_at_1c[0x4]; 4531 4532 u8 qpn[0x18]; 4533 u8 mkey_7_0[0x8]; 4534 4535 u8 reserved_at_40[0x20]; 4536 4537 u8 length64[0x1]; 4538 u8 bsf_en[0x1]; 4539 u8 sync_umr[0x1]; 4540 u8 reserved_at_63[0x2]; 4541 u8 expected_sigerr_count[0x1]; 4542 u8 reserved_at_66[0x1]; 4543 u8 en_rinval[0x1]; 4544 u8 pd[0x18]; 4545 4546 u8 start_addr[0x40]; 4547 4548 u8 len[0x40]; 4549 4550 u8 bsf_octword_size[0x20]; 4551 4552 u8 reserved_at_120[0x60]; 4553 4554 u8 crossing_target_vhca_id[0x10]; 4555 u8 reserved_at_190[0x10]; 4556 4557 u8 translations_octword_size[0x20]; 4558 4559 u8 reserved_at_1c0[0x19]; 4560 u8 relaxed_ordering_read[0x1]; 4561 u8 log_page_size[0x6]; 4562 4563 u8 reserved_at_1e0[0x5]; 4564 u8 pcie_tph_en[0x1]; 4565 u8 pcie_tph_ph[0x2]; 4566 u8 pcie_tph_steering_tag_index[0x8]; 4567 u8 reserved_at_1f0[0x10]; 4568 }; 4569 4570 struct mlx5_ifc_pkey_bits { 4571 u8 reserved_at_0[0x10]; 4572 u8 pkey[0x10]; 4573 }; 4574 4575 struct mlx5_ifc_array128_auto_bits { 4576 u8 array128_auto[16][0x8]; 4577 }; 4578 4579 struct mlx5_ifc_hca_vport_context_bits { 4580 u8 field_select[0x20]; 4581 4582 u8 reserved_at_20[0xe0]; 4583 4584 u8 sm_virt_aware[0x1]; 4585 u8 has_smi[0x1]; 4586 u8 has_raw[0x1]; 4587 u8 grh_required[0x1]; 4588 u8 reserved_at_104[0x4]; 4589 u8 num_port_plane[0x8]; 4590 u8 port_physical_state[0x4]; 4591 u8 vport_state_policy[0x4]; 4592 u8 port_state[0x4]; 4593 u8 vport_state[0x4]; 4594 4595 u8 reserved_at_120[0x20]; 4596 4597 u8 system_image_guid[0x40]; 4598 4599 u8 port_guid[0x40]; 4600 4601 u8 node_guid[0x40]; 4602 4603 u8 cap_mask1[0x20]; 4604 4605 u8 cap_mask1_field_select[0x20]; 4606 4607 u8 cap_mask2[0x20]; 4608 4609 u8 cap_mask2_field_select[0x20]; 4610 4611 u8 reserved_at_280[0x80]; 4612 4613 u8 lid[0x10]; 4614 u8 reserved_at_310[0x4]; 4615 u8 init_type_reply[0x4]; 4616 u8 lmc[0x3]; 4617 u8 subnet_timeout[0x5]; 4618 4619 u8 sm_lid[0x10]; 4620 u8 sm_sl[0x4]; 4621 u8 reserved_at_334[0xc]; 4622 4623 u8 qkey_violation_counter[0x10]; 4624 u8 pkey_violation_counter[0x10]; 4625 4626 u8 reserved_at_360[0xca0]; 4627 }; 4628 4629 struct mlx5_ifc_esw_vport_context_bits { 4630 u8 fdb_to_vport_reg_c[0x1]; 4631 u8 reserved_at_1[0x2]; 4632 u8 vport_svlan_strip[0x1]; 4633 u8 vport_cvlan_strip[0x1]; 4634 u8 vport_svlan_insert[0x1]; 4635 u8 vport_cvlan_insert[0x2]; 4636 u8 fdb_to_vport_reg_c_id[0x8]; 4637 u8 reserved_at_10[0x10]; 4638 4639 u8 reserved_at_20[0x20]; 4640 4641 u8 svlan_cfi[0x1]; 4642 u8 svlan_pcp[0x3]; 4643 u8 svlan_id[0xc]; 4644 u8 cvlan_cfi[0x1]; 4645 u8 cvlan_pcp[0x3]; 4646 u8 cvlan_id[0xc]; 4647 4648 u8 reserved_at_60[0x720]; 4649 4650 u8 sw_steering_vport_icm_address_rx[0x40]; 4651 4652 u8 sw_steering_vport_icm_address_tx[0x40]; 4653 }; 4654 4655 enum { 4656 MLX5_EQC_STATUS_OK = 0x0, 4657 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4658 }; 4659 4660 enum { 4661 MLX5_EQC_ST_ARMED = 0x9, 4662 MLX5_EQC_ST_FIRED = 0xa, 4663 }; 4664 4665 struct mlx5_ifc_eqc_bits { 4666 u8 status[0x4]; 4667 u8 reserved_at_4[0x9]; 4668 u8 ec[0x1]; 4669 u8 oi[0x1]; 4670 u8 reserved_at_f[0x5]; 4671 u8 st[0x4]; 4672 u8 reserved_at_18[0x8]; 4673 4674 u8 reserved_at_20[0x20]; 4675 4676 u8 reserved_at_40[0x14]; 4677 u8 page_offset[0x6]; 4678 u8 reserved_at_5a[0x6]; 4679 4680 u8 reserved_at_60[0x3]; 4681 u8 log_eq_size[0x5]; 4682 u8 uar_page[0x18]; 4683 4684 u8 reserved_at_80[0x20]; 4685 4686 u8 reserved_at_a0[0x14]; 4687 u8 intr[0xc]; 4688 4689 u8 reserved_at_c0[0x3]; 4690 u8 log_page_size[0x5]; 4691 u8 reserved_at_c8[0x18]; 4692 4693 u8 reserved_at_e0[0x60]; 4694 4695 u8 reserved_at_140[0x8]; 4696 u8 consumer_counter[0x18]; 4697 4698 u8 reserved_at_160[0x8]; 4699 u8 producer_counter[0x18]; 4700 4701 u8 reserved_at_180[0x80]; 4702 }; 4703 4704 enum { 4705 MLX5_DCTC_STATE_ACTIVE = 0x0, 4706 MLX5_DCTC_STATE_DRAINING = 0x1, 4707 MLX5_DCTC_STATE_DRAINED = 0x2, 4708 }; 4709 4710 enum { 4711 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4712 MLX5_DCTC_CS_RES_NA = 0x1, 4713 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4714 }; 4715 4716 enum { 4717 MLX5_DCTC_MTU_256_BYTES = 0x1, 4718 MLX5_DCTC_MTU_512_BYTES = 0x2, 4719 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4720 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4721 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4722 }; 4723 4724 struct mlx5_ifc_dctc_bits { 4725 u8 reserved_at_0[0x4]; 4726 u8 state[0x4]; 4727 u8 reserved_at_8[0x18]; 4728 4729 u8 reserved_at_20[0x7]; 4730 u8 dp_ordering_force[0x1]; 4731 u8 user_index[0x18]; 4732 4733 u8 reserved_at_40[0x8]; 4734 u8 cqn[0x18]; 4735 4736 u8 counter_set_id[0x8]; 4737 u8 atomic_mode[0x4]; 4738 u8 rre[0x1]; 4739 u8 rwe[0x1]; 4740 u8 rae[0x1]; 4741 u8 atomic_like_write_en[0x1]; 4742 u8 latency_sensitive[0x1]; 4743 u8 rlky[0x1]; 4744 u8 free_ar[0x1]; 4745 u8 reserved_at_73[0x1]; 4746 u8 dp_ordering_1[0x1]; 4747 u8 reserved_at_75[0xb]; 4748 4749 u8 reserved_at_80[0x8]; 4750 u8 cs_res[0x8]; 4751 u8 reserved_at_90[0x3]; 4752 u8 min_rnr_nak[0x5]; 4753 u8 reserved_at_98[0x8]; 4754 4755 u8 reserved_at_a0[0x8]; 4756 u8 srqn_xrqn[0x18]; 4757 4758 u8 reserved_at_c0[0x8]; 4759 u8 pd[0x18]; 4760 4761 u8 tclass[0x8]; 4762 u8 reserved_at_e8[0x4]; 4763 u8 flow_label[0x14]; 4764 4765 u8 dc_access_key[0x40]; 4766 4767 u8 reserved_at_140[0x5]; 4768 u8 mtu[0x3]; 4769 u8 port[0x8]; 4770 u8 pkey_index[0x10]; 4771 4772 u8 reserved_at_160[0x8]; 4773 u8 my_addr_index[0x8]; 4774 u8 reserved_at_170[0x8]; 4775 u8 hop_limit[0x8]; 4776 4777 u8 dc_access_key_violation_count[0x20]; 4778 4779 u8 reserved_at_1a0[0x14]; 4780 u8 dei_cfi[0x1]; 4781 u8 eth_prio[0x3]; 4782 u8 ecn[0x2]; 4783 u8 dscp[0x6]; 4784 4785 u8 reserved_at_1c0[0x20]; 4786 u8 ece[0x20]; 4787 }; 4788 4789 enum { 4790 MLX5_CQC_STATUS_OK = 0x0, 4791 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4792 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4793 }; 4794 4795 enum { 4796 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4797 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4798 }; 4799 4800 enum { 4801 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4802 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4803 MLX5_CQC_ST_FIRED = 0xa, 4804 }; 4805 4806 enum mlx5_cq_period_mode { 4807 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4808 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4809 MLX5_CQ_PERIOD_NUM_MODES, 4810 }; 4811 4812 struct mlx5_ifc_cqc_bits { 4813 u8 status[0x4]; 4814 u8 reserved_at_4[0x2]; 4815 u8 dbr_umem_valid[0x1]; 4816 u8 apu_cq[0x1]; 4817 u8 cqe_sz[0x3]; 4818 u8 cc[0x1]; 4819 u8 reserved_at_c[0x1]; 4820 u8 scqe_break_moderation_en[0x1]; 4821 u8 oi[0x1]; 4822 u8 cq_period_mode[0x2]; 4823 u8 cqe_comp_en[0x1]; 4824 u8 mini_cqe_res_format[0x2]; 4825 u8 st[0x4]; 4826 u8 reserved_at_18[0x6]; 4827 u8 cqe_compression_layout[0x2]; 4828 4829 u8 reserved_at_20[0x20]; 4830 4831 u8 reserved_at_40[0x14]; 4832 u8 page_offset[0x6]; 4833 u8 reserved_at_5a[0x6]; 4834 4835 u8 reserved_at_60[0x3]; 4836 u8 log_cq_size[0x5]; 4837 u8 uar_page[0x18]; 4838 4839 u8 reserved_at_80[0x4]; 4840 u8 cq_period[0xc]; 4841 u8 cq_max_count[0x10]; 4842 4843 u8 c_eqn_or_apu_element[0x20]; 4844 4845 u8 reserved_at_c0[0x3]; 4846 u8 log_page_size[0x5]; 4847 u8 reserved_at_c8[0x18]; 4848 4849 u8 reserved_at_e0[0x20]; 4850 4851 u8 reserved_at_100[0x8]; 4852 u8 last_notified_index[0x18]; 4853 4854 u8 reserved_at_120[0x8]; 4855 u8 last_solicit_index[0x18]; 4856 4857 u8 reserved_at_140[0x8]; 4858 u8 consumer_counter[0x18]; 4859 4860 u8 reserved_at_160[0x8]; 4861 u8 producer_counter[0x18]; 4862 4863 u8 reserved_at_180[0x40]; 4864 4865 u8 dbr_addr[0x40]; 4866 }; 4867 4868 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4869 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4870 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4871 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4872 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4873 u8 reserved_at_0[0x800]; 4874 }; 4875 4876 struct mlx5_ifc_query_adapter_param_block_bits { 4877 u8 reserved_at_0[0xc0]; 4878 4879 u8 reserved_at_c0[0x8]; 4880 u8 ieee_vendor_id[0x18]; 4881 4882 u8 reserved_at_e0[0x10]; 4883 u8 vsd_vendor_id[0x10]; 4884 4885 u8 vsd[208][0x8]; 4886 4887 u8 vsd_contd_psid[16][0x8]; 4888 }; 4889 4890 enum { 4891 MLX5_XRQC_STATE_GOOD = 0x0, 4892 MLX5_XRQC_STATE_ERROR = 0x1, 4893 }; 4894 4895 enum { 4896 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4897 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4898 }; 4899 4900 enum { 4901 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4902 }; 4903 4904 struct mlx5_ifc_tag_matching_topology_context_bits { 4905 u8 log_matching_list_sz[0x4]; 4906 u8 reserved_at_4[0xc]; 4907 u8 append_next_index[0x10]; 4908 4909 u8 sw_phase_cnt[0x10]; 4910 u8 hw_phase_cnt[0x10]; 4911 4912 u8 reserved_at_40[0x40]; 4913 }; 4914 4915 struct mlx5_ifc_xrqc_bits { 4916 u8 state[0x4]; 4917 u8 rlkey[0x1]; 4918 u8 reserved_at_5[0xf]; 4919 u8 topology[0x4]; 4920 u8 reserved_at_18[0x4]; 4921 u8 offload[0x4]; 4922 4923 u8 reserved_at_20[0x8]; 4924 u8 user_index[0x18]; 4925 4926 u8 reserved_at_40[0x8]; 4927 u8 cqn[0x18]; 4928 4929 u8 reserved_at_60[0xa0]; 4930 4931 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4932 4933 u8 reserved_at_180[0x280]; 4934 4935 struct mlx5_ifc_wq_bits wq; 4936 }; 4937 4938 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4939 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4940 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4941 u8 reserved_at_0[0x20]; 4942 }; 4943 4944 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4945 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4946 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4947 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4948 u8 reserved_at_0[0x20]; 4949 }; 4950 4951 struct mlx5_ifc_rs_histogram_cntrs_bits { 4952 u8 hist[16][0x40]; 4953 u8 reserved_at_400[0x2c0]; 4954 }; 4955 4956 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4957 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4958 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4959 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4960 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4961 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4962 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4963 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4964 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4965 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4966 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4967 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4968 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4969 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4970 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4971 u8 reserved_at_0[0x7c0]; 4972 }; 4973 4974 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4975 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4976 u8 reserved_at_0[0x7c0]; 4977 }; 4978 4979 union mlx5_ifc_event_auto_bits { 4980 struct mlx5_ifc_comp_event_bits comp_event; 4981 struct mlx5_ifc_dct_events_bits dct_events; 4982 struct mlx5_ifc_qp_events_bits qp_events; 4983 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4984 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4985 struct mlx5_ifc_cq_error_bits cq_error; 4986 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4987 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4988 struct mlx5_ifc_gpio_event_bits gpio_event; 4989 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4990 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4991 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4992 u8 reserved_at_0[0xe0]; 4993 }; 4994 4995 struct mlx5_ifc_health_buffer_bits { 4996 u8 reserved_at_0[0x100]; 4997 4998 u8 assert_existptr[0x20]; 4999 5000 u8 assert_callra[0x20]; 5001 5002 u8 reserved_at_140[0x20]; 5003 5004 u8 time[0x20]; 5005 5006 u8 fw_version[0x20]; 5007 5008 u8 hw_id[0x20]; 5009 5010 u8 rfr[0x1]; 5011 u8 reserved_at_1c1[0x3]; 5012 u8 valid[0x1]; 5013 u8 severity[0x3]; 5014 u8 reserved_at_1c8[0x18]; 5015 5016 u8 irisc_index[0x8]; 5017 u8 synd[0x8]; 5018 u8 ext_synd[0x10]; 5019 }; 5020 5021 struct mlx5_ifc_register_loopback_control_bits { 5022 u8 no_lb[0x1]; 5023 u8 reserved_at_1[0x7]; 5024 u8 port[0x8]; 5025 u8 reserved_at_10[0x10]; 5026 5027 u8 reserved_at_20[0x60]; 5028 }; 5029 5030 enum { 5031 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 5032 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 5033 }; 5034 5035 struct mlx5_ifc_teardown_hca_out_bits { 5036 u8 status[0x8]; 5037 u8 reserved_at_8[0x18]; 5038 5039 u8 syndrome[0x20]; 5040 5041 u8 reserved_at_40[0x3f]; 5042 5043 u8 state[0x1]; 5044 }; 5045 5046 enum { 5047 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5048 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5049 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5050 }; 5051 5052 struct mlx5_ifc_teardown_hca_in_bits { 5053 u8 opcode[0x10]; 5054 u8 reserved_at_10[0x10]; 5055 5056 u8 reserved_at_20[0x10]; 5057 u8 op_mod[0x10]; 5058 5059 u8 reserved_at_40[0x10]; 5060 u8 profile[0x10]; 5061 5062 u8 reserved_at_60[0x20]; 5063 }; 5064 5065 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5066 u8 status[0x8]; 5067 u8 reserved_at_8[0x18]; 5068 5069 u8 syndrome[0x20]; 5070 5071 u8 reserved_at_40[0x40]; 5072 }; 5073 5074 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5075 u8 opcode[0x10]; 5076 u8 uid[0x10]; 5077 5078 u8 reserved_at_20[0x10]; 5079 u8 op_mod[0x10]; 5080 5081 u8 reserved_at_40[0x8]; 5082 u8 qpn[0x18]; 5083 5084 u8 reserved_at_60[0x20]; 5085 5086 u8 opt_param_mask[0x20]; 5087 5088 u8 reserved_at_a0[0x20]; 5089 5090 struct mlx5_ifc_qpc_bits qpc; 5091 5092 u8 reserved_at_800[0x80]; 5093 }; 5094 5095 struct mlx5_ifc_sqd2rts_qp_out_bits { 5096 u8 status[0x8]; 5097 u8 reserved_at_8[0x18]; 5098 5099 u8 syndrome[0x20]; 5100 5101 u8 reserved_at_40[0x40]; 5102 }; 5103 5104 struct mlx5_ifc_sqd2rts_qp_in_bits { 5105 u8 opcode[0x10]; 5106 u8 uid[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 qpn[0x18]; 5113 5114 u8 reserved_at_60[0x20]; 5115 5116 u8 opt_param_mask[0x20]; 5117 5118 u8 reserved_at_a0[0x20]; 5119 5120 struct mlx5_ifc_qpc_bits qpc; 5121 5122 u8 reserved_at_800[0x80]; 5123 }; 5124 5125 struct mlx5_ifc_set_roce_address_out_bits { 5126 u8 status[0x8]; 5127 u8 reserved_at_8[0x18]; 5128 5129 u8 syndrome[0x20]; 5130 5131 u8 reserved_at_40[0x40]; 5132 }; 5133 5134 struct mlx5_ifc_set_roce_address_in_bits { 5135 u8 opcode[0x10]; 5136 u8 reserved_at_10[0x10]; 5137 5138 u8 reserved_at_20[0x10]; 5139 u8 op_mod[0x10]; 5140 5141 u8 roce_address_index[0x10]; 5142 u8 reserved_at_50[0xc]; 5143 u8 vhca_port_num[0x4]; 5144 5145 u8 reserved_at_60[0x20]; 5146 5147 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5148 }; 5149 5150 struct mlx5_ifc_set_mad_demux_out_bits { 5151 u8 status[0x8]; 5152 u8 reserved_at_8[0x18]; 5153 5154 u8 syndrome[0x20]; 5155 5156 u8 reserved_at_40[0x40]; 5157 }; 5158 5159 enum { 5160 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5161 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5162 }; 5163 5164 struct mlx5_ifc_set_mad_demux_in_bits { 5165 u8 opcode[0x10]; 5166 u8 reserved_at_10[0x10]; 5167 5168 u8 reserved_at_20[0x10]; 5169 u8 op_mod[0x10]; 5170 5171 u8 reserved_at_40[0x20]; 5172 5173 u8 reserved_at_60[0x6]; 5174 u8 demux_mode[0x2]; 5175 u8 reserved_at_68[0x18]; 5176 }; 5177 5178 struct mlx5_ifc_set_l2_table_entry_out_bits { 5179 u8 status[0x8]; 5180 u8 reserved_at_8[0x18]; 5181 5182 u8 syndrome[0x20]; 5183 5184 u8 reserved_at_40[0x40]; 5185 }; 5186 5187 struct mlx5_ifc_set_l2_table_entry_in_bits { 5188 u8 opcode[0x10]; 5189 u8 reserved_at_10[0x10]; 5190 5191 u8 reserved_at_20[0x10]; 5192 u8 op_mod[0x10]; 5193 5194 u8 reserved_at_40[0x60]; 5195 5196 u8 reserved_at_a0[0x8]; 5197 u8 table_index[0x18]; 5198 5199 u8 reserved_at_c0[0x20]; 5200 5201 u8 reserved_at_e0[0x10]; 5202 u8 silent_mode_valid[0x1]; 5203 u8 silent_mode[0x1]; 5204 u8 reserved_at_f2[0x1]; 5205 u8 vlan_valid[0x1]; 5206 u8 vlan[0xc]; 5207 5208 struct mlx5_ifc_mac_address_layout_bits mac_address; 5209 5210 u8 reserved_at_140[0xc0]; 5211 }; 5212 5213 struct mlx5_ifc_set_issi_out_bits { 5214 u8 status[0x8]; 5215 u8 reserved_at_8[0x18]; 5216 5217 u8 syndrome[0x20]; 5218 5219 u8 reserved_at_40[0x40]; 5220 }; 5221 5222 struct mlx5_ifc_set_issi_in_bits { 5223 u8 opcode[0x10]; 5224 u8 reserved_at_10[0x10]; 5225 5226 u8 reserved_at_20[0x10]; 5227 u8 op_mod[0x10]; 5228 5229 u8 reserved_at_40[0x10]; 5230 u8 current_issi[0x10]; 5231 5232 u8 reserved_at_60[0x20]; 5233 }; 5234 5235 struct mlx5_ifc_set_hca_cap_out_bits { 5236 u8 status[0x8]; 5237 u8 reserved_at_8[0x18]; 5238 5239 u8 syndrome[0x20]; 5240 5241 u8 reserved_at_40[0x40]; 5242 }; 5243 5244 struct mlx5_ifc_set_hca_cap_in_bits { 5245 u8 opcode[0x10]; 5246 u8 reserved_at_10[0x10]; 5247 5248 u8 reserved_at_20[0x10]; 5249 u8 op_mod[0x10]; 5250 5251 u8 other_function[0x1]; 5252 u8 ec_vf_function[0x1]; 5253 u8 reserved_at_42[0x1]; 5254 u8 function_id_type[0x1]; 5255 u8 reserved_at_44[0xc]; 5256 u8 function_id[0x10]; 5257 5258 u8 reserved_at_60[0x20]; 5259 5260 union mlx5_ifc_hca_cap_union_bits capability; 5261 }; 5262 5263 enum { 5264 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5265 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5266 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5267 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5268 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5269 }; 5270 5271 struct mlx5_ifc_set_fte_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 }; 5279 5280 struct mlx5_ifc_set_fte_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 other_vport[0x1]; 5288 u8 other_eswitch[0x1]; 5289 u8 reserved_at_42[0xe]; 5290 u8 vport_number[0x10]; 5291 5292 u8 reserved_at_60[0x20]; 5293 5294 u8 table_type[0x8]; 5295 u8 reserved_at_88[0x8]; 5296 u8 eswitch_owner_vhca_id[0x10]; 5297 5298 u8 reserved_at_a0[0x8]; 5299 u8 table_id[0x18]; 5300 5301 u8 ignore_flow_level[0x1]; 5302 u8 reserved_at_c1[0x17]; 5303 u8 modify_enable_mask[0x8]; 5304 5305 u8 reserved_at_e0[0x20]; 5306 5307 u8 flow_index[0x20]; 5308 5309 u8 reserved_at_120[0xe0]; 5310 5311 struct mlx5_ifc_flow_context_bits flow_context; 5312 }; 5313 5314 struct mlx5_ifc_dest_format_bits { 5315 u8 destination_type[0x8]; 5316 u8 destination_id[0x18]; 5317 5318 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5319 u8 packet_reformat[0x1]; 5320 u8 reserved_at_22[0xe]; 5321 u8 destination_eswitch_owner_vhca_id[0x10]; 5322 }; 5323 5324 struct mlx5_ifc_rts2rts_qp_out_bits { 5325 u8 status[0x8]; 5326 u8 reserved_at_8[0x18]; 5327 5328 u8 syndrome[0x20]; 5329 5330 u8 reserved_at_40[0x20]; 5331 u8 ece[0x20]; 5332 }; 5333 5334 struct mlx5_ifc_rts2rts_qp_in_bits { 5335 u8 opcode[0x10]; 5336 u8 uid[0x10]; 5337 5338 u8 reserved_at_20[0x10]; 5339 u8 op_mod[0x10]; 5340 5341 u8 reserved_at_40[0x8]; 5342 u8 qpn[0x18]; 5343 5344 u8 reserved_at_60[0x20]; 5345 5346 u8 opt_param_mask[0x20]; 5347 5348 u8 ece[0x20]; 5349 5350 struct mlx5_ifc_qpc_bits qpc; 5351 5352 u8 reserved_at_800[0x80]; 5353 }; 5354 5355 struct mlx5_ifc_rtr2rts_qp_out_bits { 5356 u8 status[0x8]; 5357 u8 reserved_at_8[0x18]; 5358 5359 u8 syndrome[0x20]; 5360 5361 u8 reserved_at_40[0x20]; 5362 u8 ece[0x20]; 5363 }; 5364 5365 struct mlx5_ifc_rtr2rts_qp_in_bits { 5366 u8 opcode[0x10]; 5367 u8 uid[0x10]; 5368 5369 u8 reserved_at_20[0x10]; 5370 u8 op_mod[0x10]; 5371 5372 u8 reserved_at_40[0x8]; 5373 u8 qpn[0x18]; 5374 5375 u8 reserved_at_60[0x20]; 5376 5377 u8 opt_param_mask[0x20]; 5378 5379 u8 ece[0x20]; 5380 5381 struct mlx5_ifc_qpc_bits qpc; 5382 5383 u8 reserved_at_800[0x80]; 5384 }; 5385 5386 struct mlx5_ifc_rst2init_qp_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x20]; 5393 u8 ece[0x20]; 5394 }; 5395 5396 struct mlx5_ifc_rst2init_qp_in_bits { 5397 u8 opcode[0x10]; 5398 u8 uid[0x10]; 5399 5400 u8 reserved_at_20[0x10]; 5401 u8 op_mod[0x10]; 5402 5403 u8 reserved_at_40[0x8]; 5404 u8 qpn[0x18]; 5405 5406 u8 reserved_at_60[0x20]; 5407 5408 u8 opt_param_mask[0x20]; 5409 5410 u8 ece[0x20]; 5411 5412 struct mlx5_ifc_qpc_bits qpc; 5413 5414 u8 reserved_at_800[0x80]; 5415 }; 5416 5417 struct mlx5_ifc_query_xrq_out_bits { 5418 u8 status[0x8]; 5419 u8 reserved_at_8[0x18]; 5420 5421 u8 syndrome[0x20]; 5422 5423 u8 reserved_at_40[0x40]; 5424 5425 struct mlx5_ifc_xrqc_bits xrq_context; 5426 }; 5427 5428 struct mlx5_ifc_query_xrq_in_bits { 5429 u8 opcode[0x10]; 5430 u8 reserved_at_10[0x10]; 5431 5432 u8 reserved_at_20[0x10]; 5433 u8 op_mod[0x10]; 5434 5435 u8 reserved_at_40[0x8]; 5436 u8 xrqn[0x18]; 5437 5438 u8 reserved_at_60[0x20]; 5439 }; 5440 5441 struct mlx5_ifc_query_xrc_srq_out_bits { 5442 u8 status[0x8]; 5443 u8 reserved_at_8[0x18]; 5444 5445 u8 syndrome[0x20]; 5446 5447 u8 reserved_at_40[0x40]; 5448 5449 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5450 5451 u8 reserved_at_280[0x600]; 5452 5453 u8 pas[][0x40]; 5454 }; 5455 5456 struct mlx5_ifc_query_xrc_srq_in_bits { 5457 u8 opcode[0x10]; 5458 u8 reserved_at_10[0x10]; 5459 5460 u8 reserved_at_20[0x10]; 5461 u8 op_mod[0x10]; 5462 5463 u8 reserved_at_40[0x8]; 5464 u8 xrc_srqn[0x18]; 5465 5466 u8 reserved_at_60[0x20]; 5467 }; 5468 5469 enum { 5470 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5471 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5472 }; 5473 5474 struct mlx5_ifc_query_vport_state_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_at_8[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 reserved_at_40[0x20]; 5481 5482 u8 max_tx_speed[0x10]; 5483 u8 reserved_at_70[0x8]; 5484 u8 admin_state[0x4]; 5485 u8 state[0x4]; 5486 }; 5487 5488 struct mlx5_ifc_array1024_auto_bits { 5489 u8 array1024_auto[32][0x20]; 5490 }; 5491 5492 struct mlx5_ifc_query_vuid_in_bits { 5493 u8 opcode[0x10]; 5494 u8 uid[0x10]; 5495 5496 u8 reserved_at_20[0x40]; 5497 5498 u8 query_vfs_vuid[0x1]; 5499 u8 data_direct[0x1]; 5500 u8 reserved_at_62[0xe]; 5501 u8 vhca_id[0x10]; 5502 }; 5503 5504 struct mlx5_ifc_query_vuid_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x1a0]; 5511 5512 u8 reserved_at_1e0[0x10]; 5513 u8 num_of_entries[0x10]; 5514 5515 struct mlx5_ifc_array1024_auto_bits vuid[]; 5516 }; 5517 5518 enum { 5519 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5520 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5521 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5522 }; 5523 5524 struct mlx5_ifc_arm_monitor_counter_in_bits { 5525 u8 opcode[0x10]; 5526 u8 uid[0x10]; 5527 5528 u8 reserved_at_20[0x10]; 5529 u8 op_mod[0x10]; 5530 5531 u8 reserved_at_40[0x20]; 5532 5533 u8 reserved_at_60[0x20]; 5534 }; 5535 5536 struct mlx5_ifc_arm_monitor_counter_out_bits { 5537 u8 status[0x8]; 5538 u8 reserved_at_8[0x18]; 5539 5540 u8 syndrome[0x20]; 5541 5542 u8 reserved_at_40[0x40]; 5543 }; 5544 5545 enum { 5546 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5547 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5548 }; 5549 5550 enum mlx5_monitor_counter_ppcnt { 5551 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5552 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5553 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5554 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5555 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5556 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5557 }; 5558 5559 enum { 5560 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5561 }; 5562 5563 struct mlx5_ifc_monitor_counter_output_bits { 5564 u8 reserved_at_0[0x4]; 5565 u8 type[0x4]; 5566 u8 reserved_at_8[0x8]; 5567 u8 counter[0x10]; 5568 5569 u8 counter_group_id[0x20]; 5570 }; 5571 5572 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5573 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5574 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5575 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5576 5577 struct mlx5_ifc_set_monitor_counter_in_bits { 5578 u8 opcode[0x10]; 5579 u8 uid[0x10]; 5580 5581 u8 reserved_at_20[0x10]; 5582 u8 op_mod[0x10]; 5583 5584 u8 reserved_at_40[0x10]; 5585 u8 num_of_counters[0x10]; 5586 5587 u8 reserved_at_60[0x20]; 5588 5589 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5590 }; 5591 5592 struct mlx5_ifc_set_monitor_counter_out_bits { 5593 u8 status[0x8]; 5594 u8 reserved_at_8[0x18]; 5595 5596 u8 syndrome[0x20]; 5597 5598 u8 reserved_at_40[0x40]; 5599 }; 5600 5601 struct mlx5_ifc_query_vport_state_in_bits { 5602 u8 opcode[0x10]; 5603 u8 reserved_at_10[0x10]; 5604 5605 u8 reserved_at_20[0x10]; 5606 u8 op_mod[0x10]; 5607 5608 u8 other_vport[0x1]; 5609 u8 reserved_at_41[0xf]; 5610 u8 vport_number[0x10]; 5611 5612 u8 reserved_at_60[0x20]; 5613 }; 5614 5615 struct mlx5_ifc_query_vnic_env_out_bits { 5616 u8 status[0x8]; 5617 u8 reserved_at_8[0x18]; 5618 5619 u8 syndrome[0x20]; 5620 5621 u8 reserved_at_40[0x40]; 5622 5623 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5624 }; 5625 5626 enum { 5627 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5628 }; 5629 5630 struct mlx5_ifc_query_vnic_env_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_at_10[0x10]; 5633 5634 u8 reserved_at_20[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 other_vport[0x1]; 5638 u8 reserved_at_41[0xf]; 5639 u8 vport_number[0x10]; 5640 5641 u8 reserved_at_60[0x20]; 5642 }; 5643 5644 struct mlx5_ifc_query_vport_counter_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x40]; 5651 5652 struct mlx5_ifc_traffic_counter_bits received_errors; 5653 5654 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5655 5656 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5657 5658 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5659 5660 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5661 5662 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5663 5664 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5665 5666 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5667 5668 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5669 5670 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5671 5672 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5673 5674 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5675 5676 struct mlx5_ifc_traffic_counter_bits local_loopback; 5677 5678 u8 reserved_at_700[0x980]; 5679 }; 5680 5681 enum { 5682 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5683 }; 5684 5685 struct mlx5_ifc_query_vport_counter_in_bits { 5686 u8 opcode[0x10]; 5687 u8 reserved_at_10[0x10]; 5688 5689 u8 reserved_at_20[0x10]; 5690 u8 op_mod[0x10]; 5691 5692 u8 other_vport[0x1]; 5693 u8 reserved_at_41[0xb]; 5694 u8 port_num[0x4]; 5695 u8 vport_number[0x10]; 5696 5697 u8 reserved_at_60[0x60]; 5698 5699 u8 clear[0x1]; 5700 u8 reserved_at_c1[0x1f]; 5701 5702 u8 reserved_at_e0[0x20]; 5703 }; 5704 5705 struct mlx5_ifc_query_tis_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0x40]; 5712 5713 struct mlx5_ifc_tisc_bits tis_context; 5714 }; 5715 5716 struct mlx5_ifc_query_tis_in_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 reserved_at_40[0x8]; 5724 u8 tisn[0x18]; 5725 5726 u8 reserved_at_60[0x20]; 5727 }; 5728 5729 struct mlx5_ifc_query_tir_out_bits { 5730 u8 status[0x8]; 5731 u8 reserved_at_8[0x18]; 5732 5733 u8 syndrome[0x20]; 5734 5735 u8 reserved_at_40[0xc0]; 5736 5737 struct mlx5_ifc_tirc_bits tir_context; 5738 }; 5739 5740 struct mlx5_ifc_query_tir_in_bits { 5741 u8 opcode[0x10]; 5742 u8 reserved_at_10[0x10]; 5743 5744 u8 reserved_at_20[0x10]; 5745 u8 op_mod[0x10]; 5746 5747 u8 reserved_at_40[0x8]; 5748 u8 tirn[0x18]; 5749 5750 u8 reserved_at_60[0x20]; 5751 }; 5752 5753 struct mlx5_ifc_query_srq_out_bits { 5754 u8 status[0x8]; 5755 u8 reserved_at_8[0x18]; 5756 5757 u8 syndrome[0x20]; 5758 5759 u8 reserved_at_40[0x40]; 5760 5761 struct mlx5_ifc_srqc_bits srq_context_entry; 5762 5763 u8 reserved_at_280[0x600]; 5764 5765 u8 pas[][0x40]; 5766 }; 5767 5768 struct mlx5_ifc_query_srq_in_bits { 5769 u8 opcode[0x10]; 5770 u8 reserved_at_10[0x10]; 5771 5772 u8 reserved_at_20[0x10]; 5773 u8 op_mod[0x10]; 5774 5775 u8 reserved_at_40[0x8]; 5776 u8 srqn[0x18]; 5777 5778 u8 reserved_at_60[0x20]; 5779 }; 5780 5781 struct mlx5_ifc_query_sq_out_bits { 5782 u8 status[0x8]; 5783 u8 reserved_at_8[0x18]; 5784 5785 u8 syndrome[0x20]; 5786 5787 u8 reserved_at_40[0xc0]; 5788 5789 struct mlx5_ifc_sqc_bits sq_context; 5790 }; 5791 5792 struct mlx5_ifc_query_sq_in_bits { 5793 u8 opcode[0x10]; 5794 u8 reserved_at_10[0x10]; 5795 5796 u8 reserved_at_20[0x10]; 5797 u8 op_mod[0x10]; 5798 5799 u8 reserved_at_40[0x8]; 5800 u8 sqn[0x18]; 5801 5802 u8 reserved_at_60[0x20]; 5803 }; 5804 5805 struct mlx5_ifc_query_special_contexts_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_at_8[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 dump_fill_mkey[0x20]; 5812 5813 u8 resd_lkey[0x20]; 5814 5815 u8 null_mkey[0x20]; 5816 5817 u8 terminate_scatter_list_mkey[0x20]; 5818 5819 u8 repeated_mkey[0x20]; 5820 5821 u8 reserved_at_a0[0x20]; 5822 }; 5823 5824 struct mlx5_ifc_query_special_contexts_in_bits { 5825 u8 opcode[0x10]; 5826 u8 reserved_at_10[0x10]; 5827 5828 u8 reserved_at_20[0x10]; 5829 u8 op_mod[0x10]; 5830 5831 u8 reserved_at_40[0x40]; 5832 }; 5833 5834 struct mlx5_ifc_query_scheduling_element_out_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_at_10[0x10]; 5837 5838 u8 reserved_at_20[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 reserved_at_40[0xc0]; 5842 5843 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5844 5845 u8 reserved_at_300[0x100]; 5846 }; 5847 5848 enum { 5849 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5850 SCHEDULING_HIERARCHY_NIC = 0x3, 5851 }; 5852 5853 struct mlx5_ifc_query_scheduling_element_in_bits { 5854 u8 opcode[0x10]; 5855 u8 reserved_at_10[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 scheduling_hierarchy[0x8]; 5861 u8 reserved_at_48[0x18]; 5862 5863 u8 scheduling_element_id[0x20]; 5864 5865 u8 reserved_at_80[0x180]; 5866 }; 5867 5868 struct mlx5_ifc_query_rqt_out_bits { 5869 u8 status[0x8]; 5870 u8 reserved_at_8[0x18]; 5871 5872 u8 syndrome[0x20]; 5873 5874 u8 reserved_at_40[0xc0]; 5875 5876 struct mlx5_ifc_rqtc_bits rqt_context; 5877 }; 5878 5879 struct mlx5_ifc_query_rqt_in_bits { 5880 u8 opcode[0x10]; 5881 u8 reserved_at_10[0x10]; 5882 5883 u8 reserved_at_20[0x10]; 5884 u8 op_mod[0x10]; 5885 5886 u8 reserved_at_40[0x8]; 5887 u8 rqtn[0x18]; 5888 5889 u8 reserved_at_60[0x20]; 5890 }; 5891 5892 struct mlx5_ifc_query_rq_out_bits { 5893 u8 status[0x8]; 5894 u8 reserved_at_8[0x18]; 5895 5896 u8 syndrome[0x20]; 5897 5898 u8 reserved_at_40[0xc0]; 5899 5900 struct mlx5_ifc_rqc_bits rq_context; 5901 }; 5902 5903 struct mlx5_ifc_query_rq_in_bits { 5904 u8 opcode[0x10]; 5905 u8 reserved_at_10[0x10]; 5906 5907 u8 reserved_at_20[0x10]; 5908 u8 op_mod[0x10]; 5909 5910 u8 reserved_at_40[0x8]; 5911 u8 rqn[0x18]; 5912 5913 u8 reserved_at_60[0x20]; 5914 }; 5915 5916 struct mlx5_ifc_query_roce_address_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x40]; 5923 5924 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5925 }; 5926 5927 struct mlx5_ifc_query_roce_address_in_bits { 5928 u8 opcode[0x10]; 5929 u8 reserved_at_10[0x10]; 5930 5931 u8 reserved_at_20[0x10]; 5932 u8 op_mod[0x10]; 5933 5934 u8 roce_address_index[0x10]; 5935 u8 reserved_at_50[0xc]; 5936 u8 vhca_port_num[0x4]; 5937 5938 u8 reserved_at_60[0x20]; 5939 }; 5940 5941 struct mlx5_ifc_query_rmp_out_bits { 5942 u8 status[0x8]; 5943 u8 reserved_at_8[0x18]; 5944 5945 u8 syndrome[0x20]; 5946 5947 u8 reserved_at_40[0xc0]; 5948 5949 struct mlx5_ifc_rmpc_bits rmp_context; 5950 }; 5951 5952 struct mlx5_ifc_query_rmp_in_bits { 5953 u8 opcode[0x10]; 5954 u8 reserved_at_10[0x10]; 5955 5956 u8 reserved_at_20[0x10]; 5957 u8 op_mod[0x10]; 5958 5959 u8 reserved_at_40[0x8]; 5960 u8 rmpn[0x18]; 5961 5962 u8 reserved_at_60[0x20]; 5963 }; 5964 5965 struct mlx5_ifc_cqe_error_syndrome_bits { 5966 u8 hw_error_syndrome[0x8]; 5967 u8 hw_syndrome_type[0x4]; 5968 u8 reserved_at_c[0x4]; 5969 u8 vendor_error_syndrome[0x8]; 5970 u8 syndrome[0x8]; 5971 }; 5972 5973 struct mlx5_ifc_qp_context_extension_bits { 5974 u8 reserved_at_0[0x60]; 5975 5976 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5977 5978 u8 reserved_at_80[0x580]; 5979 }; 5980 5981 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5982 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5983 5984 u8 pas[0][0x40]; 5985 }; 5986 5987 struct mlx5_ifc_qp_pas_list_in_bits { 5988 struct mlx5_ifc_cmd_pas_bits pas[0]; 5989 }; 5990 5991 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5992 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5993 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5994 }; 5995 5996 struct mlx5_ifc_query_qp_out_bits { 5997 u8 status[0x8]; 5998 u8 reserved_at_8[0x18]; 5999 6000 u8 syndrome[0x20]; 6001 6002 u8 reserved_at_40[0x40]; 6003 6004 u8 opt_param_mask[0x20]; 6005 6006 u8 ece[0x20]; 6007 6008 struct mlx5_ifc_qpc_bits qpc; 6009 6010 u8 reserved_at_800[0x80]; 6011 6012 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 6013 }; 6014 6015 struct mlx5_ifc_query_qp_in_bits { 6016 u8 opcode[0x10]; 6017 u8 reserved_at_10[0x10]; 6018 6019 u8 reserved_at_20[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 qpc_ext[0x1]; 6023 u8 reserved_at_41[0x7]; 6024 u8 qpn[0x18]; 6025 6026 u8 reserved_at_60[0x20]; 6027 }; 6028 6029 struct mlx5_ifc_query_q_counter_out_bits { 6030 u8 status[0x8]; 6031 u8 reserved_at_8[0x18]; 6032 6033 u8 syndrome[0x20]; 6034 6035 u8 reserved_at_40[0x40]; 6036 6037 u8 rx_write_requests[0x20]; 6038 6039 u8 reserved_at_a0[0x20]; 6040 6041 u8 rx_read_requests[0x20]; 6042 6043 u8 reserved_at_e0[0x20]; 6044 6045 u8 rx_atomic_requests[0x20]; 6046 6047 u8 reserved_at_120[0x20]; 6048 6049 u8 rx_dct_connect[0x20]; 6050 6051 u8 reserved_at_160[0x20]; 6052 6053 u8 out_of_buffer[0x20]; 6054 6055 u8 reserved_at_1a0[0x20]; 6056 6057 u8 out_of_sequence[0x20]; 6058 6059 u8 reserved_at_1e0[0x20]; 6060 6061 u8 duplicate_request[0x20]; 6062 6063 u8 reserved_at_220[0x20]; 6064 6065 u8 rnr_nak_retry_err[0x20]; 6066 6067 u8 reserved_at_260[0x20]; 6068 6069 u8 packet_seq_err[0x20]; 6070 6071 u8 reserved_at_2a0[0x20]; 6072 6073 u8 implied_nak_seq_err[0x20]; 6074 6075 u8 reserved_at_2e0[0x20]; 6076 6077 u8 local_ack_timeout_err[0x20]; 6078 6079 u8 reserved_at_320[0x60]; 6080 6081 u8 req_rnr_retries_exceeded[0x20]; 6082 6083 u8 reserved_at_3a0[0x20]; 6084 6085 u8 resp_local_length_error[0x20]; 6086 6087 u8 req_local_length_error[0x20]; 6088 6089 u8 resp_local_qp_error[0x20]; 6090 6091 u8 local_operation_error[0x20]; 6092 6093 u8 resp_local_protection[0x20]; 6094 6095 u8 req_local_protection[0x20]; 6096 6097 u8 resp_cqe_error[0x20]; 6098 6099 u8 req_cqe_error[0x20]; 6100 6101 u8 req_mw_binding[0x20]; 6102 6103 u8 req_bad_response[0x20]; 6104 6105 u8 req_remote_invalid_request[0x20]; 6106 6107 u8 resp_remote_invalid_request[0x20]; 6108 6109 u8 req_remote_access_errors[0x20]; 6110 6111 u8 resp_remote_access_errors[0x20]; 6112 6113 u8 req_remote_operation_errors[0x20]; 6114 6115 u8 req_transport_retries_exceeded[0x20]; 6116 6117 u8 cq_overflow[0x20]; 6118 6119 u8 resp_cqe_flush_error[0x20]; 6120 6121 u8 req_cqe_flush_error[0x20]; 6122 6123 u8 reserved_at_620[0x20]; 6124 6125 u8 roce_adp_retrans[0x20]; 6126 6127 u8 roce_adp_retrans_to[0x20]; 6128 6129 u8 roce_slow_restart[0x20]; 6130 6131 u8 roce_slow_restart_cnps[0x20]; 6132 6133 u8 roce_slow_restart_trans[0x20]; 6134 6135 u8 reserved_at_6e0[0x120]; 6136 }; 6137 6138 struct mlx5_ifc_query_q_counter_in_bits { 6139 u8 opcode[0x10]; 6140 u8 reserved_at_10[0x10]; 6141 6142 u8 reserved_at_20[0x10]; 6143 u8 op_mod[0x10]; 6144 6145 u8 other_vport[0x1]; 6146 u8 reserved_at_41[0xf]; 6147 u8 vport_number[0x10]; 6148 6149 u8 reserved_at_60[0x60]; 6150 6151 u8 clear[0x1]; 6152 u8 aggregate[0x1]; 6153 u8 reserved_at_c2[0x1e]; 6154 6155 u8 reserved_at_e0[0x18]; 6156 u8 counter_set_id[0x8]; 6157 }; 6158 6159 struct mlx5_ifc_query_pages_out_bits { 6160 u8 status[0x8]; 6161 u8 reserved_at_8[0x18]; 6162 6163 u8 syndrome[0x20]; 6164 6165 u8 embedded_cpu_function[0x1]; 6166 u8 reserved_at_41[0xf]; 6167 u8 function_id[0x10]; 6168 6169 u8 num_pages[0x20]; 6170 }; 6171 6172 enum { 6173 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6174 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6175 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6176 }; 6177 6178 struct mlx5_ifc_query_pages_in_bits { 6179 u8 opcode[0x10]; 6180 u8 reserved_at_10[0x10]; 6181 6182 u8 reserved_at_20[0x10]; 6183 u8 op_mod[0x10]; 6184 6185 u8 embedded_cpu_function[0x1]; 6186 u8 reserved_at_41[0xf]; 6187 u8 function_id[0x10]; 6188 6189 u8 reserved_at_60[0x20]; 6190 }; 6191 6192 struct mlx5_ifc_query_nic_vport_context_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_at_8[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_at_40[0x40]; 6199 6200 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6201 }; 6202 6203 struct mlx5_ifc_query_nic_vport_context_in_bits { 6204 u8 opcode[0x10]; 6205 u8 reserved_at_10[0x10]; 6206 6207 u8 reserved_at_20[0x10]; 6208 u8 op_mod[0x10]; 6209 6210 u8 other_vport[0x1]; 6211 u8 reserved_at_41[0xf]; 6212 u8 vport_number[0x10]; 6213 6214 u8 reserved_at_60[0x5]; 6215 u8 allowed_list_type[0x3]; 6216 u8 reserved_at_68[0x18]; 6217 }; 6218 6219 struct mlx5_ifc_query_mkey_out_bits { 6220 u8 status[0x8]; 6221 u8 reserved_at_8[0x18]; 6222 6223 u8 syndrome[0x20]; 6224 6225 u8 reserved_at_40[0x40]; 6226 6227 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6228 6229 u8 reserved_at_280[0x600]; 6230 6231 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6232 6233 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6234 }; 6235 6236 struct mlx5_ifc_query_mkey_in_bits { 6237 u8 opcode[0x10]; 6238 u8 reserved_at_10[0x10]; 6239 6240 u8 reserved_at_20[0x10]; 6241 u8 op_mod[0x10]; 6242 6243 u8 reserved_at_40[0x8]; 6244 u8 mkey_index[0x18]; 6245 6246 u8 pg_access[0x1]; 6247 u8 reserved_at_61[0x1f]; 6248 }; 6249 6250 struct mlx5_ifc_query_mad_demux_out_bits { 6251 u8 status[0x8]; 6252 u8 reserved_at_8[0x18]; 6253 6254 u8 syndrome[0x20]; 6255 6256 u8 reserved_at_40[0x40]; 6257 6258 u8 mad_dumux_parameters_block[0x20]; 6259 }; 6260 6261 struct mlx5_ifc_query_mad_demux_in_bits { 6262 u8 opcode[0x10]; 6263 u8 reserved_at_10[0x10]; 6264 6265 u8 reserved_at_20[0x10]; 6266 u8 op_mod[0x10]; 6267 6268 u8 reserved_at_40[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_query_l2_table_entry_out_bits { 6272 u8 status[0x8]; 6273 u8 reserved_at_8[0x18]; 6274 6275 u8 syndrome[0x20]; 6276 6277 u8 reserved_at_40[0xa0]; 6278 6279 u8 reserved_at_e0[0x11]; 6280 u8 silent_mode[0x1]; 6281 u8 reserved_at_f2[0x1]; 6282 u8 vlan_valid[0x1]; 6283 u8 vlan[0xc]; 6284 6285 struct mlx5_ifc_mac_address_layout_bits mac_address; 6286 6287 u8 reserved_at_140[0xc0]; 6288 }; 6289 6290 struct mlx5_ifc_query_l2_table_entry_in_bits { 6291 u8 opcode[0x10]; 6292 u8 reserved_at_10[0x10]; 6293 6294 u8 reserved_at_20[0x10]; 6295 u8 op_mod[0x10]; 6296 6297 u8 reserved_at_40[0x40]; 6298 6299 u8 silent_mode_query[0x1]; 6300 u8 reserved_at_81[0x1f]; 6301 6302 u8 reserved_at_a0[0x8]; 6303 u8 table_index[0x18]; 6304 6305 u8 reserved_at_c0[0x140]; 6306 }; 6307 6308 struct mlx5_ifc_query_issi_out_bits { 6309 u8 status[0x8]; 6310 u8 reserved_at_8[0x18]; 6311 6312 u8 syndrome[0x20]; 6313 6314 u8 reserved_at_40[0x10]; 6315 u8 current_issi[0x10]; 6316 6317 u8 reserved_at_60[0xa0]; 6318 6319 u8 reserved_at_100[76][0x8]; 6320 u8 supported_issi_dw0[0x20]; 6321 }; 6322 6323 struct mlx5_ifc_query_issi_in_bits { 6324 u8 opcode[0x10]; 6325 u8 reserved_at_10[0x10]; 6326 6327 u8 reserved_at_20[0x10]; 6328 u8 op_mod[0x10]; 6329 6330 u8 reserved_at_40[0x40]; 6331 }; 6332 6333 struct mlx5_ifc_set_driver_version_out_bits { 6334 u8 status[0x8]; 6335 u8 reserved_0[0x18]; 6336 6337 u8 syndrome[0x20]; 6338 u8 reserved_1[0x40]; 6339 }; 6340 6341 struct mlx5_ifc_set_driver_version_in_bits { 6342 u8 opcode[0x10]; 6343 u8 reserved_0[0x10]; 6344 6345 u8 reserved_1[0x10]; 6346 u8 op_mod[0x10]; 6347 6348 u8 reserved_2[0x40]; 6349 u8 driver_version[64][0x8]; 6350 }; 6351 6352 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6353 u8 status[0x8]; 6354 u8 reserved_at_8[0x18]; 6355 6356 u8 syndrome[0x20]; 6357 6358 u8 reserved_at_40[0x40]; 6359 6360 struct mlx5_ifc_pkey_bits pkey[]; 6361 }; 6362 6363 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6364 u8 opcode[0x10]; 6365 u8 reserved_at_10[0x10]; 6366 6367 u8 reserved_at_20[0x10]; 6368 u8 op_mod[0x10]; 6369 6370 u8 other_vport[0x1]; 6371 u8 reserved_at_41[0xb]; 6372 u8 port_num[0x4]; 6373 u8 vport_number[0x10]; 6374 6375 u8 reserved_at_60[0x10]; 6376 u8 pkey_index[0x10]; 6377 }; 6378 6379 enum { 6380 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6381 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6382 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6383 }; 6384 6385 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6386 u8 status[0x8]; 6387 u8 reserved_at_8[0x18]; 6388 6389 u8 syndrome[0x20]; 6390 6391 u8 reserved_at_40[0x20]; 6392 6393 u8 gids_num[0x10]; 6394 u8 reserved_at_70[0x10]; 6395 6396 struct mlx5_ifc_array128_auto_bits gid[]; 6397 }; 6398 6399 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6400 u8 opcode[0x10]; 6401 u8 reserved_at_10[0x10]; 6402 6403 u8 reserved_at_20[0x10]; 6404 u8 op_mod[0x10]; 6405 6406 u8 other_vport[0x1]; 6407 u8 reserved_at_41[0xb]; 6408 u8 port_num[0x4]; 6409 u8 vport_number[0x10]; 6410 6411 u8 reserved_at_60[0x10]; 6412 u8 gid_index[0x10]; 6413 }; 6414 6415 struct mlx5_ifc_query_hca_vport_context_out_bits { 6416 u8 status[0x8]; 6417 u8 reserved_at_8[0x18]; 6418 6419 u8 syndrome[0x20]; 6420 6421 u8 reserved_at_40[0x40]; 6422 6423 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6424 }; 6425 6426 struct mlx5_ifc_query_hca_vport_context_in_bits { 6427 u8 opcode[0x10]; 6428 u8 reserved_at_10[0x10]; 6429 6430 u8 reserved_at_20[0x10]; 6431 u8 op_mod[0x10]; 6432 6433 u8 other_vport[0x1]; 6434 u8 reserved_at_41[0xb]; 6435 u8 port_num[0x4]; 6436 u8 vport_number[0x10]; 6437 6438 u8 reserved_at_60[0x20]; 6439 }; 6440 6441 struct mlx5_ifc_query_hca_cap_out_bits { 6442 u8 status[0x8]; 6443 u8 reserved_at_8[0x18]; 6444 6445 u8 syndrome[0x20]; 6446 6447 u8 reserved_at_40[0x40]; 6448 6449 union mlx5_ifc_hca_cap_union_bits capability; 6450 }; 6451 6452 struct mlx5_ifc_query_hca_cap_in_bits { 6453 u8 opcode[0x10]; 6454 u8 reserved_at_10[0x10]; 6455 6456 u8 reserved_at_20[0x10]; 6457 u8 op_mod[0x10]; 6458 6459 u8 other_function[0x1]; 6460 u8 ec_vf_function[0x1]; 6461 u8 reserved_at_42[0x1]; 6462 u8 function_id_type[0x1]; 6463 u8 reserved_at_44[0xc]; 6464 u8 function_id[0x10]; 6465 6466 u8 reserved_at_60[0x20]; 6467 }; 6468 6469 struct mlx5_ifc_other_hca_cap_bits { 6470 u8 roce[0x1]; 6471 u8 reserved_at_1[0x27f]; 6472 }; 6473 6474 struct mlx5_ifc_query_other_hca_cap_out_bits { 6475 u8 status[0x8]; 6476 u8 reserved_at_8[0x18]; 6477 6478 u8 syndrome[0x20]; 6479 6480 u8 reserved_at_40[0x40]; 6481 6482 struct mlx5_ifc_other_hca_cap_bits other_capability; 6483 }; 6484 6485 struct mlx5_ifc_query_other_hca_cap_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_at_10[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_at_40[0x10]; 6493 u8 function_id[0x10]; 6494 6495 u8 reserved_at_60[0x20]; 6496 }; 6497 6498 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6499 u8 status[0x8]; 6500 u8 reserved_at_8[0x18]; 6501 6502 u8 syndrome[0x20]; 6503 6504 u8 reserved_at_40[0x40]; 6505 }; 6506 6507 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6508 u8 opcode[0x10]; 6509 u8 reserved_at_10[0x10]; 6510 6511 u8 reserved_at_20[0x10]; 6512 u8 op_mod[0x10]; 6513 6514 u8 reserved_at_40[0x10]; 6515 u8 function_id[0x10]; 6516 u8 field_select[0x20]; 6517 6518 struct mlx5_ifc_other_hca_cap_bits other_capability; 6519 }; 6520 6521 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6522 u8 sw_owner_icm_root_1[0x40]; 6523 6524 u8 sw_owner_icm_root_0[0x40]; 6525 }; 6526 6527 struct mlx5_ifc_rtc_params_bits { 6528 u8 rtc_id_0[0x20]; 6529 6530 u8 rtc_id_1[0x20]; 6531 6532 u8 reserved_at_40[0x40]; 6533 }; 6534 6535 struct mlx5_ifc_flow_table_context_bits { 6536 u8 reformat_en[0x1]; 6537 u8 decap_en[0x1]; 6538 u8 sw_owner[0x1]; 6539 u8 termination_table[0x1]; 6540 u8 table_miss_action[0x4]; 6541 u8 level[0x8]; 6542 u8 rtc_valid[0x1]; 6543 u8 reserved_at_11[0x7]; 6544 u8 log_size[0x8]; 6545 6546 u8 reserved_at_20[0x8]; 6547 u8 table_miss_id[0x18]; 6548 6549 u8 reserved_at_40[0x8]; 6550 u8 lag_master_next_table_id[0x18]; 6551 6552 u8 reserved_at_60[0x60]; 6553 6554 union { 6555 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6556 struct mlx5_ifc_rtc_params_bits hws; 6557 }; 6558 }; 6559 6560 struct mlx5_ifc_query_flow_table_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x80]; 6567 6568 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6569 }; 6570 6571 struct mlx5_ifc_query_flow_table_in_bits { 6572 u8 opcode[0x10]; 6573 u8 reserved_at_10[0x10]; 6574 6575 u8 reserved_at_20[0x10]; 6576 u8 op_mod[0x10]; 6577 6578 u8 reserved_at_40[0x40]; 6579 6580 u8 table_type[0x8]; 6581 u8 reserved_at_88[0x18]; 6582 6583 u8 reserved_at_a0[0x8]; 6584 u8 table_id[0x18]; 6585 6586 u8 reserved_at_c0[0x140]; 6587 }; 6588 6589 struct mlx5_ifc_query_fte_out_bits { 6590 u8 status[0x8]; 6591 u8 reserved_at_8[0x18]; 6592 6593 u8 syndrome[0x20]; 6594 6595 u8 reserved_at_40[0x1c0]; 6596 6597 struct mlx5_ifc_flow_context_bits flow_context; 6598 }; 6599 6600 struct mlx5_ifc_query_fte_in_bits { 6601 u8 opcode[0x10]; 6602 u8 reserved_at_10[0x10]; 6603 6604 u8 reserved_at_20[0x10]; 6605 u8 op_mod[0x10]; 6606 6607 u8 reserved_at_40[0x40]; 6608 6609 u8 table_type[0x8]; 6610 u8 reserved_at_88[0x18]; 6611 6612 u8 reserved_at_a0[0x8]; 6613 u8 table_id[0x18]; 6614 6615 u8 reserved_at_c0[0x40]; 6616 6617 u8 flow_index[0x20]; 6618 6619 u8 reserved_at_120[0xe0]; 6620 }; 6621 6622 struct mlx5_ifc_match_definer_format_0_bits { 6623 u8 reserved_at_0[0x100]; 6624 6625 u8 metadata_reg_c_0[0x20]; 6626 6627 u8 metadata_reg_c_1[0x20]; 6628 6629 u8 outer_dmac_47_16[0x20]; 6630 6631 u8 outer_dmac_15_0[0x10]; 6632 u8 outer_ethertype[0x10]; 6633 6634 u8 reserved_at_180[0x1]; 6635 u8 sx_sniffer[0x1]; 6636 u8 functional_lb[0x1]; 6637 u8 outer_ip_frag[0x1]; 6638 u8 outer_qp_type[0x2]; 6639 u8 outer_encap_type[0x2]; 6640 u8 port_number[0x2]; 6641 u8 outer_l3_type[0x2]; 6642 u8 outer_l4_type[0x2]; 6643 u8 outer_first_vlan_type[0x2]; 6644 u8 outer_first_vlan_prio[0x3]; 6645 u8 outer_first_vlan_cfi[0x1]; 6646 u8 outer_first_vlan_vid[0xc]; 6647 6648 u8 outer_l4_type_ext[0x4]; 6649 u8 reserved_at_1a4[0x2]; 6650 u8 outer_ipsec_layer[0x2]; 6651 u8 outer_l2_type[0x2]; 6652 u8 force_lb[0x1]; 6653 u8 outer_l2_ok[0x1]; 6654 u8 outer_l3_ok[0x1]; 6655 u8 outer_l4_ok[0x1]; 6656 u8 outer_second_vlan_type[0x2]; 6657 u8 outer_second_vlan_prio[0x3]; 6658 u8 outer_second_vlan_cfi[0x1]; 6659 u8 outer_second_vlan_vid[0xc]; 6660 6661 u8 outer_smac_47_16[0x20]; 6662 6663 u8 outer_smac_15_0[0x10]; 6664 u8 inner_ipv4_checksum_ok[0x1]; 6665 u8 inner_l4_checksum_ok[0x1]; 6666 u8 outer_ipv4_checksum_ok[0x1]; 6667 u8 outer_l4_checksum_ok[0x1]; 6668 u8 inner_l3_ok[0x1]; 6669 u8 inner_l4_ok[0x1]; 6670 u8 outer_l3_ok_duplicate[0x1]; 6671 u8 outer_l4_ok_duplicate[0x1]; 6672 u8 outer_tcp_cwr[0x1]; 6673 u8 outer_tcp_ece[0x1]; 6674 u8 outer_tcp_urg[0x1]; 6675 u8 outer_tcp_ack[0x1]; 6676 u8 outer_tcp_psh[0x1]; 6677 u8 outer_tcp_rst[0x1]; 6678 u8 outer_tcp_syn[0x1]; 6679 u8 outer_tcp_fin[0x1]; 6680 }; 6681 6682 struct mlx5_ifc_match_definer_format_22_bits { 6683 u8 reserved_at_0[0x100]; 6684 6685 u8 outer_ip_src_addr[0x20]; 6686 6687 u8 outer_ip_dest_addr[0x20]; 6688 6689 u8 outer_l4_sport[0x10]; 6690 u8 outer_l4_dport[0x10]; 6691 6692 u8 reserved_at_160[0x1]; 6693 u8 sx_sniffer[0x1]; 6694 u8 functional_lb[0x1]; 6695 u8 outer_ip_frag[0x1]; 6696 u8 outer_qp_type[0x2]; 6697 u8 outer_encap_type[0x2]; 6698 u8 port_number[0x2]; 6699 u8 outer_l3_type[0x2]; 6700 u8 outer_l4_type[0x2]; 6701 u8 outer_first_vlan_type[0x2]; 6702 u8 outer_first_vlan_prio[0x3]; 6703 u8 outer_first_vlan_cfi[0x1]; 6704 u8 outer_first_vlan_vid[0xc]; 6705 6706 u8 metadata_reg_c_0[0x20]; 6707 6708 u8 outer_dmac_47_16[0x20]; 6709 6710 u8 outer_smac_47_16[0x20]; 6711 6712 u8 outer_smac_15_0[0x10]; 6713 u8 outer_dmac_15_0[0x10]; 6714 }; 6715 6716 struct mlx5_ifc_match_definer_format_23_bits { 6717 u8 reserved_at_0[0x100]; 6718 6719 u8 inner_ip_src_addr[0x20]; 6720 6721 u8 inner_ip_dest_addr[0x20]; 6722 6723 u8 inner_l4_sport[0x10]; 6724 u8 inner_l4_dport[0x10]; 6725 6726 u8 reserved_at_160[0x1]; 6727 u8 sx_sniffer[0x1]; 6728 u8 functional_lb[0x1]; 6729 u8 inner_ip_frag[0x1]; 6730 u8 inner_qp_type[0x2]; 6731 u8 inner_encap_type[0x2]; 6732 u8 port_number[0x2]; 6733 u8 inner_l3_type[0x2]; 6734 u8 inner_l4_type[0x2]; 6735 u8 inner_first_vlan_type[0x2]; 6736 u8 inner_first_vlan_prio[0x3]; 6737 u8 inner_first_vlan_cfi[0x1]; 6738 u8 inner_first_vlan_vid[0xc]; 6739 6740 u8 tunnel_header_0[0x20]; 6741 6742 u8 inner_dmac_47_16[0x20]; 6743 6744 u8 inner_smac_47_16[0x20]; 6745 6746 u8 inner_smac_15_0[0x10]; 6747 u8 inner_dmac_15_0[0x10]; 6748 }; 6749 6750 struct mlx5_ifc_match_definer_format_29_bits { 6751 u8 reserved_at_0[0xc0]; 6752 6753 u8 outer_ip_dest_addr[0x80]; 6754 6755 u8 outer_ip_src_addr[0x80]; 6756 6757 u8 outer_l4_sport[0x10]; 6758 u8 outer_l4_dport[0x10]; 6759 6760 u8 reserved_at_1e0[0x20]; 6761 }; 6762 6763 struct mlx5_ifc_match_definer_format_30_bits { 6764 u8 reserved_at_0[0xa0]; 6765 6766 u8 outer_ip_dest_addr[0x80]; 6767 6768 u8 outer_ip_src_addr[0x80]; 6769 6770 u8 outer_dmac_47_16[0x20]; 6771 6772 u8 outer_smac_47_16[0x20]; 6773 6774 u8 outer_smac_15_0[0x10]; 6775 u8 outer_dmac_15_0[0x10]; 6776 }; 6777 6778 struct mlx5_ifc_match_definer_format_31_bits { 6779 u8 reserved_at_0[0xc0]; 6780 6781 u8 inner_ip_dest_addr[0x80]; 6782 6783 u8 inner_ip_src_addr[0x80]; 6784 6785 u8 inner_l4_sport[0x10]; 6786 u8 inner_l4_dport[0x10]; 6787 6788 u8 reserved_at_1e0[0x20]; 6789 }; 6790 6791 struct mlx5_ifc_match_definer_format_32_bits { 6792 u8 reserved_at_0[0xa0]; 6793 6794 u8 inner_ip_dest_addr[0x80]; 6795 6796 u8 inner_ip_src_addr[0x80]; 6797 6798 u8 inner_dmac_47_16[0x20]; 6799 6800 u8 inner_smac_47_16[0x20]; 6801 6802 u8 inner_smac_15_0[0x10]; 6803 u8 inner_dmac_15_0[0x10]; 6804 }; 6805 6806 enum { 6807 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6808 }; 6809 6810 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6811 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6812 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6813 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6814 6815 struct mlx5_ifc_match_definer_match_mask_bits { 6816 u8 reserved_at_1c0[5][0x20]; 6817 u8 match_dw_8[0x20]; 6818 u8 match_dw_7[0x20]; 6819 u8 match_dw_6[0x20]; 6820 u8 match_dw_5[0x20]; 6821 u8 match_dw_4[0x20]; 6822 u8 match_dw_3[0x20]; 6823 u8 match_dw_2[0x20]; 6824 u8 match_dw_1[0x20]; 6825 u8 match_dw_0[0x20]; 6826 6827 u8 match_byte_7[0x8]; 6828 u8 match_byte_6[0x8]; 6829 u8 match_byte_5[0x8]; 6830 u8 match_byte_4[0x8]; 6831 6832 u8 match_byte_3[0x8]; 6833 u8 match_byte_2[0x8]; 6834 u8 match_byte_1[0x8]; 6835 u8 match_byte_0[0x8]; 6836 }; 6837 6838 struct mlx5_ifc_match_definer_bits { 6839 u8 modify_field_select[0x40]; 6840 6841 u8 reserved_at_40[0x40]; 6842 6843 u8 reserved_at_80[0x10]; 6844 u8 format_id[0x10]; 6845 6846 u8 reserved_at_a0[0x60]; 6847 6848 u8 format_select_dw3[0x8]; 6849 u8 format_select_dw2[0x8]; 6850 u8 format_select_dw1[0x8]; 6851 u8 format_select_dw0[0x8]; 6852 6853 u8 format_select_dw7[0x8]; 6854 u8 format_select_dw6[0x8]; 6855 u8 format_select_dw5[0x8]; 6856 u8 format_select_dw4[0x8]; 6857 6858 u8 reserved_at_100[0x18]; 6859 u8 format_select_dw8[0x8]; 6860 6861 u8 reserved_at_120[0x20]; 6862 6863 u8 format_select_byte3[0x8]; 6864 u8 format_select_byte2[0x8]; 6865 u8 format_select_byte1[0x8]; 6866 u8 format_select_byte0[0x8]; 6867 6868 u8 format_select_byte7[0x8]; 6869 u8 format_select_byte6[0x8]; 6870 u8 format_select_byte5[0x8]; 6871 u8 format_select_byte4[0x8]; 6872 6873 u8 reserved_at_180[0x40]; 6874 6875 union { 6876 struct { 6877 u8 match_mask[16][0x20]; 6878 }; 6879 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6880 }; 6881 }; 6882 6883 struct mlx5_ifc_general_obj_create_param_bits { 6884 u8 alias_object[0x1]; 6885 u8 reserved_at_1[0x2]; 6886 u8 log_obj_range[0x5]; 6887 u8 reserved_at_8[0x18]; 6888 }; 6889 6890 struct mlx5_ifc_general_obj_query_param_bits { 6891 u8 alias_object[0x1]; 6892 u8 obj_offset[0x1f]; 6893 }; 6894 6895 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6896 u8 opcode[0x10]; 6897 u8 uid[0x10]; 6898 6899 u8 vhca_tunnel_id[0x10]; 6900 u8 obj_type[0x10]; 6901 6902 u8 obj_id[0x20]; 6903 6904 union { 6905 struct mlx5_ifc_general_obj_create_param_bits create; 6906 struct mlx5_ifc_general_obj_query_param_bits query; 6907 } op_param; 6908 }; 6909 6910 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 obj_id[0x20]; 6917 6918 u8 reserved_at_60[0x20]; 6919 }; 6920 6921 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6922 u8 opcode[0x10]; 6923 u8 uid[0x10]; 6924 u8 reserved_at_20[0x10]; 6925 u8 op_mod[0x10]; 6926 u8 reserved_at_40[0x50]; 6927 u8 object_type_to_be_accessed[0x10]; 6928 u8 object_id_to_be_accessed[0x20]; 6929 u8 reserved_at_c0[0x40]; 6930 union { 6931 u8 access_key_raw[0x100]; 6932 u8 access_key[8][0x20]; 6933 }; 6934 }; 6935 6936 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6937 u8 status[0x8]; 6938 u8 reserved_at_8[0x18]; 6939 u8 syndrome[0x20]; 6940 u8 reserved_at_40[0x40]; 6941 }; 6942 6943 struct mlx5_ifc_modify_header_arg_bits { 6944 u8 reserved_at_0[0x80]; 6945 6946 u8 reserved_at_80[0x8]; 6947 u8 access_pd[0x18]; 6948 }; 6949 6950 struct mlx5_ifc_create_modify_header_arg_in_bits { 6951 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6952 struct mlx5_ifc_modify_header_arg_bits arg; 6953 }; 6954 6955 struct mlx5_ifc_create_match_definer_in_bits { 6956 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6957 6958 struct mlx5_ifc_match_definer_bits obj_context; 6959 }; 6960 6961 struct mlx5_ifc_create_match_definer_out_bits { 6962 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6963 }; 6964 6965 struct mlx5_ifc_alias_context_bits { 6966 u8 vhca_id_to_be_accessed[0x10]; 6967 u8 reserved_at_10[0xb]; 6968 u8 vhca_id_type[0x1]; 6969 u8 reserved_at_1c[0x1]; 6970 u8 status[0x3]; 6971 u8 object_id_to_be_accessed[0x20]; 6972 u8 reserved_at_40[0x40]; 6973 union { 6974 u8 access_key_raw[0x100]; 6975 u8 access_key[8][0x20]; 6976 }; 6977 u8 metadata[0x80]; 6978 }; 6979 6980 struct mlx5_ifc_create_alias_obj_in_bits { 6981 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6982 struct mlx5_ifc_alias_context_bits alias_ctx; 6983 }; 6984 6985 enum { 6986 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6987 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6988 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6989 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6990 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6991 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6992 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6993 }; 6994 6995 struct mlx5_ifc_query_flow_group_out_bits { 6996 u8 status[0x8]; 6997 u8 reserved_at_8[0x18]; 6998 6999 u8 syndrome[0x20]; 7000 7001 u8 reserved_at_40[0xa0]; 7002 7003 u8 start_flow_index[0x20]; 7004 7005 u8 reserved_at_100[0x20]; 7006 7007 u8 end_flow_index[0x20]; 7008 7009 u8 reserved_at_140[0xa0]; 7010 7011 u8 reserved_at_1e0[0x18]; 7012 u8 match_criteria_enable[0x8]; 7013 7014 struct mlx5_ifc_fte_match_param_bits match_criteria; 7015 7016 u8 reserved_at_1200[0xe00]; 7017 }; 7018 7019 struct mlx5_ifc_query_flow_group_in_bits { 7020 u8 opcode[0x10]; 7021 u8 reserved_at_10[0x10]; 7022 7023 u8 reserved_at_20[0x10]; 7024 u8 op_mod[0x10]; 7025 7026 u8 reserved_at_40[0x40]; 7027 7028 u8 table_type[0x8]; 7029 u8 reserved_at_88[0x18]; 7030 7031 u8 reserved_at_a0[0x8]; 7032 u8 table_id[0x18]; 7033 7034 u8 group_id[0x20]; 7035 7036 u8 reserved_at_e0[0x120]; 7037 }; 7038 7039 struct mlx5_ifc_query_flow_counter_out_bits { 7040 u8 status[0x8]; 7041 u8 reserved_at_8[0x18]; 7042 7043 u8 syndrome[0x20]; 7044 7045 u8 reserved_at_40[0x40]; 7046 7047 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 7048 }; 7049 7050 struct mlx5_ifc_query_flow_counter_in_bits { 7051 u8 opcode[0x10]; 7052 u8 reserved_at_10[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 reserved_at_40[0x80]; 7058 7059 u8 clear[0x1]; 7060 u8 reserved_at_c1[0xf]; 7061 u8 num_of_counters[0x10]; 7062 7063 u8 flow_counter_id[0x20]; 7064 }; 7065 7066 struct mlx5_ifc_query_esw_vport_context_out_bits { 7067 u8 status[0x8]; 7068 u8 reserved_at_8[0x18]; 7069 7070 u8 syndrome[0x20]; 7071 7072 u8 reserved_at_40[0x40]; 7073 7074 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7075 }; 7076 7077 struct mlx5_ifc_query_esw_vport_context_in_bits { 7078 u8 opcode[0x10]; 7079 u8 reserved_at_10[0x10]; 7080 7081 u8 reserved_at_20[0x10]; 7082 u8 op_mod[0x10]; 7083 7084 u8 other_vport[0x1]; 7085 u8 reserved_at_41[0xf]; 7086 u8 vport_number[0x10]; 7087 7088 u8 reserved_at_60[0x20]; 7089 }; 7090 7091 struct mlx5_ifc_destroy_esw_vport_out_bits { 7092 u8 status[0x8]; 7093 u8 reserved_at_8[0x18]; 7094 7095 u8 syndrome[0x20]; 7096 7097 u8 reserved_at_40[0x20]; 7098 }; 7099 7100 struct mlx5_ifc_destroy_esw_vport_in_bits { 7101 u8 opcode[0x10]; 7102 u8 uid[0x10]; 7103 7104 u8 reserved_at_20[0x10]; 7105 u8 op_mod[0x10]; 7106 7107 u8 reserved_at_40[0x10]; 7108 u8 vport_num[0x10]; 7109 7110 u8 reserved_at_60[0x20]; 7111 }; 7112 7113 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 reserved_at_40[0x40]; 7120 }; 7121 7122 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7123 u8 reserved_at_0[0x1b]; 7124 u8 fdb_to_vport_reg_c_id[0x1]; 7125 u8 vport_cvlan_insert[0x1]; 7126 u8 vport_svlan_insert[0x1]; 7127 u8 vport_cvlan_strip[0x1]; 7128 u8 vport_svlan_strip[0x1]; 7129 }; 7130 7131 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7132 u8 opcode[0x10]; 7133 u8 reserved_at_10[0x10]; 7134 7135 u8 reserved_at_20[0x10]; 7136 u8 op_mod[0x10]; 7137 7138 u8 other_vport[0x1]; 7139 u8 reserved_at_41[0xf]; 7140 u8 vport_number[0x10]; 7141 7142 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7143 7144 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7145 }; 7146 7147 struct mlx5_ifc_query_eq_out_bits { 7148 u8 status[0x8]; 7149 u8 reserved_at_8[0x18]; 7150 7151 u8 syndrome[0x20]; 7152 7153 u8 reserved_at_40[0x40]; 7154 7155 struct mlx5_ifc_eqc_bits eq_context_entry; 7156 7157 u8 reserved_at_280[0x40]; 7158 7159 u8 event_bitmask[0x40]; 7160 7161 u8 reserved_at_300[0x580]; 7162 7163 u8 pas[][0x40]; 7164 }; 7165 7166 struct mlx5_ifc_query_eq_in_bits { 7167 u8 opcode[0x10]; 7168 u8 reserved_at_10[0x10]; 7169 7170 u8 reserved_at_20[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 reserved_at_40[0x18]; 7174 u8 eq_number[0x8]; 7175 7176 u8 reserved_at_60[0x20]; 7177 }; 7178 7179 struct mlx5_ifc_packet_reformat_context_in_bits { 7180 u8 reformat_type[0x8]; 7181 u8 reserved_at_8[0x4]; 7182 u8 reformat_param_0[0x4]; 7183 u8 reserved_at_10[0x6]; 7184 u8 reformat_data_size[0xa]; 7185 7186 u8 reformat_param_1[0x8]; 7187 u8 reserved_at_28[0x8]; 7188 u8 reformat_data[2][0x8]; 7189 7190 u8 more_reformat_data[][0x8]; 7191 }; 7192 7193 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7194 u8 status[0x8]; 7195 u8 reserved_at_8[0x18]; 7196 7197 u8 syndrome[0x20]; 7198 7199 u8 reserved_at_40[0xa0]; 7200 7201 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7202 }; 7203 7204 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7205 u8 opcode[0x10]; 7206 u8 reserved_at_10[0x10]; 7207 7208 u8 reserved_at_20[0x10]; 7209 u8 op_mod[0x10]; 7210 7211 u8 packet_reformat_id[0x20]; 7212 7213 u8 reserved_at_60[0xa0]; 7214 }; 7215 7216 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7217 u8 status[0x8]; 7218 u8 reserved_at_8[0x18]; 7219 7220 u8 syndrome[0x20]; 7221 7222 u8 packet_reformat_id[0x20]; 7223 7224 u8 reserved_at_60[0x20]; 7225 }; 7226 7227 enum { 7228 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7229 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7230 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7231 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7232 }; 7233 7234 enum mlx5_reformat_ctx_type { 7235 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7236 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7237 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7238 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7239 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7240 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7241 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7242 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7243 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7244 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7245 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7246 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7247 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7248 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7249 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7250 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7251 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7252 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7253 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7254 }; 7255 7256 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7257 u8 opcode[0x10]; 7258 u8 reserved_at_10[0x10]; 7259 7260 u8 reserved_at_20[0x10]; 7261 u8 op_mod[0x10]; 7262 7263 u8 reserved_at_40[0xa0]; 7264 7265 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7266 }; 7267 7268 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7269 u8 status[0x8]; 7270 u8 reserved_at_8[0x18]; 7271 7272 u8 syndrome[0x20]; 7273 7274 u8 reserved_at_40[0x40]; 7275 }; 7276 7277 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7278 u8 opcode[0x10]; 7279 u8 reserved_at_10[0x10]; 7280 7281 u8 reserved_20[0x10]; 7282 u8 op_mod[0x10]; 7283 7284 u8 packet_reformat_id[0x20]; 7285 7286 u8 reserved_60[0x20]; 7287 }; 7288 7289 struct mlx5_ifc_set_action_in_bits { 7290 u8 action_type[0x4]; 7291 u8 field[0xc]; 7292 u8 reserved_at_10[0x3]; 7293 u8 offset[0x5]; 7294 u8 reserved_at_18[0x3]; 7295 u8 length[0x5]; 7296 7297 u8 data[0x20]; 7298 }; 7299 7300 struct mlx5_ifc_add_action_in_bits { 7301 u8 action_type[0x4]; 7302 u8 field[0xc]; 7303 u8 reserved_at_10[0x10]; 7304 7305 u8 data[0x20]; 7306 }; 7307 7308 struct mlx5_ifc_copy_action_in_bits { 7309 u8 action_type[0x4]; 7310 u8 src_field[0xc]; 7311 u8 reserved_at_10[0x3]; 7312 u8 src_offset[0x5]; 7313 u8 reserved_at_18[0x3]; 7314 u8 length[0x5]; 7315 7316 u8 reserved_at_20[0x4]; 7317 u8 dst_field[0xc]; 7318 u8 reserved_at_30[0x3]; 7319 u8 dst_offset[0x5]; 7320 u8 reserved_at_38[0x8]; 7321 }; 7322 7323 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7324 struct mlx5_ifc_set_action_in_bits set_action_in; 7325 struct mlx5_ifc_add_action_in_bits add_action_in; 7326 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7327 u8 reserved_at_0[0x40]; 7328 }; 7329 7330 enum { 7331 MLX5_ACTION_TYPE_SET = 0x1, 7332 MLX5_ACTION_TYPE_ADD = 0x2, 7333 MLX5_ACTION_TYPE_COPY = 0x3, 7334 }; 7335 7336 enum { 7337 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7338 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7339 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7340 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7341 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7342 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7343 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7344 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7345 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7346 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7347 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7348 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7349 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7350 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7351 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7352 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7353 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7354 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7355 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7356 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7357 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7358 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7359 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7360 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7361 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7362 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7363 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7364 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7365 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7366 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7367 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7368 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7369 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7370 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7371 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7372 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7373 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7374 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7375 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7376 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7377 }; 7378 7379 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7380 u8 status[0x8]; 7381 u8 reserved_at_8[0x18]; 7382 7383 u8 syndrome[0x20]; 7384 7385 u8 modify_header_id[0x20]; 7386 7387 u8 reserved_at_60[0x20]; 7388 }; 7389 7390 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7391 u8 opcode[0x10]; 7392 u8 reserved_at_10[0x10]; 7393 7394 u8 reserved_at_20[0x10]; 7395 u8 op_mod[0x10]; 7396 7397 u8 reserved_at_40[0x20]; 7398 7399 u8 table_type[0x8]; 7400 u8 reserved_at_68[0x10]; 7401 u8 num_of_actions[0x8]; 7402 7403 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7404 }; 7405 7406 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_at_8[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_at_40[0x40]; 7413 }; 7414 7415 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7416 u8 opcode[0x10]; 7417 u8 reserved_at_10[0x10]; 7418 7419 u8 reserved_at_20[0x10]; 7420 u8 op_mod[0x10]; 7421 7422 u8 modify_header_id[0x20]; 7423 7424 u8 reserved_at_60[0x20]; 7425 }; 7426 7427 struct mlx5_ifc_query_modify_header_context_in_bits { 7428 u8 opcode[0x10]; 7429 u8 uid[0x10]; 7430 7431 u8 reserved_at_20[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 modify_header_id[0x20]; 7435 7436 u8 reserved_at_60[0xa0]; 7437 }; 7438 7439 struct mlx5_ifc_query_dct_out_bits { 7440 u8 status[0x8]; 7441 u8 reserved_at_8[0x18]; 7442 7443 u8 syndrome[0x20]; 7444 7445 u8 reserved_at_40[0x40]; 7446 7447 struct mlx5_ifc_dctc_bits dct_context_entry; 7448 7449 u8 reserved_at_280[0x180]; 7450 }; 7451 7452 struct mlx5_ifc_query_dct_in_bits { 7453 u8 opcode[0x10]; 7454 u8 reserved_at_10[0x10]; 7455 7456 u8 reserved_at_20[0x10]; 7457 u8 op_mod[0x10]; 7458 7459 u8 reserved_at_40[0x8]; 7460 u8 dctn[0x18]; 7461 7462 u8 reserved_at_60[0x20]; 7463 }; 7464 7465 struct mlx5_ifc_query_cq_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_at_8[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_at_40[0x40]; 7472 7473 struct mlx5_ifc_cqc_bits cq_context; 7474 7475 u8 reserved_at_280[0x600]; 7476 7477 u8 pas[][0x40]; 7478 }; 7479 7480 struct mlx5_ifc_query_cq_in_bits { 7481 u8 opcode[0x10]; 7482 u8 reserved_at_10[0x10]; 7483 7484 u8 reserved_at_20[0x10]; 7485 u8 op_mod[0x10]; 7486 7487 u8 reserved_at_40[0x8]; 7488 u8 cqn[0x18]; 7489 7490 u8 reserved_at_60[0x20]; 7491 }; 7492 7493 struct mlx5_ifc_query_cong_status_out_bits { 7494 u8 status[0x8]; 7495 u8 reserved_at_8[0x18]; 7496 7497 u8 syndrome[0x20]; 7498 7499 u8 reserved_at_40[0x20]; 7500 7501 u8 enable[0x1]; 7502 u8 tag_enable[0x1]; 7503 u8 reserved_at_62[0x1e]; 7504 }; 7505 7506 struct mlx5_ifc_query_cong_status_in_bits { 7507 u8 opcode[0x10]; 7508 u8 reserved_at_10[0x10]; 7509 7510 u8 reserved_at_20[0x10]; 7511 u8 op_mod[0x10]; 7512 7513 u8 reserved_at_40[0x18]; 7514 u8 priority[0x4]; 7515 u8 cong_protocol[0x4]; 7516 7517 u8 reserved_at_60[0x20]; 7518 }; 7519 7520 struct mlx5_ifc_query_cong_statistics_out_bits { 7521 u8 status[0x8]; 7522 u8 reserved_at_8[0x18]; 7523 7524 u8 syndrome[0x20]; 7525 7526 u8 reserved_at_40[0x40]; 7527 7528 u8 rp_cur_flows[0x20]; 7529 7530 u8 sum_flows[0x20]; 7531 7532 u8 rp_cnp_ignored_high[0x20]; 7533 7534 u8 rp_cnp_ignored_low[0x20]; 7535 7536 u8 rp_cnp_handled_high[0x20]; 7537 7538 u8 rp_cnp_handled_low[0x20]; 7539 7540 u8 reserved_at_140[0x100]; 7541 7542 u8 time_stamp_high[0x20]; 7543 7544 u8 time_stamp_low[0x20]; 7545 7546 u8 accumulators_period[0x20]; 7547 7548 u8 np_ecn_marked_roce_packets_high[0x20]; 7549 7550 u8 np_ecn_marked_roce_packets_low[0x20]; 7551 7552 u8 np_cnp_sent_high[0x20]; 7553 7554 u8 np_cnp_sent_low[0x20]; 7555 7556 u8 reserved_at_320[0x560]; 7557 }; 7558 7559 struct mlx5_ifc_query_cong_statistics_in_bits { 7560 u8 opcode[0x10]; 7561 u8 reserved_at_10[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 clear[0x1]; 7567 u8 reserved_at_41[0x1f]; 7568 7569 u8 reserved_at_60[0x20]; 7570 }; 7571 7572 struct mlx5_ifc_query_cong_params_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x40]; 7579 7580 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7581 }; 7582 7583 struct mlx5_ifc_query_cong_params_in_bits { 7584 u8 opcode[0x10]; 7585 u8 reserved_at_10[0x10]; 7586 7587 u8 reserved_at_20[0x10]; 7588 u8 op_mod[0x10]; 7589 7590 u8 reserved_at_40[0x1c]; 7591 u8 cong_protocol[0x4]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_query_adapter_out_bits { 7597 u8 status[0x8]; 7598 u8 reserved_at_8[0x18]; 7599 7600 u8 syndrome[0x20]; 7601 7602 u8 reserved_at_40[0x40]; 7603 7604 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7605 }; 7606 7607 struct mlx5_ifc_query_adapter_in_bits { 7608 u8 opcode[0x10]; 7609 u8 reserved_at_10[0x10]; 7610 7611 u8 reserved_at_20[0x10]; 7612 u8 op_mod[0x10]; 7613 7614 u8 reserved_at_40[0x40]; 7615 }; 7616 7617 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7618 u8 host_number[0x8]; 7619 u8 host_pci_device_function[0x8]; 7620 u8 host_pci_bus[0x8]; 7621 u8 reserved_at_18[0x3]; 7622 u8 pci_bus_assigned[0x1]; 7623 u8 function_type[0x4]; 7624 7625 u8 parent_pci_device_function[0x8]; 7626 u8 parent_pci_bus[0x8]; 7627 u8 vhca_id[0x10]; 7628 7629 u8 reserved_at_40[0x10]; 7630 u8 function_id[0x10]; 7631 7632 u8 reserved_at_60[0x20]; 7633 }; 7634 7635 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7636 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7637 7638 u8 reserved_at_80[0x18]; 7639 u8 manage_profile[0x8]; 7640 7641 u8 reserved_at_a0[0x60]; 7642 }; 7643 7644 struct mlx5_ifc_query_delegated_vhca_out_bits { 7645 u8 status[0x8]; 7646 u8 reserved_at_8[0x18]; 7647 7648 u8 syndrome[0x20]; 7649 7650 u8 reserved_at_40[0x20]; 7651 7652 u8 reserved_at_60[0x10]; 7653 u8 functions_count[0x10]; 7654 7655 u8 reserved_at_80[0x80]; 7656 7657 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7658 delegated_function_vhca_rid_info[]; 7659 }; 7660 7661 struct mlx5_ifc_query_delegated_vhca_in_bits { 7662 u8 opcode[0x10]; 7663 u8 uid[0x10]; 7664 7665 u8 reserved_at_20[0x10]; 7666 u8 op_mod[0x10]; 7667 7668 u8 reserved_at_40[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_create_esw_vport_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x20]; 7678 7679 u8 reserved_at_60[0x10]; 7680 u8 vport_num[0x10]; 7681 }; 7682 7683 struct mlx5_ifc_create_esw_vport_in_bits { 7684 u8 opcode[0x10]; 7685 u8 reserved_at_10[0x10]; 7686 7687 u8 reserved_at_20[0x10]; 7688 u8 op_mod[0x10]; 7689 7690 u8 reserved_at_40[0x10]; 7691 u8 managed_vhca_id[0x10]; 7692 7693 u8 reserved_at_60[0x20]; 7694 }; 7695 7696 struct mlx5_ifc_qp_2rst_out_bits { 7697 u8 status[0x8]; 7698 u8 reserved_at_8[0x18]; 7699 7700 u8 syndrome[0x20]; 7701 7702 u8 reserved_at_40[0x40]; 7703 }; 7704 7705 struct mlx5_ifc_qp_2rst_in_bits { 7706 u8 opcode[0x10]; 7707 u8 uid[0x10]; 7708 7709 u8 reserved_at_20[0x10]; 7710 u8 op_mod[0x10]; 7711 7712 u8 reserved_at_40[0x8]; 7713 u8 qpn[0x18]; 7714 7715 u8 reserved_at_60[0x20]; 7716 }; 7717 7718 struct mlx5_ifc_qp_2err_out_bits { 7719 u8 status[0x8]; 7720 u8 reserved_at_8[0x18]; 7721 7722 u8 syndrome[0x20]; 7723 7724 u8 reserved_at_40[0x40]; 7725 }; 7726 7727 struct mlx5_ifc_qp_2err_in_bits { 7728 u8 opcode[0x10]; 7729 u8 uid[0x10]; 7730 7731 u8 reserved_at_20[0x10]; 7732 u8 op_mod[0x10]; 7733 7734 u8 reserved_at_40[0x8]; 7735 u8 qpn[0x18]; 7736 7737 u8 reserved_at_60[0x20]; 7738 }; 7739 7740 struct mlx5_ifc_trans_page_fault_info_bits { 7741 u8 error[0x1]; 7742 u8 reserved_at_1[0x4]; 7743 u8 page_fault_type[0x3]; 7744 u8 wq_number[0x18]; 7745 7746 u8 reserved_at_20[0x8]; 7747 u8 fault_token[0x18]; 7748 }; 7749 7750 struct mlx5_ifc_mem_page_fault_info_bits { 7751 u8 error[0x1]; 7752 u8 reserved_at_1[0xf]; 7753 u8 fault_token_47_32[0x10]; 7754 7755 u8 fault_token_31_0[0x20]; 7756 }; 7757 7758 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7759 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7760 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7761 u8 reserved_at_0[0x40]; 7762 }; 7763 7764 struct mlx5_ifc_page_fault_resume_out_bits { 7765 u8 status[0x8]; 7766 u8 reserved_at_8[0x18]; 7767 7768 u8 syndrome[0x20]; 7769 7770 u8 reserved_at_40[0x40]; 7771 }; 7772 7773 struct mlx5_ifc_page_fault_resume_in_bits { 7774 u8 opcode[0x10]; 7775 u8 reserved_at_10[0x10]; 7776 7777 u8 reserved_at_20[0x10]; 7778 u8 op_mod[0x10]; 7779 7780 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7781 page_fault_info; 7782 }; 7783 7784 struct mlx5_ifc_nop_out_bits { 7785 u8 status[0x8]; 7786 u8 reserved_at_8[0x18]; 7787 7788 u8 syndrome[0x20]; 7789 7790 u8 reserved_at_40[0x40]; 7791 }; 7792 7793 struct mlx5_ifc_nop_in_bits { 7794 u8 opcode[0x10]; 7795 u8 reserved_at_10[0x10]; 7796 7797 u8 reserved_at_20[0x10]; 7798 u8 op_mod[0x10]; 7799 7800 u8 reserved_at_40[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_modify_vport_state_out_bits { 7804 u8 status[0x8]; 7805 u8 reserved_at_8[0x18]; 7806 7807 u8 syndrome[0x20]; 7808 7809 u8 reserved_at_40[0x40]; 7810 }; 7811 7812 struct mlx5_ifc_modify_vport_state_in_bits { 7813 u8 opcode[0x10]; 7814 u8 reserved_at_10[0x10]; 7815 7816 u8 reserved_at_20[0x10]; 7817 u8 op_mod[0x10]; 7818 7819 u8 other_vport[0x1]; 7820 u8 reserved_at_41[0xf]; 7821 u8 vport_number[0x10]; 7822 7823 u8 max_tx_speed[0x10]; 7824 u8 ingress_connect[0x1]; 7825 u8 egress_connect[0x1]; 7826 u8 ingress_connect_valid[0x1]; 7827 u8 egress_connect_valid[0x1]; 7828 u8 reserved_at_74[0x4]; 7829 u8 admin_state[0x4]; 7830 u8 reserved_at_7c[0x4]; 7831 }; 7832 7833 struct mlx5_ifc_modify_tis_out_bits { 7834 u8 status[0x8]; 7835 u8 reserved_at_8[0x18]; 7836 7837 u8 syndrome[0x20]; 7838 7839 u8 reserved_at_40[0x40]; 7840 }; 7841 7842 struct mlx5_ifc_modify_tis_bitmask_bits { 7843 u8 reserved_at_0[0x20]; 7844 7845 u8 reserved_at_20[0x1d]; 7846 u8 lag_tx_port_affinity[0x1]; 7847 u8 strict_lag_tx_port_affinity[0x1]; 7848 u8 prio[0x1]; 7849 }; 7850 7851 struct mlx5_ifc_modify_tis_in_bits { 7852 u8 opcode[0x10]; 7853 u8 uid[0x10]; 7854 7855 u8 reserved_at_20[0x10]; 7856 u8 op_mod[0x10]; 7857 7858 u8 reserved_at_40[0x8]; 7859 u8 tisn[0x18]; 7860 7861 u8 reserved_at_60[0x20]; 7862 7863 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7864 7865 u8 reserved_at_c0[0x40]; 7866 7867 struct mlx5_ifc_tisc_bits ctx; 7868 }; 7869 7870 struct mlx5_ifc_modify_tir_bitmask_bits { 7871 u8 reserved_at_0[0x20]; 7872 7873 u8 reserved_at_20[0x1b]; 7874 u8 self_lb_en[0x1]; 7875 u8 reserved_at_3c[0x1]; 7876 u8 hash[0x1]; 7877 u8 reserved_at_3e[0x1]; 7878 u8 packet_merge[0x1]; 7879 }; 7880 7881 struct mlx5_ifc_modify_tir_out_bits { 7882 u8 status[0x8]; 7883 u8 reserved_at_8[0x18]; 7884 7885 u8 syndrome[0x20]; 7886 7887 u8 reserved_at_40[0x40]; 7888 }; 7889 7890 struct mlx5_ifc_modify_tir_in_bits { 7891 u8 opcode[0x10]; 7892 u8 uid[0x10]; 7893 7894 u8 reserved_at_20[0x10]; 7895 u8 op_mod[0x10]; 7896 7897 u8 reserved_at_40[0x8]; 7898 u8 tirn[0x18]; 7899 7900 u8 reserved_at_60[0x20]; 7901 7902 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7903 7904 u8 reserved_at_c0[0x40]; 7905 7906 struct mlx5_ifc_tirc_bits ctx; 7907 }; 7908 7909 struct mlx5_ifc_modify_sq_out_bits { 7910 u8 status[0x8]; 7911 u8 reserved_at_8[0x18]; 7912 7913 u8 syndrome[0x20]; 7914 7915 u8 reserved_at_40[0x40]; 7916 }; 7917 7918 struct mlx5_ifc_modify_sq_in_bits { 7919 u8 opcode[0x10]; 7920 u8 uid[0x10]; 7921 7922 u8 reserved_at_20[0x10]; 7923 u8 op_mod[0x10]; 7924 7925 u8 sq_state[0x4]; 7926 u8 reserved_at_44[0x4]; 7927 u8 sqn[0x18]; 7928 7929 u8 reserved_at_60[0x20]; 7930 7931 u8 modify_bitmask[0x40]; 7932 7933 u8 reserved_at_c0[0x40]; 7934 7935 struct mlx5_ifc_sqc_bits ctx; 7936 }; 7937 7938 struct mlx5_ifc_modify_scheduling_element_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x1c0]; 7945 }; 7946 7947 enum { 7948 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7949 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7950 }; 7951 7952 struct mlx5_ifc_modify_scheduling_element_in_bits { 7953 u8 opcode[0x10]; 7954 u8 reserved_at_10[0x10]; 7955 7956 u8 reserved_at_20[0x10]; 7957 u8 op_mod[0x10]; 7958 7959 u8 scheduling_hierarchy[0x8]; 7960 u8 reserved_at_48[0x18]; 7961 7962 u8 scheduling_element_id[0x20]; 7963 7964 u8 reserved_at_80[0x20]; 7965 7966 u8 modify_bitmask[0x20]; 7967 7968 u8 reserved_at_c0[0x40]; 7969 7970 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7971 7972 u8 reserved_at_300[0x100]; 7973 }; 7974 7975 struct mlx5_ifc_modify_rqt_out_bits { 7976 u8 status[0x8]; 7977 u8 reserved_at_8[0x18]; 7978 7979 u8 syndrome[0x20]; 7980 7981 u8 reserved_at_40[0x40]; 7982 }; 7983 7984 struct mlx5_ifc_rqt_bitmask_bits { 7985 u8 reserved_at_0[0x20]; 7986 7987 u8 reserved_at_20[0x1f]; 7988 u8 rqn_list[0x1]; 7989 }; 7990 7991 struct mlx5_ifc_modify_rqt_in_bits { 7992 u8 opcode[0x10]; 7993 u8 uid[0x10]; 7994 7995 u8 reserved_at_20[0x10]; 7996 u8 op_mod[0x10]; 7997 7998 u8 reserved_at_40[0x8]; 7999 u8 rqtn[0x18]; 8000 8001 u8 reserved_at_60[0x20]; 8002 8003 struct mlx5_ifc_rqt_bitmask_bits bitmask; 8004 8005 u8 reserved_at_c0[0x40]; 8006 8007 struct mlx5_ifc_rqtc_bits ctx; 8008 }; 8009 8010 struct mlx5_ifc_modify_rq_out_bits { 8011 u8 status[0x8]; 8012 u8 reserved_at_8[0x18]; 8013 8014 u8 syndrome[0x20]; 8015 8016 u8 reserved_at_40[0x40]; 8017 }; 8018 8019 enum { 8020 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 8021 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 8022 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 8023 }; 8024 8025 struct mlx5_ifc_modify_rq_in_bits { 8026 u8 opcode[0x10]; 8027 u8 uid[0x10]; 8028 8029 u8 reserved_at_20[0x10]; 8030 u8 op_mod[0x10]; 8031 8032 u8 rq_state[0x4]; 8033 u8 reserved_at_44[0x4]; 8034 u8 rqn[0x18]; 8035 8036 u8 reserved_at_60[0x20]; 8037 8038 u8 modify_bitmask[0x40]; 8039 8040 u8 reserved_at_c0[0x40]; 8041 8042 struct mlx5_ifc_rqc_bits ctx; 8043 }; 8044 8045 struct mlx5_ifc_modify_rmp_out_bits { 8046 u8 status[0x8]; 8047 u8 reserved_at_8[0x18]; 8048 8049 u8 syndrome[0x20]; 8050 8051 u8 reserved_at_40[0x40]; 8052 }; 8053 8054 struct mlx5_ifc_rmp_bitmask_bits { 8055 u8 reserved_at_0[0x20]; 8056 8057 u8 reserved_at_20[0x1f]; 8058 u8 lwm[0x1]; 8059 }; 8060 8061 struct mlx5_ifc_modify_rmp_in_bits { 8062 u8 opcode[0x10]; 8063 u8 uid[0x10]; 8064 8065 u8 reserved_at_20[0x10]; 8066 u8 op_mod[0x10]; 8067 8068 u8 rmp_state[0x4]; 8069 u8 reserved_at_44[0x4]; 8070 u8 rmpn[0x18]; 8071 8072 u8 reserved_at_60[0x20]; 8073 8074 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8075 8076 u8 reserved_at_c0[0x40]; 8077 8078 struct mlx5_ifc_rmpc_bits ctx; 8079 }; 8080 8081 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8082 u8 status[0x8]; 8083 u8 reserved_at_8[0x18]; 8084 8085 u8 syndrome[0x20]; 8086 8087 u8 reserved_at_40[0x40]; 8088 }; 8089 8090 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8091 u8 reserved_at_0[0x12]; 8092 u8 affiliation[0x1]; 8093 u8 reserved_at_13[0x1]; 8094 u8 disable_uc_local_lb[0x1]; 8095 u8 disable_mc_local_lb[0x1]; 8096 u8 node_guid[0x1]; 8097 u8 port_guid[0x1]; 8098 u8 min_inline[0x1]; 8099 u8 mtu[0x1]; 8100 u8 change_event[0x1]; 8101 u8 promisc[0x1]; 8102 u8 permanent_address[0x1]; 8103 u8 addresses_list[0x1]; 8104 u8 roce_en[0x1]; 8105 u8 reserved_at_1f[0x1]; 8106 }; 8107 8108 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8109 u8 opcode[0x10]; 8110 u8 reserved_at_10[0x10]; 8111 8112 u8 reserved_at_20[0x10]; 8113 u8 op_mod[0x10]; 8114 8115 u8 other_vport[0x1]; 8116 u8 reserved_at_41[0xf]; 8117 u8 vport_number[0x10]; 8118 8119 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8120 8121 u8 reserved_at_80[0x780]; 8122 8123 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8124 }; 8125 8126 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8127 u8 status[0x8]; 8128 u8 reserved_at_8[0x18]; 8129 8130 u8 syndrome[0x20]; 8131 8132 u8 reserved_at_40[0x40]; 8133 }; 8134 8135 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8136 u8 opcode[0x10]; 8137 u8 reserved_at_10[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 other_vport[0x1]; 8143 u8 reserved_at_41[0xb]; 8144 u8 port_num[0x4]; 8145 u8 vport_number[0x10]; 8146 8147 u8 reserved_at_60[0x20]; 8148 8149 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8150 }; 8151 8152 struct mlx5_ifc_modify_cq_out_bits { 8153 u8 status[0x8]; 8154 u8 reserved_at_8[0x18]; 8155 8156 u8 syndrome[0x20]; 8157 8158 u8 reserved_at_40[0x40]; 8159 }; 8160 8161 enum { 8162 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8163 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8164 }; 8165 8166 struct mlx5_ifc_modify_cq_in_bits { 8167 u8 opcode[0x10]; 8168 u8 uid[0x10]; 8169 8170 u8 reserved_at_20[0x10]; 8171 u8 op_mod[0x10]; 8172 8173 u8 reserved_at_40[0x8]; 8174 u8 cqn[0x18]; 8175 8176 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8177 8178 struct mlx5_ifc_cqc_bits cq_context; 8179 8180 u8 reserved_at_280[0x60]; 8181 8182 u8 cq_umem_valid[0x1]; 8183 u8 reserved_at_2e1[0x1f]; 8184 8185 u8 reserved_at_300[0x580]; 8186 8187 u8 pas[][0x40]; 8188 }; 8189 8190 struct mlx5_ifc_modify_cong_status_out_bits { 8191 u8 status[0x8]; 8192 u8 reserved_at_8[0x18]; 8193 8194 u8 syndrome[0x20]; 8195 8196 u8 reserved_at_40[0x40]; 8197 }; 8198 8199 struct mlx5_ifc_modify_cong_status_in_bits { 8200 u8 opcode[0x10]; 8201 u8 reserved_at_10[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x18]; 8207 u8 priority[0x4]; 8208 u8 cong_protocol[0x4]; 8209 8210 u8 enable[0x1]; 8211 u8 tag_enable[0x1]; 8212 u8 reserved_at_62[0x1e]; 8213 }; 8214 8215 struct mlx5_ifc_modify_cong_params_out_bits { 8216 u8 status[0x8]; 8217 u8 reserved_at_8[0x18]; 8218 8219 u8 syndrome[0x20]; 8220 8221 u8 reserved_at_40[0x40]; 8222 }; 8223 8224 struct mlx5_ifc_modify_cong_params_in_bits { 8225 u8 opcode[0x10]; 8226 u8 reserved_at_10[0x10]; 8227 8228 u8 reserved_at_20[0x10]; 8229 u8 op_mod[0x10]; 8230 8231 u8 reserved_at_40[0x1c]; 8232 u8 cong_protocol[0x4]; 8233 8234 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8235 8236 u8 reserved_at_80[0x80]; 8237 8238 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8239 }; 8240 8241 struct mlx5_ifc_manage_pages_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 output_num_entries[0x20]; 8248 8249 u8 reserved_at_60[0x20]; 8250 8251 u8 pas[][0x40]; 8252 }; 8253 8254 enum { 8255 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8256 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8257 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8258 }; 8259 8260 struct mlx5_ifc_manage_pages_in_bits { 8261 u8 opcode[0x10]; 8262 u8 reserved_at_10[0x10]; 8263 8264 u8 reserved_at_20[0x10]; 8265 u8 op_mod[0x10]; 8266 8267 u8 embedded_cpu_function[0x1]; 8268 u8 reserved_at_41[0xf]; 8269 u8 function_id[0x10]; 8270 8271 u8 input_num_entries[0x20]; 8272 8273 u8 pas[][0x40]; 8274 }; 8275 8276 struct mlx5_ifc_mad_ifc_out_bits { 8277 u8 status[0x8]; 8278 u8 reserved_at_8[0x18]; 8279 8280 u8 syndrome[0x20]; 8281 8282 u8 reserved_at_40[0x40]; 8283 8284 u8 response_mad_packet[256][0x8]; 8285 }; 8286 8287 struct mlx5_ifc_mad_ifc_in_bits { 8288 u8 opcode[0x10]; 8289 u8 reserved_at_10[0x10]; 8290 8291 u8 reserved_at_20[0x10]; 8292 u8 op_mod[0x10]; 8293 8294 u8 remote_lid[0x10]; 8295 u8 plane_index[0x8]; 8296 u8 port[0x8]; 8297 8298 u8 reserved_at_60[0x20]; 8299 8300 u8 mad[256][0x8]; 8301 }; 8302 8303 struct mlx5_ifc_init_hca_out_bits { 8304 u8 status[0x8]; 8305 u8 reserved_at_8[0x18]; 8306 8307 u8 syndrome[0x20]; 8308 8309 u8 reserved_at_40[0x40]; 8310 }; 8311 8312 struct mlx5_ifc_init_hca_in_bits { 8313 u8 opcode[0x10]; 8314 u8 reserved_at_10[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 reserved_at_40[0x20]; 8320 8321 u8 reserved_at_60[0x2]; 8322 u8 sw_vhca_id[0xe]; 8323 u8 reserved_at_70[0x10]; 8324 8325 u8 sw_owner_id[4][0x20]; 8326 }; 8327 8328 struct mlx5_ifc_init2rtr_qp_out_bits { 8329 u8 status[0x8]; 8330 u8 reserved_at_8[0x18]; 8331 8332 u8 syndrome[0x20]; 8333 8334 u8 reserved_at_40[0x20]; 8335 u8 ece[0x20]; 8336 }; 8337 8338 struct mlx5_ifc_init2rtr_qp_in_bits { 8339 u8 opcode[0x10]; 8340 u8 uid[0x10]; 8341 8342 u8 reserved_at_20[0x10]; 8343 u8 op_mod[0x10]; 8344 8345 u8 reserved_at_40[0x8]; 8346 u8 qpn[0x18]; 8347 8348 u8 reserved_at_60[0x20]; 8349 8350 u8 opt_param_mask[0x20]; 8351 8352 u8 ece[0x20]; 8353 8354 struct mlx5_ifc_qpc_bits qpc; 8355 8356 u8 reserved_at_800[0x80]; 8357 }; 8358 8359 struct mlx5_ifc_init2init_qp_out_bits { 8360 u8 status[0x8]; 8361 u8 reserved_at_8[0x18]; 8362 8363 u8 syndrome[0x20]; 8364 8365 u8 reserved_at_40[0x20]; 8366 u8 ece[0x20]; 8367 }; 8368 8369 struct mlx5_ifc_init2init_qp_in_bits { 8370 u8 opcode[0x10]; 8371 u8 uid[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x8]; 8377 u8 qpn[0x18]; 8378 8379 u8 reserved_at_60[0x20]; 8380 8381 u8 opt_param_mask[0x20]; 8382 8383 u8 ece[0x20]; 8384 8385 struct mlx5_ifc_qpc_bits qpc; 8386 8387 u8 reserved_at_800[0x80]; 8388 }; 8389 8390 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8391 u8 status[0x8]; 8392 u8 reserved_at_8[0x18]; 8393 8394 u8 syndrome[0x20]; 8395 8396 u8 reserved_at_40[0x40]; 8397 8398 u8 packet_headers_log[128][0x8]; 8399 8400 u8 packet_syndrome[64][0x8]; 8401 }; 8402 8403 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8404 u8 opcode[0x10]; 8405 u8 reserved_at_10[0x10]; 8406 8407 u8 reserved_at_20[0x10]; 8408 u8 op_mod[0x10]; 8409 8410 u8 reserved_at_40[0x40]; 8411 }; 8412 8413 struct mlx5_ifc_gen_eqe_in_bits { 8414 u8 opcode[0x10]; 8415 u8 reserved_at_10[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_at_40[0x18]; 8421 u8 eq_number[0x8]; 8422 8423 u8 reserved_at_60[0x20]; 8424 8425 u8 eqe[64][0x8]; 8426 }; 8427 8428 struct mlx5_ifc_gen_eq_out_bits { 8429 u8 status[0x8]; 8430 u8 reserved_at_8[0x18]; 8431 8432 u8 syndrome[0x20]; 8433 8434 u8 reserved_at_40[0x40]; 8435 }; 8436 8437 struct mlx5_ifc_enable_hca_out_bits { 8438 u8 status[0x8]; 8439 u8 reserved_at_8[0x18]; 8440 8441 u8 syndrome[0x20]; 8442 8443 u8 reserved_at_40[0x20]; 8444 }; 8445 8446 struct mlx5_ifc_enable_hca_in_bits { 8447 u8 opcode[0x10]; 8448 u8 reserved_at_10[0x10]; 8449 8450 u8 reserved_at_20[0x10]; 8451 u8 op_mod[0x10]; 8452 8453 u8 embedded_cpu_function[0x1]; 8454 u8 reserved_at_41[0xf]; 8455 u8 function_id[0x10]; 8456 8457 u8 reserved_at_60[0x20]; 8458 }; 8459 8460 struct mlx5_ifc_drain_dct_out_bits { 8461 u8 status[0x8]; 8462 u8 reserved_at_8[0x18]; 8463 8464 u8 syndrome[0x20]; 8465 8466 u8 reserved_at_40[0x40]; 8467 }; 8468 8469 struct mlx5_ifc_drain_dct_in_bits { 8470 u8 opcode[0x10]; 8471 u8 uid[0x10]; 8472 8473 u8 reserved_at_20[0x10]; 8474 u8 op_mod[0x10]; 8475 8476 u8 reserved_at_40[0x8]; 8477 u8 dctn[0x18]; 8478 8479 u8 reserved_at_60[0x20]; 8480 }; 8481 8482 struct mlx5_ifc_disable_hca_out_bits { 8483 u8 status[0x8]; 8484 u8 reserved_at_8[0x18]; 8485 8486 u8 syndrome[0x20]; 8487 8488 u8 reserved_at_40[0x20]; 8489 }; 8490 8491 struct mlx5_ifc_disable_hca_in_bits { 8492 u8 opcode[0x10]; 8493 u8 reserved_at_10[0x10]; 8494 8495 u8 reserved_at_20[0x10]; 8496 u8 op_mod[0x10]; 8497 8498 u8 embedded_cpu_function[0x1]; 8499 u8 reserved_at_41[0xf]; 8500 u8 function_id[0x10]; 8501 8502 u8 reserved_at_60[0x20]; 8503 }; 8504 8505 struct mlx5_ifc_detach_from_mcg_out_bits { 8506 u8 status[0x8]; 8507 u8 reserved_at_8[0x18]; 8508 8509 u8 syndrome[0x20]; 8510 8511 u8 reserved_at_40[0x40]; 8512 }; 8513 8514 struct mlx5_ifc_detach_from_mcg_in_bits { 8515 u8 opcode[0x10]; 8516 u8 uid[0x10]; 8517 8518 u8 reserved_at_20[0x10]; 8519 u8 op_mod[0x10]; 8520 8521 u8 reserved_at_40[0x8]; 8522 u8 qpn[0x18]; 8523 8524 u8 reserved_at_60[0x20]; 8525 8526 u8 multicast_gid[16][0x8]; 8527 }; 8528 8529 struct mlx5_ifc_destroy_xrq_out_bits { 8530 u8 status[0x8]; 8531 u8 reserved_at_8[0x18]; 8532 8533 u8 syndrome[0x20]; 8534 8535 u8 reserved_at_40[0x40]; 8536 }; 8537 8538 struct mlx5_ifc_destroy_xrq_in_bits { 8539 u8 opcode[0x10]; 8540 u8 uid[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 reserved_at_40[0x8]; 8546 u8 xrqn[0x18]; 8547 8548 u8 reserved_at_60[0x20]; 8549 }; 8550 8551 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8552 u8 status[0x8]; 8553 u8 reserved_at_8[0x18]; 8554 8555 u8 syndrome[0x20]; 8556 8557 u8 reserved_at_40[0x40]; 8558 }; 8559 8560 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8561 u8 opcode[0x10]; 8562 u8 uid[0x10]; 8563 8564 u8 reserved_at_20[0x10]; 8565 u8 op_mod[0x10]; 8566 8567 u8 reserved_at_40[0x8]; 8568 u8 xrc_srqn[0x18]; 8569 8570 u8 reserved_at_60[0x20]; 8571 }; 8572 8573 struct mlx5_ifc_destroy_tis_out_bits { 8574 u8 status[0x8]; 8575 u8 reserved_at_8[0x18]; 8576 8577 u8 syndrome[0x20]; 8578 8579 u8 reserved_at_40[0x40]; 8580 }; 8581 8582 struct mlx5_ifc_destroy_tis_in_bits { 8583 u8 opcode[0x10]; 8584 u8 uid[0x10]; 8585 8586 u8 reserved_at_20[0x10]; 8587 u8 op_mod[0x10]; 8588 8589 u8 reserved_at_40[0x8]; 8590 u8 tisn[0x18]; 8591 8592 u8 reserved_at_60[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_destroy_tir_out_bits { 8596 u8 status[0x8]; 8597 u8 reserved_at_8[0x18]; 8598 8599 u8 syndrome[0x20]; 8600 8601 u8 reserved_at_40[0x40]; 8602 }; 8603 8604 struct mlx5_ifc_destroy_tir_in_bits { 8605 u8 opcode[0x10]; 8606 u8 uid[0x10]; 8607 8608 u8 reserved_at_20[0x10]; 8609 u8 op_mod[0x10]; 8610 8611 u8 reserved_at_40[0x8]; 8612 u8 tirn[0x18]; 8613 8614 u8 reserved_at_60[0x20]; 8615 }; 8616 8617 struct mlx5_ifc_destroy_srq_out_bits { 8618 u8 status[0x8]; 8619 u8 reserved_at_8[0x18]; 8620 8621 u8 syndrome[0x20]; 8622 8623 u8 reserved_at_40[0x40]; 8624 }; 8625 8626 struct mlx5_ifc_destroy_srq_in_bits { 8627 u8 opcode[0x10]; 8628 u8 uid[0x10]; 8629 8630 u8 reserved_at_20[0x10]; 8631 u8 op_mod[0x10]; 8632 8633 u8 reserved_at_40[0x8]; 8634 u8 srqn[0x18]; 8635 8636 u8 reserved_at_60[0x20]; 8637 }; 8638 8639 struct mlx5_ifc_destroy_sq_out_bits { 8640 u8 status[0x8]; 8641 u8 reserved_at_8[0x18]; 8642 8643 u8 syndrome[0x20]; 8644 8645 u8 reserved_at_40[0x40]; 8646 }; 8647 8648 struct mlx5_ifc_destroy_sq_in_bits { 8649 u8 opcode[0x10]; 8650 u8 uid[0x10]; 8651 8652 u8 reserved_at_20[0x10]; 8653 u8 op_mod[0x10]; 8654 8655 u8 reserved_at_40[0x8]; 8656 u8 sqn[0x18]; 8657 8658 u8 reserved_at_60[0x20]; 8659 }; 8660 8661 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8662 u8 status[0x8]; 8663 u8 reserved_at_8[0x18]; 8664 8665 u8 syndrome[0x20]; 8666 8667 u8 reserved_at_40[0x1c0]; 8668 }; 8669 8670 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8671 u8 opcode[0x10]; 8672 u8 reserved_at_10[0x10]; 8673 8674 u8 reserved_at_20[0x10]; 8675 u8 op_mod[0x10]; 8676 8677 u8 scheduling_hierarchy[0x8]; 8678 u8 reserved_at_48[0x18]; 8679 8680 u8 scheduling_element_id[0x20]; 8681 8682 u8 reserved_at_80[0x180]; 8683 }; 8684 8685 struct mlx5_ifc_destroy_rqt_out_bits { 8686 u8 status[0x8]; 8687 u8 reserved_at_8[0x18]; 8688 8689 u8 syndrome[0x20]; 8690 8691 u8 reserved_at_40[0x40]; 8692 }; 8693 8694 struct mlx5_ifc_destroy_rqt_in_bits { 8695 u8 opcode[0x10]; 8696 u8 uid[0x10]; 8697 8698 u8 reserved_at_20[0x10]; 8699 u8 op_mod[0x10]; 8700 8701 u8 reserved_at_40[0x8]; 8702 u8 rqtn[0x18]; 8703 8704 u8 reserved_at_60[0x20]; 8705 }; 8706 8707 struct mlx5_ifc_destroy_rq_out_bits { 8708 u8 status[0x8]; 8709 u8 reserved_at_8[0x18]; 8710 8711 u8 syndrome[0x20]; 8712 8713 u8 reserved_at_40[0x40]; 8714 }; 8715 8716 struct mlx5_ifc_destroy_rq_in_bits { 8717 u8 opcode[0x10]; 8718 u8 uid[0x10]; 8719 8720 u8 reserved_at_20[0x10]; 8721 u8 op_mod[0x10]; 8722 8723 u8 reserved_at_40[0x8]; 8724 u8 rqn[0x18]; 8725 8726 u8 reserved_at_60[0x20]; 8727 }; 8728 8729 struct mlx5_ifc_set_delay_drop_params_in_bits { 8730 u8 opcode[0x10]; 8731 u8 reserved_at_10[0x10]; 8732 8733 u8 reserved_at_20[0x10]; 8734 u8 op_mod[0x10]; 8735 8736 u8 reserved_at_40[0x20]; 8737 8738 u8 reserved_at_60[0x10]; 8739 u8 delay_drop_timeout[0x10]; 8740 }; 8741 8742 struct mlx5_ifc_set_delay_drop_params_out_bits { 8743 u8 status[0x8]; 8744 u8 reserved_at_8[0x18]; 8745 8746 u8 syndrome[0x20]; 8747 8748 u8 reserved_at_40[0x40]; 8749 }; 8750 8751 struct mlx5_ifc_destroy_rmp_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x40]; 8758 }; 8759 8760 struct mlx5_ifc_destroy_rmp_in_bits { 8761 u8 opcode[0x10]; 8762 u8 uid[0x10]; 8763 8764 u8 reserved_at_20[0x10]; 8765 u8 op_mod[0x10]; 8766 8767 u8 reserved_at_40[0x8]; 8768 u8 rmpn[0x18]; 8769 8770 u8 reserved_at_60[0x20]; 8771 }; 8772 8773 struct mlx5_ifc_destroy_qp_out_bits { 8774 u8 status[0x8]; 8775 u8 reserved_at_8[0x18]; 8776 8777 u8 syndrome[0x20]; 8778 8779 u8 reserved_at_40[0x40]; 8780 }; 8781 8782 struct mlx5_ifc_destroy_qp_in_bits { 8783 u8 opcode[0x10]; 8784 u8 uid[0x10]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 op_mod[0x10]; 8788 8789 u8 reserved_at_40[0x8]; 8790 u8 qpn[0x18]; 8791 8792 u8 reserved_at_60[0x20]; 8793 }; 8794 8795 struct mlx5_ifc_destroy_psv_out_bits { 8796 u8 status[0x8]; 8797 u8 reserved_at_8[0x18]; 8798 8799 u8 syndrome[0x20]; 8800 8801 u8 reserved_at_40[0x40]; 8802 }; 8803 8804 struct mlx5_ifc_destroy_psv_in_bits { 8805 u8 opcode[0x10]; 8806 u8 reserved_at_10[0x10]; 8807 8808 u8 reserved_at_20[0x10]; 8809 u8 op_mod[0x10]; 8810 8811 u8 reserved_at_40[0x8]; 8812 u8 psvn[0x18]; 8813 8814 u8 reserved_at_60[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_destroy_mkey_out_bits { 8818 u8 status[0x8]; 8819 u8 reserved_at_8[0x18]; 8820 8821 u8 syndrome[0x20]; 8822 8823 u8 reserved_at_40[0x40]; 8824 }; 8825 8826 struct mlx5_ifc_destroy_mkey_in_bits { 8827 u8 opcode[0x10]; 8828 u8 uid[0x10]; 8829 8830 u8 reserved_at_20[0x10]; 8831 u8 op_mod[0x10]; 8832 8833 u8 reserved_at_40[0x8]; 8834 u8 mkey_index[0x18]; 8835 8836 u8 reserved_at_60[0x20]; 8837 }; 8838 8839 struct mlx5_ifc_destroy_flow_table_out_bits { 8840 u8 status[0x8]; 8841 u8 reserved_at_8[0x18]; 8842 8843 u8 syndrome[0x20]; 8844 8845 u8 reserved_at_40[0x40]; 8846 }; 8847 8848 struct mlx5_ifc_destroy_flow_table_in_bits { 8849 u8 opcode[0x10]; 8850 u8 reserved_at_10[0x10]; 8851 8852 u8 reserved_at_20[0x10]; 8853 u8 op_mod[0x10]; 8854 8855 u8 other_vport[0x1]; 8856 u8 other_eswitch[0x1]; 8857 u8 reserved_at_42[0xe]; 8858 u8 vport_number[0x10]; 8859 8860 u8 reserved_at_60[0x20]; 8861 8862 u8 table_type[0x8]; 8863 u8 reserved_at_88[0x8]; 8864 u8 eswitch_owner_vhca_id[0x10]; 8865 8866 u8 reserved_at_a0[0x8]; 8867 u8 table_id[0x18]; 8868 8869 u8 reserved_at_c0[0x140]; 8870 }; 8871 8872 struct mlx5_ifc_destroy_flow_group_out_bits { 8873 u8 status[0x8]; 8874 u8 reserved_at_8[0x18]; 8875 8876 u8 syndrome[0x20]; 8877 8878 u8 reserved_at_40[0x40]; 8879 }; 8880 8881 struct mlx5_ifc_destroy_flow_group_in_bits { 8882 u8 opcode[0x10]; 8883 u8 reserved_at_10[0x10]; 8884 8885 u8 reserved_at_20[0x10]; 8886 u8 op_mod[0x10]; 8887 8888 u8 other_vport[0x1]; 8889 u8 other_eswitch[0x1]; 8890 u8 reserved_at_42[0xe]; 8891 u8 vport_number[0x10]; 8892 8893 u8 reserved_at_60[0x20]; 8894 8895 u8 table_type[0x8]; 8896 u8 reserved_at_88[0x8]; 8897 u8 eswitch_owner_vhca_id[0x10]; 8898 8899 u8 reserved_at_a0[0x8]; 8900 u8 table_id[0x18]; 8901 8902 u8 group_id[0x20]; 8903 8904 u8 reserved_at_e0[0x120]; 8905 }; 8906 8907 struct mlx5_ifc_destroy_eq_out_bits { 8908 u8 status[0x8]; 8909 u8 reserved_at_8[0x18]; 8910 8911 u8 syndrome[0x20]; 8912 8913 u8 reserved_at_40[0x40]; 8914 }; 8915 8916 struct mlx5_ifc_destroy_eq_in_bits { 8917 u8 opcode[0x10]; 8918 u8 reserved_at_10[0x10]; 8919 8920 u8 reserved_at_20[0x10]; 8921 u8 op_mod[0x10]; 8922 8923 u8 reserved_at_40[0x18]; 8924 u8 eq_number[0x8]; 8925 8926 u8 reserved_at_60[0x20]; 8927 }; 8928 8929 struct mlx5_ifc_destroy_dct_out_bits { 8930 u8 status[0x8]; 8931 u8 reserved_at_8[0x18]; 8932 8933 u8 syndrome[0x20]; 8934 8935 u8 reserved_at_40[0x40]; 8936 }; 8937 8938 struct mlx5_ifc_destroy_dct_in_bits { 8939 u8 opcode[0x10]; 8940 u8 uid[0x10]; 8941 8942 u8 reserved_at_20[0x10]; 8943 u8 op_mod[0x10]; 8944 8945 u8 reserved_at_40[0x8]; 8946 u8 dctn[0x18]; 8947 8948 u8 reserved_at_60[0x20]; 8949 }; 8950 8951 struct mlx5_ifc_destroy_cq_out_bits { 8952 u8 status[0x8]; 8953 u8 reserved_at_8[0x18]; 8954 8955 u8 syndrome[0x20]; 8956 8957 u8 reserved_at_40[0x40]; 8958 }; 8959 8960 struct mlx5_ifc_destroy_cq_in_bits { 8961 u8 opcode[0x10]; 8962 u8 uid[0x10]; 8963 8964 u8 reserved_at_20[0x10]; 8965 u8 op_mod[0x10]; 8966 8967 u8 reserved_at_40[0x8]; 8968 u8 cqn[0x18]; 8969 8970 u8 reserved_at_60[0x20]; 8971 }; 8972 8973 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8974 u8 status[0x8]; 8975 u8 reserved_at_8[0x18]; 8976 8977 u8 syndrome[0x20]; 8978 8979 u8 reserved_at_40[0x40]; 8980 }; 8981 8982 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8983 u8 opcode[0x10]; 8984 u8 reserved_at_10[0x10]; 8985 8986 u8 reserved_at_20[0x10]; 8987 u8 op_mod[0x10]; 8988 8989 u8 reserved_at_40[0x20]; 8990 8991 u8 reserved_at_60[0x10]; 8992 u8 vxlan_udp_port[0x10]; 8993 }; 8994 8995 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8996 u8 status[0x8]; 8997 u8 reserved_at_8[0x18]; 8998 8999 u8 syndrome[0x20]; 9000 9001 u8 reserved_at_40[0x40]; 9002 }; 9003 9004 struct mlx5_ifc_delete_l2_table_entry_in_bits { 9005 u8 opcode[0x10]; 9006 u8 reserved_at_10[0x10]; 9007 9008 u8 reserved_at_20[0x10]; 9009 u8 op_mod[0x10]; 9010 9011 u8 reserved_at_40[0x60]; 9012 9013 u8 reserved_at_a0[0x8]; 9014 u8 table_index[0x18]; 9015 9016 u8 reserved_at_c0[0x140]; 9017 }; 9018 9019 struct mlx5_ifc_delete_fte_out_bits { 9020 u8 status[0x8]; 9021 u8 reserved_at_8[0x18]; 9022 9023 u8 syndrome[0x20]; 9024 9025 u8 reserved_at_40[0x40]; 9026 }; 9027 9028 struct mlx5_ifc_delete_fte_in_bits { 9029 u8 opcode[0x10]; 9030 u8 reserved_at_10[0x10]; 9031 9032 u8 reserved_at_20[0x10]; 9033 u8 op_mod[0x10]; 9034 9035 u8 other_vport[0x1]; 9036 u8 other_eswitch[0x1]; 9037 u8 reserved_at_42[0xe]; 9038 u8 vport_number[0x10]; 9039 9040 u8 reserved_at_60[0x20]; 9041 9042 u8 table_type[0x8]; 9043 u8 reserved_at_88[0x8]; 9044 u8 eswitch_owner_vhca_id[0x10]; 9045 9046 u8 reserved_at_a0[0x8]; 9047 u8 table_id[0x18]; 9048 9049 u8 reserved_at_c0[0x40]; 9050 9051 u8 flow_index[0x20]; 9052 9053 u8 reserved_at_120[0xe0]; 9054 }; 9055 9056 struct mlx5_ifc_dealloc_xrcd_out_bits { 9057 u8 status[0x8]; 9058 u8 reserved_at_8[0x18]; 9059 9060 u8 syndrome[0x20]; 9061 9062 u8 reserved_at_40[0x40]; 9063 }; 9064 9065 struct mlx5_ifc_dealloc_xrcd_in_bits { 9066 u8 opcode[0x10]; 9067 u8 uid[0x10]; 9068 9069 u8 reserved_at_20[0x10]; 9070 u8 op_mod[0x10]; 9071 9072 u8 reserved_at_40[0x8]; 9073 u8 xrcd[0x18]; 9074 9075 u8 reserved_at_60[0x20]; 9076 }; 9077 9078 struct mlx5_ifc_dealloc_uar_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 struct mlx5_ifc_dealloc_uar_in_bits { 9088 u8 opcode[0x10]; 9089 u8 uid[0x10]; 9090 9091 u8 reserved_at_20[0x10]; 9092 u8 op_mod[0x10]; 9093 9094 u8 reserved_at_40[0x8]; 9095 u8 uar[0x18]; 9096 9097 u8 reserved_at_60[0x20]; 9098 }; 9099 9100 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9101 u8 status[0x8]; 9102 u8 reserved_at_8[0x18]; 9103 9104 u8 syndrome[0x20]; 9105 9106 u8 reserved_at_40[0x40]; 9107 }; 9108 9109 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9110 u8 opcode[0x10]; 9111 u8 uid[0x10]; 9112 9113 u8 reserved_at_20[0x10]; 9114 u8 op_mod[0x10]; 9115 9116 u8 reserved_at_40[0x8]; 9117 u8 transport_domain[0x18]; 9118 9119 u8 reserved_at_60[0x20]; 9120 }; 9121 9122 struct mlx5_ifc_dealloc_q_counter_out_bits { 9123 u8 status[0x8]; 9124 u8 reserved_at_8[0x18]; 9125 9126 u8 syndrome[0x20]; 9127 9128 u8 reserved_at_40[0x40]; 9129 }; 9130 9131 struct mlx5_ifc_dealloc_q_counter_in_bits { 9132 u8 opcode[0x10]; 9133 u8 reserved_at_10[0x10]; 9134 9135 u8 reserved_at_20[0x10]; 9136 u8 op_mod[0x10]; 9137 9138 u8 reserved_at_40[0x18]; 9139 u8 counter_set_id[0x8]; 9140 9141 u8 reserved_at_60[0x20]; 9142 }; 9143 9144 struct mlx5_ifc_dealloc_pd_out_bits { 9145 u8 status[0x8]; 9146 u8 reserved_at_8[0x18]; 9147 9148 u8 syndrome[0x20]; 9149 9150 u8 reserved_at_40[0x40]; 9151 }; 9152 9153 struct mlx5_ifc_dealloc_pd_in_bits { 9154 u8 opcode[0x10]; 9155 u8 uid[0x10]; 9156 9157 u8 reserved_at_20[0x10]; 9158 u8 op_mod[0x10]; 9159 9160 u8 reserved_at_40[0x8]; 9161 u8 pd[0x18]; 9162 9163 u8 reserved_at_60[0x20]; 9164 }; 9165 9166 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9167 u8 status[0x8]; 9168 u8 reserved_at_8[0x18]; 9169 9170 u8 syndrome[0x20]; 9171 9172 u8 reserved_at_40[0x40]; 9173 }; 9174 9175 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9176 u8 opcode[0x10]; 9177 u8 reserved_at_10[0x10]; 9178 9179 u8 reserved_at_20[0x10]; 9180 u8 op_mod[0x10]; 9181 9182 u8 flow_counter_id[0x20]; 9183 9184 u8 reserved_at_60[0x20]; 9185 }; 9186 9187 struct mlx5_ifc_create_xrq_out_bits { 9188 u8 status[0x8]; 9189 u8 reserved_at_8[0x18]; 9190 9191 u8 syndrome[0x20]; 9192 9193 u8 reserved_at_40[0x8]; 9194 u8 xrqn[0x18]; 9195 9196 u8 reserved_at_60[0x20]; 9197 }; 9198 9199 struct mlx5_ifc_create_xrq_in_bits { 9200 u8 opcode[0x10]; 9201 u8 uid[0x10]; 9202 9203 u8 reserved_at_20[0x10]; 9204 u8 op_mod[0x10]; 9205 9206 u8 reserved_at_40[0x40]; 9207 9208 struct mlx5_ifc_xrqc_bits xrq_context; 9209 }; 9210 9211 struct mlx5_ifc_create_xrc_srq_out_bits { 9212 u8 status[0x8]; 9213 u8 reserved_at_8[0x18]; 9214 9215 u8 syndrome[0x20]; 9216 9217 u8 reserved_at_40[0x8]; 9218 u8 xrc_srqn[0x18]; 9219 9220 u8 reserved_at_60[0x20]; 9221 }; 9222 9223 struct mlx5_ifc_create_xrc_srq_in_bits { 9224 u8 opcode[0x10]; 9225 u8 uid[0x10]; 9226 9227 u8 reserved_at_20[0x10]; 9228 u8 op_mod[0x10]; 9229 9230 u8 reserved_at_40[0x40]; 9231 9232 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9233 9234 u8 reserved_at_280[0x60]; 9235 9236 u8 xrc_srq_umem_valid[0x1]; 9237 u8 reserved_at_2e1[0x1f]; 9238 9239 u8 reserved_at_300[0x580]; 9240 9241 u8 pas[][0x40]; 9242 }; 9243 9244 struct mlx5_ifc_create_tis_out_bits { 9245 u8 status[0x8]; 9246 u8 reserved_at_8[0x18]; 9247 9248 u8 syndrome[0x20]; 9249 9250 u8 reserved_at_40[0x8]; 9251 u8 tisn[0x18]; 9252 9253 u8 reserved_at_60[0x20]; 9254 }; 9255 9256 struct mlx5_ifc_create_tis_in_bits { 9257 u8 opcode[0x10]; 9258 u8 uid[0x10]; 9259 9260 u8 reserved_at_20[0x10]; 9261 u8 op_mod[0x10]; 9262 9263 u8 reserved_at_40[0xc0]; 9264 9265 struct mlx5_ifc_tisc_bits ctx; 9266 }; 9267 9268 struct mlx5_ifc_create_tir_out_bits { 9269 u8 status[0x8]; 9270 u8 icm_address_63_40[0x18]; 9271 9272 u8 syndrome[0x20]; 9273 9274 u8 icm_address_39_32[0x8]; 9275 u8 tirn[0x18]; 9276 9277 u8 icm_address_31_0[0x20]; 9278 }; 9279 9280 struct mlx5_ifc_create_tir_in_bits { 9281 u8 opcode[0x10]; 9282 u8 uid[0x10]; 9283 9284 u8 reserved_at_20[0x10]; 9285 u8 op_mod[0x10]; 9286 9287 u8 reserved_at_40[0xc0]; 9288 9289 struct mlx5_ifc_tirc_bits ctx; 9290 }; 9291 9292 struct mlx5_ifc_create_srq_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 reserved_at_40[0x8]; 9299 u8 srqn[0x18]; 9300 9301 u8 reserved_at_60[0x20]; 9302 }; 9303 9304 struct mlx5_ifc_create_srq_in_bits { 9305 u8 opcode[0x10]; 9306 u8 uid[0x10]; 9307 9308 u8 reserved_at_20[0x10]; 9309 u8 op_mod[0x10]; 9310 9311 u8 reserved_at_40[0x40]; 9312 9313 struct mlx5_ifc_srqc_bits srq_context_entry; 9314 9315 u8 reserved_at_280[0x600]; 9316 9317 u8 pas[][0x40]; 9318 }; 9319 9320 struct mlx5_ifc_create_sq_out_bits { 9321 u8 status[0x8]; 9322 u8 reserved_at_8[0x18]; 9323 9324 u8 syndrome[0x20]; 9325 9326 u8 reserved_at_40[0x8]; 9327 u8 sqn[0x18]; 9328 9329 u8 reserved_at_60[0x20]; 9330 }; 9331 9332 struct mlx5_ifc_create_sq_in_bits { 9333 u8 opcode[0x10]; 9334 u8 uid[0x10]; 9335 9336 u8 reserved_at_20[0x10]; 9337 u8 op_mod[0x10]; 9338 9339 u8 reserved_at_40[0xc0]; 9340 9341 struct mlx5_ifc_sqc_bits ctx; 9342 }; 9343 9344 struct mlx5_ifc_create_scheduling_element_out_bits { 9345 u8 status[0x8]; 9346 u8 reserved_at_8[0x18]; 9347 9348 u8 syndrome[0x20]; 9349 9350 u8 reserved_at_40[0x40]; 9351 9352 u8 scheduling_element_id[0x20]; 9353 9354 u8 reserved_at_a0[0x160]; 9355 }; 9356 9357 struct mlx5_ifc_create_scheduling_element_in_bits { 9358 u8 opcode[0x10]; 9359 u8 reserved_at_10[0x10]; 9360 9361 u8 reserved_at_20[0x10]; 9362 u8 op_mod[0x10]; 9363 9364 u8 scheduling_hierarchy[0x8]; 9365 u8 reserved_at_48[0x18]; 9366 9367 u8 reserved_at_60[0xa0]; 9368 9369 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9370 9371 u8 reserved_at_300[0x100]; 9372 }; 9373 9374 struct mlx5_ifc_create_rqt_out_bits { 9375 u8 status[0x8]; 9376 u8 reserved_at_8[0x18]; 9377 9378 u8 syndrome[0x20]; 9379 9380 u8 reserved_at_40[0x8]; 9381 u8 rqtn[0x18]; 9382 9383 u8 reserved_at_60[0x20]; 9384 }; 9385 9386 struct mlx5_ifc_create_rqt_in_bits { 9387 u8 opcode[0x10]; 9388 u8 uid[0x10]; 9389 9390 u8 reserved_at_20[0x10]; 9391 u8 op_mod[0x10]; 9392 9393 u8 reserved_at_40[0xc0]; 9394 9395 struct mlx5_ifc_rqtc_bits rqt_context; 9396 }; 9397 9398 struct mlx5_ifc_create_rq_out_bits { 9399 u8 status[0x8]; 9400 u8 reserved_at_8[0x18]; 9401 9402 u8 syndrome[0x20]; 9403 9404 u8 reserved_at_40[0x8]; 9405 u8 rqn[0x18]; 9406 9407 u8 reserved_at_60[0x20]; 9408 }; 9409 9410 struct mlx5_ifc_create_rq_in_bits { 9411 u8 opcode[0x10]; 9412 u8 uid[0x10]; 9413 9414 u8 reserved_at_20[0x10]; 9415 u8 op_mod[0x10]; 9416 9417 u8 reserved_at_40[0xc0]; 9418 9419 struct mlx5_ifc_rqc_bits ctx; 9420 }; 9421 9422 struct mlx5_ifc_create_rmp_out_bits { 9423 u8 status[0x8]; 9424 u8 reserved_at_8[0x18]; 9425 9426 u8 syndrome[0x20]; 9427 9428 u8 reserved_at_40[0x8]; 9429 u8 rmpn[0x18]; 9430 9431 u8 reserved_at_60[0x20]; 9432 }; 9433 9434 struct mlx5_ifc_create_rmp_in_bits { 9435 u8 opcode[0x10]; 9436 u8 uid[0x10]; 9437 9438 u8 reserved_at_20[0x10]; 9439 u8 op_mod[0x10]; 9440 9441 u8 reserved_at_40[0xc0]; 9442 9443 struct mlx5_ifc_rmpc_bits ctx; 9444 }; 9445 9446 struct mlx5_ifc_create_qp_out_bits { 9447 u8 status[0x8]; 9448 u8 reserved_at_8[0x18]; 9449 9450 u8 syndrome[0x20]; 9451 9452 u8 reserved_at_40[0x8]; 9453 u8 qpn[0x18]; 9454 9455 u8 ece[0x20]; 9456 }; 9457 9458 struct mlx5_ifc_create_qp_in_bits { 9459 u8 opcode[0x10]; 9460 u8 uid[0x10]; 9461 9462 u8 reserved_at_20[0x10]; 9463 u8 op_mod[0x10]; 9464 9465 u8 qpc_ext[0x1]; 9466 u8 reserved_at_41[0x7]; 9467 u8 input_qpn[0x18]; 9468 9469 u8 reserved_at_60[0x20]; 9470 u8 opt_param_mask[0x20]; 9471 9472 u8 ece[0x20]; 9473 9474 struct mlx5_ifc_qpc_bits qpc; 9475 9476 u8 wq_umem_offset[0x40]; 9477 9478 u8 wq_umem_id[0x20]; 9479 9480 u8 wq_umem_valid[0x1]; 9481 u8 reserved_at_861[0x1f]; 9482 9483 u8 pas[][0x40]; 9484 }; 9485 9486 struct mlx5_ifc_create_psv_out_bits { 9487 u8 status[0x8]; 9488 u8 reserved_at_8[0x18]; 9489 9490 u8 syndrome[0x20]; 9491 9492 u8 reserved_at_40[0x40]; 9493 9494 u8 reserved_at_80[0x8]; 9495 u8 psv0_index[0x18]; 9496 9497 u8 reserved_at_a0[0x8]; 9498 u8 psv1_index[0x18]; 9499 9500 u8 reserved_at_c0[0x8]; 9501 u8 psv2_index[0x18]; 9502 9503 u8 reserved_at_e0[0x8]; 9504 u8 psv3_index[0x18]; 9505 }; 9506 9507 struct mlx5_ifc_create_psv_in_bits { 9508 u8 opcode[0x10]; 9509 u8 reserved_at_10[0x10]; 9510 9511 u8 reserved_at_20[0x10]; 9512 u8 op_mod[0x10]; 9513 9514 u8 num_psv[0x4]; 9515 u8 reserved_at_44[0x4]; 9516 u8 pd[0x18]; 9517 9518 u8 reserved_at_60[0x20]; 9519 }; 9520 9521 struct mlx5_ifc_create_mkey_out_bits { 9522 u8 status[0x8]; 9523 u8 reserved_at_8[0x18]; 9524 9525 u8 syndrome[0x20]; 9526 9527 u8 reserved_at_40[0x8]; 9528 u8 mkey_index[0x18]; 9529 9530 u8 reserved_at_60[0x20]; 9531 }; 9532 9533 struct mlx5_ifc_create_mkey_in_bits { 9534 u8 opcode[0x10]; 9535 u8 uid[0x10]; 9536 9537 u8 reserved_at_20[0x10]; 9538 u8 op_mod[0x10]; 9539 9540 u8 reserved_at_40[0x20]; 9541 9542 u8 pg_access[0x1]; 9543 u8 mkey_umem_valid[0x1]; 9544 u8 data_direct[0x1]; 9545 u8 reserved_at_63[0x1d]; 9546 9547 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9548 9549 u8 reserved_at_280[0x80]; 9550 9551 u8 translations_octword_actual_size[0x20]; 9552 9553 u8 reserved_at_320[0x560]; 9554 9555 u8 klm_pas_mtt[][0x20]; 9556 }; 9557 9558 enum { 9559 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9560 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9561 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9562 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9563 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9564 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9565 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9566 }; 9567 9568 struct mlx5_ifc_create_flow_table_out_bits { 9569 u8 status[0x8]; 9570 u8 icm_address_63_40[0x18]; 9571 9572 u8 syndrome[0x20]; 9573 9574 u8 icm_address_39_32[0x8]; 9575 u8 table_id[0x18]; 9576 9577 u8 icm_address_31_0[0x20]; 9578 }; 9579 9580 struct mlx5_ifc_create_flow_table_in_bits { 9581 u8 opcode[0x10]; 9582 u8 uid[0x10]; 9583 9584 u8 reserved_at_20[0x10]; 9585 u8 op_mod[0x10]; 9586 9587 u8 other_vport[0x1]; 9588 u8 other_eswitch[0x1]; 9589 u8 reserved_at_42[0xe]; 9590 u8 vport_number[0x10]; 9591 9592 u8 reserved_at_60[0x20]; 9593 9594 u8 table_type[0x8]; 9595 u8 reserved_at_88[0x8]; 9596 u8 eswitch_owner_vhca_id[0x10]; 9597 9598 u8 reserved_at_a0[0x20]; 9599 9600 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9601 }; 9602 9603 struct mlx5_ifc_create_flow_group_out_bits { 9604 u8 status[0x8]; 9605 u8 reserved_at_8[0x18]; 9606 9607 u8 syndrome[0x20]; 9608 9609 u8 reserved_at_40[0x8]; 9610 u8 group_id[0x18]; 9611 9612 u8 reserved_at_60[0x20]; 9613 }; 9614 9615 enum { 9616 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9617 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9618 }; 9619 9620 enum { 9621 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9622 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9623 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9624 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9625 }; 9626 9627 struct mlx5_ifc_create_flow_group_in_bits { 9628 u8 opcode[0x10]; 9629 u8 reserved_at_10[0x10]; 9630 9631 u8 reserved_at_20[0x10]; 9632 u8 op_mod[0x10]; 9633 9634 u8 other_vport[0x1]; 9635 u8 other_eswitch[0x1]; 9636 u8 reserved_at_42[0xe]; 9637 u8 vport_number[0x10]; 9638 9639 u8 reserved_at_60[0x20]; 9640 9641 u8 table_type[0x8]; 9642 u8 reserved_at_88[0x4]; 9643 u8 group_type[0x4]; 9644 u8 eswitch_owner_vhca_id[0x10]; 9645 9646 u8 reserved_at_a0[0x8]; 9647 u8 table_id[0x18]; 9648 9649 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9650 9651 u8 reserved_at_c1[0x1f]; 9652 9653 u8 start_flow_index[0x20]; 9654 9655 u8 reserved_at_100[0x20]; 9656 9657 u8 end_flow_index[0x20]; 9658 9659 u8 reserved_at_140[0x10]; 9660 u8 match_definer_id[0x10]; 9661 9662 u8 reserved_at_160[0x80]; 9663 9664 u8 reserved_at_1e0[0x18]; 9665 u8 match_criteria_enable[0x8]; 9666 9667 struct mlx5_ifc_fte_match_param_bits match_criteria; 9668 9669 u8 reserved_at_1200[0xe00]; 9670 }; 9671 9672 struct mlx5_ifc_create_eq_out_bits { 9673 u8 status[0x8]; 9674 u8 reserved_at_8[0x18]; 9675 9676 u8 syndrome[0x20]; 9677 9678 u8 reserved_at_40[0x18]; 9679 u8 eq_number[0x8]; 9680 9681 u8 reserved_at_60[0x20]; 9682 }; 9683 9684 struct mlx5_ifc_create_eq_in_bits { 9685 u8 opcode[0x10]; 9686 u8 uid[0x10]; 9687 9688 u8 reserved_at_20[0x10]; 9689 u8 op_mod[0x10]; 9690 9691 u8 reserved_at_40[0x40]; 9692 9693 struct mlx5_ifc_eqc_bits eq_context_entry; 9694 9695 u8 reserved_at_280[0x40]; 9696 9697 u8 event_bitmask[4][0x40]; 9698 9699 u8 reserved_at_3c0[0x4c0]; 9700 9701 u8 pas[][0x40]; 9702 }; 9703 9704 struct mlx5_ifc_create_dct_out_bits { 9705 u8 status[0x8]; 9706 u8 reserved_at_8[0x18]; 9707 9708 u8 syndrome[0x20]; 9709 9710 u8 reserved_at_40[0x8]; 9711 u8 dctn[0x18]; 9712 9713 u8 ece[0x20]; 9714 }; 9715 9716 struct mlx5_ifc_create_dct_in_bits { 9717 u8 opcode[0x10]; 9718 u8 uid[0x10]; 9719 9720 u8 reserved_at_20[0x10]; 9721 u8 op_mod[0x10]; 9722 9723 u8 reserved_at_40[0x40]; 9724 9725 struct mlx5_ifc_dctc_bits dct_context_entry; 9726 9727 u8 reserved_at_280[0x180]; 9728 }; 9729 9730 struct mlx5_ifc_create_cq_out_bits { 9731 u8 status[0x8]; 9732 u8 reserved_at_8[0x18]; 9733 9734 u8 syndrome[0x20]; 9735 9736 u8 reserved_at_40[0x8]; 9737 u8 cqn[0x18]; 9738 9739 u8 reserved_at_60[0x20]; 9740 }; 9741 9742 struct mlx5_ifc_create_cq_in_bits { 9743 u8 opcode[0x10]; 9744 u8 uid[0x10]; 9745 9746 u8 reserved_at_20[0x10]; 9747 u8 op_mod[0x10]; 9748 9749 u8 reserved_at_40[0x40]; 9750 9751 struct mlx5_ifc_cqc_bits cq_context; 9752 9753 u8 reserved_at_280[0x60]; 9754 9755 u8 cq_umem_valid[0x1]; 9756 u8 reserved_at_2e1[0x59f]; 9757 9758 u8 pas[][0x40]; 9759 }; 9760 9761 struct mlx5_ifc_config_int_moderation_out_bits { 9762 u8 status[0x8]; 9763 u8 reserved_at_8[0x18]; 9764 9765 u8 syndrome[0x20]; 9766 9767 u8 reserved_at_40[0x4]; 9768 u8 min_delay[0xc]; 9769 u8 int_vector[0x10]; 9770 9771 u8 reserved_at_60[0x20]; 9772 }; 9773 9774 enum { 9775 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9776 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9777 }; 9778 9779 struct mlx5_ifc_config_int_moderation_in_bits { 9780 u8 opcode[0x10]; 9781 u8 reserved_at_10[0x10]; 9782 9783 u8 reserved_at_20[0x10]; 9784 u8 op_mod[0x10]; 9785 9786 u8 reserved_at_40[0x4]; 9787 u8 min_delay[0xc]; 9788 u8 int_vector[0x10]; 9789 9790 u8 reserved_at_60[0x20]; 9791 }; 9792 9793 struct mlx5_ifc_attach_to_mcg_out_bits { 9794 u8 status[0x8]; 9795 u8 reserved_at_8[0x18]; 9796 9797 u8 syndrome[0x20]; 9798 9799 u8 reserved_at_40[0x40]; 9800 }; 9801 9802 struct mlx5_ifc_attach_to_mcg_in_bits { 9803 u8 opcode[0x10]; 9804 u8 uid[0x10]; 9805 9806 u8 reserved_at_20[0x10]; 9807 u8 op_mod[0x10]; 9808 9809 u8 reserved_at_40[0x8]; 9810 u8 qpn[0x18]; 9811 9812 u8 reserved_at_60[0x20]; 9813 9814 u8 multicast_gid[16][0x8]; 9815 }; 9816 9817 struct mlx5_ifc_arm_xrq_out_bits { 9818 u8 status[0x8]; 9819 u8 reserved_at_8[0x18]; 9820 9821 u8 syndrome[0x20]; 9822 9823 u8 reserved_at_40[0x40]; 9824 }; 9825 9826 struct mlx5_ifc_arm_xrq_in_bits { 9827 u8 opcode[0x10]; 9828 u8 reserved_at_10[0x10]; 9829 9830 u8 reserved_at_20[0x10]; 9831 u8 op_mod[0x10]; 9832 9833 u8 reserved_at_40[0x8]; 9834 u8 xrqn[0x18]; 9835 9836 u8 reserved_at_60[0x10]; 9837 u8 lwm[0x10]; 9838 }; 9839 9840 struct mlx5_ifc_arm_xrc_srq_out_bits { 9841 u8 status[0x8]; 9842 u8 reserved_at_8[0x18]; 9843 9844 u8 syndrome[0x20]; 9845 9846 u8 reserved_at_40[0x40]; 9847 }; 9848 9849 enum { 9850 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9851 }; 9852 9853 struct mlx5_ifc_arm_xrc_srq_in_bits { 9854 u8 opcode[0x10]; 9855 u8 uid[0x10]; 9856 9857 u8 reserved_at_20[0x10]; 9858 u8 op_mod[0x10]; 9859 9860 u8 reserved_at_40[0x8]; 9861 u8 xrc_srqn[0x18]; 9862 9863 u8 reserved_at_60[0x10]; 9864 u8 lwm[0x10]; 9865 }; 9866 9867 struct mlx5_ifc_arm_rq_out_bits { 9868 u8 status[0x8]; 9869 u8 reserved_at_8[0x18]; 9870 9871 u8 syndrome[0x20]; 9872 9873 u8 reserved_at_40[0x40]; 9874 }; 9875 9876 enum { 9877 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9878 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9879 }; 9880 9881 struct mlx5_ifc_arm_rq_in_bits { 9882 u8 opcode[0x10]; 9883 u8 uid[0x10]; 9884 9885 u8 reserved_at_20[0x10]; 9886 u8 op_mod[0x10]; 9887 9888 u8 reserved_at_40[0x8]; 9889 u8 srq_number[0x18]; 9890 9891 u8 reserved_at_60[0x10]; 9892 u8 lwm[0x10]; 9893 }; 9894 9895 struct mlx5_ifc_arm_dct_out_bits { 9896 u8 status[0x8]; 9897 u8 reserved_at_8[0x18]; 9898 9899 u8 syndrome[0x20]; 9900 9901 u8 reserved_at_40[0x40]; 9902 }; 9903 9904 struct mlx5_ifc_arm_dct_in_bits { 9905 u8 opcode[0x10]; 9906 u8 reserved_at_10[0x10]; 9907 9908 u8 reserved_at_20[0x10]; 9909 u8 op_mod[0x10]; 9910 9911 u8 reserved_at_40[0x8]; 9912 u8 dct_number[0x18]; 9913 9914 u8 reserved_at_60[0x20]; 9915 }; 9916 9917 struct mlx5_ifc_alloc_xrcd_out_bits { 9918 u8 status[0x8]; 9919 u8 reserved_at_8[0x18]; 9920 9921 u8 syndrome[0x20]; 9922 9923 u8 reserved_at_40[0x8]; 9924 u8 xrcd[0x18]; 9925 9926 u8 reserved_at_60[0x20]; 9927 }; 9928 9929 struct mlx5_ifc_alloc_xrcd_in_bits { 9930 u8 opcode[0x10]; 9931 u8 uid[0x10]; 9932 9933 u8 reserved_at_20[0x10]; 9934 u8 op_mod[0x10]; 9935 9936 u8 reserved_at_40[0x40]; 9937 }; 9938 9939 struct mlx5_ifc_alloc_uar_out_bits { 9940 u8 status[0x8]; 9941 u8 reserved_at_8[0x18]; 9942 9943 u8 syndrome[0x20]; 9944 9945 u8 reserved_at_40[0x8]; 9946 u8 uar[0x18]; 9947 9948 u8 reserved_at_60[0x20]; 9949 }; 9950 9951 struct mlx5_ifc_alloc_uar_in_bits { 9952 u8 opcode[0x10]; 9953 u8 uid[0x10]; 9954 9955 u8 reserved_at_20[0x10]; 9956 u8 op_mod[0x10]; 9957 9958 u8 reserved_at_40[0x40]; 9959 }; 9960 9961 struct mlx5_ifc_alloc_transport_domain_out_bits { 9962 u8 status[0x8]; 9963 u8 reserved_at_8[0x18]; 9964 9965 u8 syndrome[0x20]; 9966 9967 u8 reserved_at_40[0x8]; 9968 u8 transport_domain[0x18]; 9969 9970 u8 reserved_at_60[0x20]; 9971 }; 9972 9973 struct mlx5_ifc_alloc_transport_domain_in_bits { 9974 u8 opcode[0x10]; 9975 u8 uid[0x10]; 9976 9977 u8 reserved_at_20[0x10]; 9978 u8 op_mod[0x10]; 9979 9980 u8 reserved_at_40[0x40]; 9981 }; 9982 9983 struct mlx5_ifc_alloc_q_counter_out_bits { 9984 u8 status[0x8]; 9985 u8 reserved_at_8[0x18]; 9986 9987 u8 syndrome[0x20]; 9988 9989 u8 reserved_at_40[0x18]; 9990 u8 counter_set_id[0x8]; 9991 9992 u8 reserved_at_60[0x20]; 9993 }; 9994 9995 struct mlx5_ifc_alloc_q_counter_in_bits { 9996 u8 opcode[0x10]; 9997 u8 uid[0x10]; 9998 9999 u8 reserved_at_20[0x10]; 10000 u8 op_mod[0x10]; 10001 10002 u8 reserved_at_40[0x40]; 10003 }; 10004 10005 struct mlx5_ifc_alloc_pd_out_bits { 10006 u8 status[0x8]; 10007 u8 reserved_at_8[0x18]; 10008 10009 u8 syndrome[0x20]; 10010 10011 u8 reserved_at_40[0x8]; 10012 u8 pd[0x18]; 10013 10014 u8 reserved_at_60[0x20]; 10015 }; 10016 10017 struct mlx5_ifc_alloc_pd_in_bits { 10018 u8 opcode[0x10]; 10019 u8 uid[0x10]; 10020 10021 u8 reserved_at_20[0x10]; 10022 u8 op_mod[0x10]; 10023 10024 u8 reserved_at_40[0x40]; 10025 }; 10026 10027 struct mlx5_ifc_alloc_flow_counter_out_bits { 10028 u8 status[0x8]; 10029 u8 reserved_at_8[0x18]; 10030 10031 u8 syndrome[0x20]; 10032 10033 u8 flow_counter_id[0x20]; 10034 10035 u8 reserved_at_60[0x20]; 10036 }; 10037 10038 struct mlx5_ifc_alloc_flow_counter_in_bits { 10039 u8 opcode[0x10]; 10040 u8 reserved_at_10[0x10]; 10041 10042 u8 reserved_at_20[0x10]; 10043 u8 op_mod[0x10]; 10044 10045 u8 reserved_at_40[0x33]; 10046 u8 flow_counter_bulk_log_size[0x5]; 10047 u8 flow_counter_bulk[0x8]; 10048 }; 10049 10050 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 10051 u8 status[0x8]; 10052 u8 reserved_at_8[0x18]; 10053 10054 u8 syndrome[0x20]; 10055 10056 u8 reserved_at_40[0x40]; 10057 }; 10058 10059 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 10060 u8 opcode[0x10]; 10061 u8 reserved_at_10[0x10]; 10062 10063 u8 reserved_at_20[0x10]; 10064 u8 op_mod[0x10]; 10065 10066 u8 reserved_at_40[0x20]; 10067 10068 u8 reserved_at_60[0x10]; 10069 u8 vxlan_udp_port[0x10]; 10070 }; 10071 10072 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10073 u8 status[0x8]; 10074 u8 reserved_at_8[0x18]; 10075 10076 u8 syndrome[0x20]; 10077 10078 u8 reserved_at_40[0x40]; 10079 }; 10080 10081 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10082 u8 rate_limit[0x20]; 10083 10084 u8 burst_upper_bound[0x20]; 10085 10086 u8 reserved_at_40[0x10]; 10087 u8 typical_packet_size[0x10]; 10088 10089 u8 reserved_at_60[0x120]; 10090 }; 10091 10092 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10093 u8 opcode[0x10]; 10094 u8 uid[0x10]; 10095 10096 u8 reserved_at_20[0x10]; 10097 u8 op_mod[0x10]; 10098 10099 u8 reserved_at_40[0x10]; 10100 u8 rate_limit_index[0x10]; 10101 10102 u8 reserved_at_60[0x20]; 10103 10104 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10105 }; 10106 10107 struct mlx5_ifc_access_register_out_bits { 10108 u8 status[0x8]; 10109 u8 reserved_at_8[0x18]; 10110 10111 u8 syndrome[0x20]; 10112 10113 u8 reserved_at_40[0x40]; 10114 10115 u8 register_data[][0x20]; 10116 }; 10117 10118 enum { 10119 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10120 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10121 }; 10122 10123 struct mlx5_ifc_access_register_in_bits { 10124 u8 opcode[0x10]; 10125 u8 reserved_at_10[0x10]; 10126 10127 u8 reserved_at_20[0x10]; 10128 u8 op_mod[0x10]; 10129 10130 u8 reserved_at_40[0x10]; 10131 u8 register_id[0x10]; 10132 10133 u8 argument[0x20]; 10134 10135 u8 register_data[][0x20]; 10136 }; 10137 10138 struct mlx5_ifc_sltp_reg_bits { 10139 u8 status[0x4]; 10140 u8 version[0x4]; 10141 u8 local_port[0x8]; 10142 u8 pnat[0x2]; 10143 u8 reserved_at_12[0x2]; 10144 u8 lane[0x4]; 10145 u8 reserved_at_18[0x8]; 10146 10147 u8 reserved_at_20[0x20]; 10148 10149 u8 reserved_at_40[0x7]; 10150 u8 polarity[0x1]; 10151 u8 ob_tap0[0x8]; 10152 u8 ob_tap1[0x8]; 10153 u8 ob_tap2[0x8]; 10154 10155 u8 reserved_at_60[0xc]; 10156 u8 ob_preemp_mode[0x4]; 10157 u8 ob_reg[0x8]; 10158 u8 ob_bias[0x8]; 10159 10160 u8 reserved_at_80[0x20]; 10161 }; 10162 10163 struct mlx5_ifc_slrg_reg_bits { 10164 u8 status[0x4]; 10165 u8 version[0x4]; 10166 u8 local_port[0x8]; 10167 u8 pnat[0x2]; 10168 u8 reserved_at_12[0x2]; 10169 u8 lane[0x4]; 10170 u8 reserved_at_18[0x8]; 10171 10172 u8 time_to_link_up[0x10]; 10173 u8 reserved_at_30[0xc]; 10174 u8 grade_lane_speed[0x4]; 10175 10176 u8 grade_version[0x8]; 10177 u8 grade[0x18]; 10178 10179 u8 reserved_at_60[0x4]; 10180 u8 height_grade_type[0x4]; 10181 u8 height_grade[0x18]; 10182 10183 u8 height_dz[0x10]; 10184 u8 height_dv[0x10]; 10185 10186 u8 reserved_at_a0[0x10]; 10187 u8 height_sigma[0x10]; 10188 10189 u8 reserved_at_c0[0x20]; 10190 10191 u8 reserved_at_e0[0x4]; 10192 u8 phase_grade_type[0x4]; 10193 u8 phase_grade[0x18]; 10194 10195 u8 reserved_at_100[0x8]; 10196 u8 phase_eo_pos[0x8]; 10197 u8 reserved_at_110[0x8]; 10198 u8 phase_eo_neg[0x8]; 10199 10200 u8 ffe_set_tested[0x10]; 10201 u8 test_errors_per_lane[0x10]; 10202 }; 10203 10204 struct mlx5_ifc_pvlc_reg_bits { 10205 u8 reserved_at_0[0x8]; 10206 u8 local_port[0x8]; 10207 u8 reserved_at_10[0x10]; 10208 10209 u8 reserved_at_20[0x1c]; 10210 u8 vl_hw_cap[0x4]; 10211 10212 u8 reserved_at_40[0x1c]; 10213 u8 vl_admin[0x4]; 10214 10215 u8 reserved_at_60[0x1c]; 10216 u8 vl_operational[0x4]; 10217 }; 10218 10219 struct mlx5_ifc_pude_reg_bits { 10220 u8 swid[0x8]; 10221 u8 local_port[0x8]; 10222 u8 reserved_at_10[0x4]; 10223 u8 admin_status[0x4]; 10224 u8 reserved_at_18[0x4]; 10225 u8 oper_status[0x4]; 10226 10227 u8 reserved_at_20[0x60]; 10228 }; 10229 10230 enum { 10231 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10232 }; 10233 10234 struct mlx5_ifc_ptys_reg_bits { 10235 u8 reserved_at_0[0x1]; 10236 u8 an_disable_admin[0x1]; 10237 u8 an_disable_cap[0x1]; 10238 u8 reserved_at_3[0x5]; 10239 u8 local_port[0x8]; 10240 u8 reserved_at_10[0x8]; 10241 u8 plane_ind[0x4]; 10242 u8 reserved_at_1c[0x1]; 10243 u8 proto_mask[0x3]; 10244 10245 u8 an_status[0x4]; 10246 u8 reserved_at_24[0xc]; 10247 u8 data_rate_oper[0x10]; 10248 10249 u8 ext_eth_proto_capability[0x20]; 10250 10251 u8 eth_proto_capability[0x20]; 10252 10253 u8 ib_link_width_capability[0x10]; 10254 u8 ib_proto_capability[0x10]; 10255 10256 u8 ext_eth_proto_admin[0x20]; 10257 10258 u8 eth_proto_admin[0x20]; 10259 10260 u8 ib_link_width_admin[0x10]; 10261 u8 ib_proto_admin[0x10]; 10262 10263 u8 ext_eth_proto_oper[0x20]; 10264 10265 u8 eth_proto_oper[0x20]; 10266 10267 u8 ib_link_width_oper[0x10]; 10268 u8 ib_proto_oper[0x10]; 10269 10270 u8 reserved_at_160[0x8]; 10271 u8 lane_rate_oper[0x14]; 10272 u8 connector_type[0x4]; 10273 10274 u8 eth_proto_lp_advertise[0x20]; 10275 10276 u8 reserved_at_1a0[0x60]; 10277 }; 10278 10279 struct mlx5_ifc_mlcr_reg_bits { 10280 u8 reserved_at_0[0x8]; 10281 u8 local_port[0x8]; 10282 u8 reserved_at_10[0x20]; 10283 10284 u8 beacon_duration[0x10]; 10285 u8 reserved_at_40[0x10]; 10286 10287 u8 beacon_remain[0x10]; 10288 }; 10289 10290 struct mlx5_ifc_ptas_reg_bits { 10291 u8 reserved_at_0[0x20]; 10292 10293 u8 algorithm_options[0x10]; 10294 u8 reserved_at_30[0x4]; 10295 u8 repetitions_mode[0x4]; 10296 u8 num_of_repetitions[0x8]; 10297 10298 u8 grade_version[0x8]; 10299 u8 height_grade_type[0x4]; 10300 u8 phase_grade_type[0x4]; 10301 u8 height_grade_weight[0x8]; 10302 u8 phase_grade_weight[0x8]; 10303 10304 u8 gisim_measure_bits[0x10]; 10305 u8 adaptive_tap_measure_bits[0x10]; 10306 10307 u8 ber_bath_high_error_threshold[0x10]; 10308 u8 ber_bath_mid_error_threshold[0x10]; 10309 10310 u8 ber_bath_low_error_threshold[0x10]; 10311 u8 one_ratio_high_threshold[0x10]; 10312 10313 u8 one_ratio_high_mid_threshold[0x10]; 10314 u8 one_ratio_low_mid_threshold[0x10]; 10315 10316 u8 one_ratio_low_threshold[0x10]; 10317 u8 ndeo_error_threshold[0x10]; 10318 10319 u8 mixer_offset_step_size[0x10]; 10320 u8 reserved_at_110[0x8]; 10321 u8 mix90_phase_for_voltage_bath[0x8]; 10322 10323 u8 mixer_offset_start[0x10]; 10324 u8 mixer_offset_end[0x10]; 10325 10326 u8 reserved_at_140[0x15]; 10327 u8 ber_test_time[0xb]; 10328 }; 10329 10330 struct mlx5_ifc_pspa_reg_bits { 10331 u8 swid[0x8]; 10332 u8 local_port[0x8]; 10333 u8 sub_port[0x8]; 10334 u8 reserved_at_18[0x8]; 10335 10336 u8 reserved_at_20[0x20]; 10337 }; 10338 10339 struct mlx5_ifc_pqdr_reg_bits { 10340 u8 reserved_at_0[0x8]; 10341 u8 local_port[0x8]; 10342 u8 reserved_at_10[0x5]; 10343 u8 prio[0x3]; 10344 u8 reserved_at_18[0x6]; 10345 u8 mode[0x2]; 10346 10347 u8 reserved_at_20[0x20]; 10348 10349 u8 reserved_at_40[0x10]; 10350 u8 min_threshold[0x10]; 10351 10352 u8 reserved_at_60[0x10]; 10353 u8 max_threshold[0x10]; 10354 10355 u8 reserved_at_80[0x10]; 10356 u8 mark_probability_denominator[0x10]; 10357 10358 u8 reserved_at_a0[0x60]; 10359 }; 10360 10361 struct mlx5_ifc_ppsc_reg_bits { 10362 u8 reserved_at_0[0x8]; 10363 u8 local_port[0x8]; 10364 u8 reserved_at_10[0x10]; 10365 10366 u8 reserved_at_20[0x60]; 10367 10368 u8 reserved_at_80[0x1c]; 10369 u8 wrps_admin[0x4]; 10370 10371 u8 reserved_at_a0[0x1c]; 10372 u8 wrps_status[0x4]; 10373 10374 u8 reserved_at_c0[0x8]; 10375 u8 up_threshold[0x8]; 10376 u8 reserved_at_d0[0x8]; 10377 u8 down_threshold[0x8]; 10378 10379 u8 reserved_at_e0[0x20]; 10380 10381 u8 reserved_at_100[0x1c]; 10382 u8 srps_admin[0x4]; 10383 10384 u8 reserved_at_120[0x1c]; 10385 u8 srps_status[0x4]; 10386 10387 u8 reserved_at_140[0x40]; 10388 }; 10389 10390 struct mlx5_ifc_pplr_reg_bits { 10391 u8 reserved_at_0[0x8]; 10392 u8 local_port[0x8]; 10393 u8 reserved_at_10[0x10]; 10394 10395 u8 reserved_at_20[0x8]; 10396 u8 lb_cap[0x8]; 10397 u8 reserved_at_30[0x8]; 10398 u8 lb_en[0x8]; 10399 }; 10400 10401 struct mlx5_ifc_pplm_reg_bits { 10402 u8 reserved_at_0[0x8]; 10403 u8 local_port[0x8]; 10404 u8 reserved_at_10[0x10]; 10405 10406 u8 reserved_at_20[0x20]; 10407 10408 u8 port_profile_mode[0x8]; 10409 u8 static_port_profile[0x8]; 10410 u8 active_port_profile[0x8]; 10411 u8 reserved_at_58[0x8]; 10412 10413 u8 retransmission_active[0x8]; 10414 u8 fec_mode_active[0x18]; 10415 10416 u8 rs_fec_correction_bypass_cap[0x4]; 10417 u8 reserved_at_84[0x8]; 10418 u8 fec_override_cap_56g[0x4]; 10419 u8 fec_override_cap_100g[0x4]; 10420 u8 fec_override_cap_50g[0x4]; 10421 u8 fec_override_cap_25g[0x4]; 10422 u8 fec_override_cap_10g_40g[0x4]; 10423 10424 u8 rs_fec_correction_bypass_admin[0x4]; 10425 u8 reserved_at_a4[0x8]; 10426 u8 fec_override_admin_56g[0x4]; 10427 u8 fec_override_admin_100g[0x4]; 10428 u8 fec_override_admin_50g[0x4]; 10429 u8 fec_override_admin_25g[0x4]; 10430 u8 fec_override_admin_10g_40g[0x4]; 10431 10432 u8 fec_override_cap_400g_8x[0x10]; 10433 u8 fec_override_cap_200g_4x[0x10]; 10434 10435 u8 fec_override_cap_100g_2x[0x10]; 10436 u8 fec_override_cap_50g_1x[0x10]; 10437 10438 u8 fec_override_admin_400g_8x[0x10]; 10439 u8 fec_override_admin_200g_4x[0x10]; 10440 10441 u8 fec_override_admin_100g_2x[0x10]; 10442 u8 fec_override_admin_50g_1x[0x10]; 10443 10444 u8 fec_override_cap_800g_8x[0x10]; 10445 u8 fec_override_cap_400g_4x[0x10]; 10446 10447 u8 fec_override_cap_200g_2x[0x10]; 10448 u8 fec_override_cap_100g_1x[0x10]; 10449 10450 u8 reserved_at_180[0xa0]; 10451 10452 u8 fec_override_admin_800g_8x[0x10]; 10453 u8 fec_override_admin_400g_4x[0x10]; 10454 10455 u8 fec_override_admin_200g_2x[0x10]; 10456 u8 fec_override_admin_100g_1x[0x10]; 10457 10458 u8 reserved_at_260[0x60]; 10459 10460 u8 fec_override_cap_1600g_8x[0x10]; 10461 u8 fec_override_cap_800g_4x[0x10]; 10462 10463 u8 fec_override_cap_400g_2x[0x10]; 10464 u8 fec_override_cap_200g_1x[0x10]; 10465 10466 u8 fec_override_admin_1600g_8x[0x10]; 10467 u8 fec_override_admin_800g_4x[0x10]; 10468 10469 u8 fec_override_admin_400g_2x[0x10]; 10470 u8 fec_override_admin_200g_1x[0x10]; 10471 10472 u8 reserved_at_340[0x80]; 10473 }; 10474 10475 struct mlx5_ifc_ppcnt_reg_bits { 10476 u8 swid[0x8]; 10477 u8 local_port[0x8]; 10478 u8 pnat[0x2]; 10479 u8 reserved_at_12[0x8]; 10480 u8 grp[0x6]; 10481 10482 u8 clr[0x1]; 10483 u8 reserved_at_21[0x13]; 10484 u8 plane_ind[0x4]; 10485 u8 reserved_at_38[0x3]; 10486 u8 prio_tc[0x5]; 10487 10488 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10489 }; 10490 10491 struct mlx5_ifc_mpein_reg_bits { 10492 u8 reserved_at_0[0x2]; 10493 u8 depth[0x6]; 10494 u8 pcie_index[0x8]; 10495 u8 node[0x8]; 10496 u8 reserved_at_18[0x8]; 10497 10498 u8 capability_mask[0x20]; 10499 10500 u8 reserved_at_40[0x8]; 10501 u8 link_width_enabled[0x8]; 10502 u8 link_speed_enabled[0x10]; 10503 10504 u8 lane0_physical_position[0x8]; 10505 u8 link_width_active[0x8]; 10506 u8 link_speed_active[0x10]; 10507 10508 u8 num_of_pfs[0x10]; 10509 u8 num_of_vfs[0x10]; 10510 10511 u8 bdf0[0x10]; 10512 u8 reserved_at_b0[0x10]; 10513 10514 u8 max_read_request_size[0x4]; 10515 u8 max_payload_size[0x4]; 10516 u8 reserved_at_c8[0x5]; 10517 u8 pwr_status[0x3]; 10518 u8 port_type[0x4]; 10519 u8 reserved_at_d4[0xb]; 10520 u8 lane_reversal[0x1]; 10521 10522 u8 reserved_at_e0[0x14]; 10523 u8 pci_power[0xc]; 10524 10525 u8 reserved_at_100[0x20]; 10526 10527 u8 device_status[0x10]; 10528 u8 port_state[0x8]; 10529 u8 reserved_at_138[0x8]; 10530 10531 u8 reserved_at_140[0x10]; 10532 u8 receiver_detect_result[0x10]; 10533 10534 u8 reserved_at_160[0x20]; 10535 }; 10536 10537 struct mlx5_ifc_mpcnt_reg_bits { 10538 u8 reserved_at_0[0x8]; 10539 u8 pcie_index[0x8]; 10540 u8 reserved_at_10[0xa]; 10541 u8 grp[0x6]; 10542 10543 u8 clr[0x1]; 10544 u8 reserved_at_21[0x1f]; 10545 10546 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10547 }; 10548 10549 struct mlx5_ifc_ppad_reg_bits { 10550 u8 reserved_at_0[0x3]; 10551 u8 single_mac[0x1]; 10552 u8 reserved_at_4[0x4]; 10553 u8 local_port[0x8]; 10554 u8 mac_47_32[0x10]; 10555 10556 u8 mac_31_0[0x20]; 10557 10558 u8 reserved_at_40[0x40]; 10559 }; 10560 10561 struct mlx5_ifc_pmtu_reg_bits { 10562 u8 reserved_at_0[0x8]; 10563 u8 local_port[0x8]; 10564 u8 reserved_at_10[0x10]; 10565 10566 u8 max_mtu[0x10]; 10567 u8 reserved_at_30[0x10]; 10568 10569 u8 admin_mtu[0x10]; 10570 u8 reserved_at_50[0x10]; 10571 10572 u8 oper_mtu[0x10]; 10573 u8 reserved_at_70[0x10]; 10574 }; 10575 10576 struct mlx5_ifc_pmpr_reg_bits { 10577 u8 reserved_at_0[0x8]; 10578 u8 module[0x8]; 10579 u8 reserved_at_10[0x10]; 10580 10581 u8 reserved_at_20[0x18]; 10582 u8 attenuation_5g[0x8]; 10583 10584 u8 reserved_at_40[0x18]; 10585 u8 attenuation_7g[0x8]; 10586 10587 u8 reserved_at_60[0x18]; 10588 u8 attenuation_12g[0x8]; 10589 }; 10590 10591 struct mlx5_ifc_pmpe_reg_bits { 10592 u8 reserved_at_0[0x8]; 10593 u8 module[0x8]; 10594 u8 reserved_at_10[0xc]; 10595 u8 module_status[0x4]; 10596 10597 u8 reserved_at_20[0x60]; 10598 }; 10599 10600 struct mlx5_ifc_pmpc_reg_bits { 10601 u8 module_state_updated[32][0x8]; 10602 }; 10603 10604 struct mlx5_ifc_pmlpn_reg_bits { 10605 u8 reserved_at_0[0x4]; 10606 u8 mlpn_status[0x4]; 10607 u8 local_port[0x8]; 10608 u8 reserved_at_10[0x10]; 10609 10610 u8 e[0x1]; 10611 u8 reserved_at_21[0x1f]; 10612 }; 10613 10614 struct mlx5_ifc_pmlp_reg_bits { 10615 u8 rxtx[0x1]; 10616 u8 reserved_at_1[0x7]; 10617 u8 local_port[0x8]; 10618 u8 reserved_at_10[0x8]; 10619 u8 width[0x8]; 10620 10621 u8 lane0_module_mapping[0x20]; 10622 10623 u8 lane1_module_mapping[0x20]; 10624 10625 u8 lane2_module_mapping[0x20]; 10626 10627 u8 lane3_module_mapping[0x20]; 10628 10629 u8 reserved_at_a0[0x160]; 10630 }; 10631 10632 struct mlx5_ifc_pmaos_reg_bits { 10633 u8 reserved_at_0[0x8]; 10634 u8 module[0x8]; 10635 u8 reserved_at_10[0x4]; 10636 u8 admin_status[0x4]; 10637 u8 reserved_at_18[0x4]; 10638 u8 oper_status[0x4]; 10639 10640 u8 ase[0x1]; 10641 u8 ee[0x1]; 10642 u8 reserved_at_22[0x1c]; 10643 u8 e[0x2]; 10644 10645 u8 reserved_at_40[0x40]; 10646 }; 10647 10648 struct mlx5_ifc_plpc_reg_bits { 10649 u8 reserved_at_0[0x4]; 10650 u8 profile_id[0xc]; 10651 u8 reserved_at_10[0x4]; 10652 u8 proto_mask[0x4]; 10653 u8 reserved_at_18[0x8]; 10654 10655 u8 reserved_at_20[0x10]; 10656 u8 lane_speed[0x10]; 10657 10658 u8 reserved_at_40[0x17]; 10659 u8 lpbf[0x1]; 10660 u8 fec_mode_policy[0x8]; 10661 10662 u8 retransmission_capability[0x8]; 10663 u8 fec_mode_capability[0x18]; 10664 10665 u8 retransmission_support_admin[0x8]; 10666 u8 fec_mode_support_admin[0x18]; 10667 10668 u8 retransmission_request_admin[0x8]; 10669 u8 fec_mode_request_admin[0x18]; 10670 10671 u8 reserved_at_c0[0x80]; 10672 }; 10673 10674 struct mlx5_ifc_plib_reg_bits { 10675 u8 reserved_at_0[0x8]; 10676 u8 local_port[0x8]; 10677 u8 reserved_at_10[0x8]; 10678 u8 ib_port[0x8]; 10679 10680 u8 reserved_at_20[0x60]; 10681 }; 10682 10683 struct mlx5_ifc_plbf_reg_bits { 10684 u8 reserved_at_0[0x8]; 10685 u8 local_port[0x8]; 10686 u8 reserved_at_10[0xd]; 10687 u8 lbf_mode[0x3]; 10688 10689 u8 reserved_at_20[0x20]; 10690 }; 10691 10692 struct mlx5_ifc_pipg_reg_bits { 10693 u8 reserved_at_0[0x8]; 10694 u8 local_port[0x8]; 10695 u8 reserved_at_10[0x10]; 10696 10697 u8 dic[0x1]; 10698 u8 reserved_at_21[0x19]; 10699 u8 ipg[0x4]; 10700 u8 reserved_at_3e[0x2]; 10701 }; 10702 10703 struct mlx5_ifc_pifr_reg_bits { 10704 u8 reserved_at_0[0x8]; 10705 u8 local_port[0x8]; 10706 u8 reserved_at_10[0x10]; 10707 10708 u8 reserved_at_20[0xe0]; 10709 10710 u8 port_filter[8][0x20]; 10711 10712 u8 port_filter_update_en[8][0x20]; 10713 }; 10714 10715 enum { 10716 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10717 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10718 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10719 }; 10720 10721 struct mlx5_ifc_pfcc_reg_bits { 10722 u8 reserved_at_0[0x4]; 10723 u8 buf_ownership[0x2]; 10724 u8 reserved_at_6[0x2]; 10725 u8 local_port[0x8]; 10726 u8 reserved_at_10[0xa]; 10727 u8 cable_length_mask[0x1]; 10728 u8 ppan_mask_n[0x1]; 10729 u8 minor_stall_mask[0x1]; 10730 u8 critical_stall_mask[0x1]; 10731 u8 reserved_at_1e[0x2]; 10732 10733 u8 ppan[0x4]; 10734 u8 reserved_at_24[0x4]; 10735 u8 prio_mask_tx[0x8]; 10736 u8 reserved_at_30[0x8]; 10737 u8 prio_mask_rx[0x8]; 10738 10739 u8 pptx[0x1]; 10740 u8 aptx[0x1]; 10741 u8 pptx_mask_n[0x1]; 10742 u8 reserved_at_43[0x5]; 10743 u8 pfctx[0x8]; 10744 u8 reserved_at_50[0x10]; 10745 10746 u8 pprx[0x1]; 10747 u8 aprx[0x1]; 10748 u8 pprx_mask_n[0x1]; 10749 u8 reserved_at_63[0x5]; 10750 u8 pfcrx[0x8]; 10751 u8 reserved_at_70[0x10]; 10752 10753 u8 device_stall_minor_watermark[0x10]; 10754 u8 device_stall_critical_watermark[0x10]; 10755 10756 u8 reserved_at_a0[0x18]; 10757 u8 cable_length[0x8]; 10758 10759 u8 reserved_at_c0[0x40]; 10760 }; 10761 10762 struct mlx5_ifc_pelc_reg_bits { 10763 u8 op[0x4]; 10764 u8 reserved_at_4[0x4]; 10765 u8 local_port[0x8]; 10766 u8 reserved_at_10[0x10]; 10767 10768 u8 op_admin[0x8]; 10769 u8 op_capability[0x8]; 10770 u8 op_request[0x8]; 10771 u8 op_active[0x8]; 10772 10773 u8 admin[0x40]; 10774 10775 u8 capability[0x40]; 10776 10777 u8 request[0x40]; 10778 10779 u8 active[0x40]; 10780 10781 u8 reserved_at_140[0x80]; 10782 }; 10783 10784 struct mlx5_ifc_peir_reg_bits { 10785 u8 reserved_at_0[0x8]; 10786 u8 local_port[0x8]; 10787 u8 reserved_at_10[0x10]; 10788 10789 u8 reserved_at_20[0xc]; 10790 u8 error_count[0x4]; 10791 u8 reserved_at_30[0x10]; 10792 10793 u8 reserved_at_40[0xc]; 10794 u8 lane[0x4]; 10795 u8 reserved_at_50[0x8]; 10796 u8 error_type[0x8]; 10797 }; 10798 10799 struct mlx5_ifc_mpegc_reg_bits { 10800 u8 reserved_at_0[0x30]; 10801 u8 field_select[0x10]; 10802 10803 u8 tx_overflow_sense[0x1]; 10804 u8 mark_cqe[0x1]; 10805 u8 mark_cnp[0x1]; 10806 u8 reserved_at_43[0x1b]; 10807 u8 tx_lossy_overflow_oper[0x2]; 10808 10809 u8 reserved_at_60[0x100]; 10810 }; 10811 10812 struct mlx5_ifc_mpir_reg_bits { 10813 u8 sdm[0x1]; 10814 u8 reserved_at_1[0x1b]; 10815 u8 host_buses[0x4]; 10816 10817 u8 reserved_at_20[0x20]; 10818 10819 u8 local_port[0x8]; 10820 u8 reserved_at_28[0x18]; 10821 10822 u8 reserved_at_60[0x20]; 10823 }; 10824 10825 enum { 10826 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10827 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10828 }; 10829 10830 enum { 10831 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10832 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10833 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10834 }; 10835 10836 struct mlx5_ifc_mtutc_reg_bits { 10837 u8 reserved_at_0[0x5]; 10838 u8 freq_adj_units[0x3]; 10839 u8 reserved_at_8[0x3]; 10840 u8 log_max_freq_adjustment[0x5]; 10841 10842 u8 reserved_at_10[0xc]; 10843 u8 operation[0x4]; 10844 10845 u8 freq_adjustment[0x20]; 10846 10847 u8 reserved_at_40[0x40]; 10848 10849 u8 utc_sec[0x20]; 10850 10851 u8 reserved_at_a0[0x2]; 10852 u8 utc_nsec[0x1e]; 10853 10854 u8 time_adjustment[0x20]; 10855 }; 10856 10857 struct mlx5_ifc_pcam_enhanced_features_bits { 10858 u8 reserved_at_0[0x10]; 10859 u8 ppcnt_recovery_counters[0x1]; 10860 u8 reserved_at_11[0x7]; 10861 u8 cable_length[0x1]; 10862 u8 reserved_at_19[0x4]; 10863 u8 fec_200G_per_lane_in_pplm[0x1]; 10864 u8 reserved_at_1e[0x2a]; 10865 u8 fec_100G_per_lane_in_pplm[0x1]; 10866 u8 reserved_at_49[0x2]; 10867 u8 shp_pbmc_pbsr_support[0x1]; 10868 u8 reserved_at_4c[0x7]; 10869 u8 buffer_ownership[0x1]; 10870 u8 resereved_at_54[0x14]; 10871 u8 fec_50G_per_lane_in_pplm[0x1]; 10872 u8 reserved_at_69[0x4]; 10873 u8 rx_icrc_encapsulated_counter[0x1]; 10874 u8 reserved_at_6e[0x4]; 10875 u8 ptys_extended_ethernet[0x1]; 10876 u8 reserved_at_73[0x3]; 10877 u8 pfcc_mask[0x1]; 10878 u8 reserved_at_77[0x3]; 10879 u8 per_lane_error_counters[0x1]; 10880 u8 rx_buffer_fullness_counters[0x1]; 10881 u8 ptys_connector_type[0x1]; 10882 u8 reserved_at_7d[0x1]; 10883 u8 ppcnt_discard_group[0x1]; 10884 u8 ppcnt_statistical_group[0x1]; 10885 }; 10886 10887 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10888 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10889 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10890 10891 u8 port_access_reg_cap_mask_63[0x1]; 10892 u8 pphcr[0x1]; 10893 u8 port_access_reg_cap_mask_61_to_36[0x1a]; 10894 u8 pplm[0x1]; 10895 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10896 10897 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10898 u8 pbmc[0x1]; 10899 u8 pptb[0x1]; 10900 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10901 u8 ppcnt[0x1]; 10902 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10903 }; 10904 10905 struct mlx5_ifc_pcam_reg_bits { 10906 u8 reserved_at_0[0x8]; 10907 u8 feature_group[0x8]; 10908 u8 reserved_at_10[0x8]; 10909 u8 access_reg_group[0x8]; 10910 10911 u8 reserved_at_20[0x20]; 10912 10913 union { 10914 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10915 u8 reserved_at_0[0x80]; 10916 } port_access_reg_cap_mask; 10917 10918 u8 reserved_at_c0[0x80]; 10919 10920 union { 10921 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10922 u8 reserved_at_0[0x80]; 10923 } feature_cap_mask; 10924 10925 u8 reserved_at_1c0[0xc0]; 10926 }; 10927 10928 struct mlx5_ifc_mcam_enhanced_features_bits { 10929 u8 reserved_at_0[0x50]; 10930 u8 mtutc_freq_adj_units[0x1]; 10931 u8 mtutc_time_adjustment_extended_range[0x1]; 10932 u8 reserved_at_52[0xb]; 10933 u8 mcia_32dwords[0x1]; 10934 u8 out_pulse_duration_ns[0x1]; 10935 u8 npps_period[0x1]; 10936 u8 reserved_at_60[0xa]; 10937 u8 reset_state[0x1]; 10938 u8 ptpcyc2realtime_modify[0x1]; 10939 u8 reserved_at_6c[0x2]; 10940 u8 pci_status_and_power[0x1]; 10941 u8 reserved_at_6f[0x5]; 10942 u8 mark_tx_action_cnp[0x1]; 10943 u8 mark_tx_action_cqe[0x1]; 10944 u8 dynamic_tx_overflow[0x1]; 10945 u8 reserved_at_77[0x4]; 10946 u8 pcie_outbound_stalled[0x1]; 10947 u8 tx_overflow_buffer_pkt[0x1]; 10948 u8 mtpps_enh_out_per_adj[0x1]; 10949 u8 mtpps_fs[0x1]; 10950 u8 pcie_performance_group[0x1]; 10951 }; 10952 10953 struct mlx5_ifc_mcam_access_reg_bits { 10954 u8 reserved_at_0[0x1c]; 10955 u8 mcda[0x1]; 10956 u8 mcc[0x1]; 10957 u8 mcqi[0x1]; 10958 u8 mcqs[0x1]; 10959 10960 u8 regs_95_to_90[0x6]; 10961 u8 mpir[0x1]; 10962 u8 regs_88_to_87[0x2]; 10963 u8 mpegc[0x1]; 10964 u8 mtutc[0x1]; 10965 u8 regs_84_to_68[0x11]; 10966 u8 tracer_registers[0x4]; 10967 10968 u8 regs_63_to_46[0x12]; 10969 u8 mrtc[0x1]; 10970 u8 regs_44_to_41[0x4]; 10971 u8 mfrl[0x1]; 10972 u8 regs_39_to_32[0x8]; 10973 10974 u8 regs_31_to_11[0x15]; 10975 u8 mtmp[0x1]; 10976 u8 regs_9_to_0[0xa]; 10977 }; 10978 10979 struct mlx5_ifc_mcam_access_reg_bits1 { 10980 u8 regs_127_to_96[0x20]; 10981 10982 u8 regs_95_to_64[0x20]; 10983 10984 u8 regs_63_to_32[0x20]; 10985 10986 u8 regs_31_to_0[0x20]; 10987 }; 10988 10989 struct mlx5_ifc_mcam_access_reg_bits2 { 10990 u8 regs_127_to_99[0x1d]; 10991 u8 mirc[0x1]; 10992 u8 regs_97_to_96[0x2]; 10993 10994 u8 regs_95_to_87[0x09]; 10995 u8 synce_registers[0x2]; 10996 u8 regs_84_to_64[0x15]; 10997 10998 u8 regs_63_to_32[0x20]; 10999 11000 u8 regs_31_to_0[0x20]; 11001 }; 11002 11003 struct mlx5_ifc_mcam_access_reg_bits3 { 11004 u8 regs_127_to_96[0x20]; 11005 11006 u8 regs_95_to_64[0x20]; 11007 11008 u8 regs_63_to_32[0x20]; 11009 11010 u8 regs_31_to_3[0x1d]; 11011 u8 mrtcq[0x1]; 11012 u8 mtctr[0x1]; 11013 u8 mtptm[0x1]; 11014 }; 11015 11016 struct mlx5_ifc_mcam_reg_bits { 11017 u8 reserved_at_0[0x8]; 11018 u8 feature_group[0x8]; 11019 u8 reserved_at_10[0x8]; 11020 u8 access_reg_group[0x8]; 11021 11022 u8 reserved_at_20[0x20]; 11023 11024 union { 11025 struct mlx5_ifc_mcam_access_reg_bits access_regs; 11026 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 11027 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 11028 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 11029 u8 reserved_at_0[0x80]; 11030 } mng_access_reg_cap_mask; 11031 11032 u8 reserved_at_c0[0x80]; 11033 11034 union { 11035 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 11036 u8 reserved_at_0[0x80]; 11037 } mng_feature_cap_mask; 11038 11039 u8 reserved_at_1c0[0x80]; 11040 }; 11041 11042 struct mlx5_ifc_qcam_access_reg_cap_mask { 11043 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 11044 u8 qpdpm[0x1]; 11045 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 11046 u8 qdpm[0x1]; 11047 u8 qpts[0x1]; 11048 u8 qcap[0x1]; 11049 u8 qcam_access_reg_cap_mask_0[0x1]; 11050 }; 11051 11052 struct mlx5_ifc_qcam_qos_feature_cap_mask { 11053 u8 qcam_qos_feature_cap_mask_127_to_5[0x7B]; 11054 u8 qetcr_qshr_max_bw_val_msb[0x1]; 11055 u8 qcam_qos_feature_cap_mask_3_to_1[0x3]; 11056 u8 qpts_trust_both[0x1]; 11057 }; 11058 11059 struct mlx5_ifc_qcam_reg_bits { 11060 u8 reserved_at_0[0x8]; 11061 u8 feature_group[0x8]; 11062 u8 reserved_at_10[0x8]; 11063 u8 access_reg_group[0x8]; 11064 u8 reserved_at_20[0x20]; 11065 11066 union { 11067 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 11068 u8 reserved_at_0[0x80]; 11069 } qos_access_reg_cap_mask; 11070 11071 u8 reserved_at_c0[0x80]; 11072 11073 union { 11074 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11075 u8 reserved_at_0[0x80]; 11076 } qos_feature_cap_mask; 11077 11078 u8 reserved_at_1c0[0x80]; 11079 }; 11080 11081 struct mlx5_ifc_core_dump_reg_bits { 11082 u8 reserved_at_0[0x18]; 11083 u8 core_dump_type[0x8]; 11084 11085 u8 reserved_at_20[0x30]; 11086 u8 vhca_id[0x10]; 11087 11088 u8 reserved_at_60[0x8]; 11089 u8 qpn[0x18]; 11090 u8 reserved_at_80[0x180]; 11091 }; 11092 11093 struct mlx5_ifc_pcap_reg_bits { 11094 u8 reserved_at_0[0x8]; 11095 u8 local_port[0x8]; 11096 u8 reserved_at_10[0x10]; 11097 11098 u8 port_capability_mask[4][0x20]; 11099 }; 11100 11101 struct mlx5_ifc_paos_reg_bits { 11102 u8 swid[0x8]; 11103 u8 local_port[0x8]; 11104 u8 reserved_at_10[0x4]; 11105 u8 admin_status[0x4]; 11106 u8 reserved_at_18[0x4]; 11107 u8 oper_status[0x4]; 11108 11109 u8 ase[0x1]; 11110 u8 ee[0x1]; 11111 u8 reserved_at_22[0x1c]; 11112 u8 e[0x2]; 11113 11114 u8 reserved_at_40[0x40]; 11115 }; 11116 11117 struct mlx5_ifc_pamp_reg_bits { 11118 u8 reserved_at_0[0x8]; 11119 u8 opamp_group[0x8]; 11120 u8 reserved_at_10[0xc]; 11121 u8 opamp_group_type[0x4]; 11122 11123 u8 start_index[0x10]; 11124 u8 reserved_at_30[0x4]; 11125 u8 num_of_indices[0xc]; 11126 11127 u8 index_data[18][0x10]; 11128 }; 11129 11130 struct mlx5_ifc_pcmr_reg_bits { 11131 u8 reserved_at_0[0x8]; 11132 u8 local_port[0x8]; 11133 u8 reserved_at_10[0x10]; 11134 11135 u8 entropy_force_cap[0x1]; 11136 u8 entropy_calc_cap[0x1]; 11137 u8 entropy_gre_calc_cap[0x1]; 11138 u8 reserved_at_23[0xf]; 11139 u8 rx_ts_over_crc_cap[0x1]; 11140 u8 reserved_at_33[0xb]; 11141 u8 fcs_cap[0x1]; 11142 u8 reserved_at_3f[0x1]; 11143 11144 u8 entropy_force[0x1]; 11145 u8 entropy_calc[0x1]; 11146 u8 entropy_gre_calc[0x1]; 11147 u8 reserved_at_43[0xf]; 11148 u8 rx_ts_over_crc[0x1]; 11149 u8 reserved_at_53[0xb]; 11150 u8 fcs_chk[0x1]; 11151 u8 reserved_at_5f[0x1]; 11152 }; 11153 11154 struct mlx5_ifc_lane_2_module_mapping_bits { 11155 u8 reserved_at_0[0x4]; 11156 u8 rx_lane[0x4]; 11157 u8 reserved_at_8[0x4]; 11158 u8 tx_lane[0x4]; 11159 u8 reserved_at_10[0x8]; 11160 u8 module[0x8]; 11161 }; 11162 11163 struct mlx5_ifc_bufferx_reg_bits { 11164 u8 reserved_at_0[0x6]; 11165 u8 lossy[0x1]; 11166 u8 epsb[0x1]; 11167 u8 reserved_at_8[0x8]; 11168 u8 size[0x10]; 11169 11170 u8 xoff_threshold[0x10]; 11171 u8 xon_threshold[0x10]; 11172 }; 11173 11174 struct mlx5_ifc_set_node_in_bits { 11175 u8 node_description[64][0x8]; 11176 }; 11177 11178 struct mlx5_ifc_register_power_settings_bits { 11179 u8 reserved_at_0[0x18]; 11180 u8 power_settings_level[0x8]; 11181 11182 u8 reserved_at_20[0x60]; 11183 }; 11184 11185 struct mlx5_ifc_register_host_endianness_bits { 11186 u8 he[0x1]; 11187 u8 reserved_at_1[0x1f]; 11188 11189 u8 reserved_at_20[0x60]; 11190 }; 11191 11192 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11193 u8 reserved_at_0[0x20]; 11194 11195 u8 mkey[0x20]; 11196 11197 u8 addressh_63_32[0x20]; 11198 11199 u8 addressl_31_0[0x20]; 11200 }; 11201 11202 struct mlx5_ifc_ud_adrs_vector_bits { 11203 u8 dc_key[0x40]; 11204 11205 u8 ext[0x1]; 11206 u8 reserved_at_41[0x7]; 11207 u8 destination_qp_dct[0x18]; 11208 11209 u8 static_rate[0x4]; 11210 u8 sl_eth_prio[0x4]; 11211 u8 fl[0x1]; 11212 u8 mlid[0x7]; 11213 u8 rlid_udp_sport[0x10]; 11214 11215 u8 reserved_at_80[0x20]; 11216 11217 u8 rmac_47_16[0x20]; 11218 11219 u8 rmac_15_0[0x10]; 11220 u8 tclass[0x8]; 11221 u8 hop_limit[0x8]; 11222 11223 u8 reserved_at_e0[0x1]; 11224 u8 grh[0x1]; 11225 u8 reserved_at_e2[0x2]; 11226 u8 src_addr_index[0x8]; 11227 u8 flow_label[0x14]; 11228 11229 u8 rgid_rip[16][0x8]; 11230 }; 11231 11232 struct mlx5_ifc_pages_req_event_bits { 11233 u8 reserved_at_0[0x10]; 11234 u8 function_id[0x10]; 11235 11236 u8 num_pages[0x20]; 11237 11238 u8 reserved_at_40[0xa0]; 11239 }; 11240 11241 struct mlx5_ifc_eqe_bits { 11242 u8 reserved_at_0[0x8]; 11243 u8 event_type[0x8]; 11244 u8 reserved_at_10[0x8]; 11245 u8 event_sub_type[0x8]; 11246 11247 u8 reserved_at_20[0xe0]; 11248 11249 union mlx5_ifc_event_auto_bits event_data; 11250 11251 u8 reserved_at_1e0[0x10]; 11252 u8 signature[0x8]; 11253 u8 reserved_at_1f8[0x7]; 11254 u8 owner[0x1]; 11255 }; 11256 11257 enum { 11258 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11259 }; 11260 11261 struct mlx5_ifc_cmd_queue_entry_bits { 11262 u8 type[0x8]; 11263 u8 reserved_at_8[0x18]; 11264 11265 u8 input_length[0x20]; 11266 11267 u8 input_mailbox_pointer_63_32[0x20]; 11268 11269 u8 input_mailbox_pointer_31_9[0x17]; 11270 u8 reserved_at_77[0x9]; 11271 11272 u8 command_input_inline_data[16][0x8]; 11273 11274 u8 command_output_inline_data[16][0x8]; 11275 11276 u8 output_mailbox_pointer_63_32[0x20]; 11277 11278 u8 output_mailbox_pointer_31_9[0x17]; 11279 u8 reserved_at_1b7[0x9]; 11280 11281 u8 output_length[0x20]; 11282 11283 u8 token[0x8]; 11284 u8 signature[0x8]; 11285 u8 reserved_at_1f0[0x8]; 11286 u8 status[0x7]; 11287 u8 ownership[0x1]; 11288 }; 11289 11290 struct mlx5_ifc_cmd_out_bits { 11291 u8 status[0x8]; 11292 u8 reserved_at_8[0x18]; 11293 11294 u8 syndrome[0x20]; 11295 11296 u8 command_output[0x20]; 11297 }; 11298 11299 struct mlx5_ifc_cmd_in_bits { 11300 u8 opcode[0x10]; 11301 u8 reserved_at_10[0x10]; 11302 11303 u8 reserved_at_20[0x10]; 11304 u8 op_mod[0x10]; 11305 11306 u8 command[][0x20]; 11307 }; 11308 11309 struct mlx5_ifc_cmd_if_box_bits { 11310 u8 mailbox_data[512][0x8]; 11311 11312 u8 reserved_at_1000[0x180]; 11313 11314 u8 next_pointer_63_32[0x20]; 11315 11316 u8 next_pointer_31_10[0x16]; 11317 u8 reserved_at_11b6[0xa]; 11318 11319 u8 block_number[0x20]; 11320 11321 u8 reserved_at_11e0[0x8]; 11322 u8 token[0x8]; 11323 u8 ctrl_signature[0x8]; 11324 u8 signature[0x8]; 11325 }; 11326 11327 struct mlx5_ifc_mtt_bits { 11328 u8 ptag_63_32[0x20]; 11329 11330 u8 ptag_31_8[0x18]; 11331 u8 reserved_at_38[0x6]; 11332 u8 wr_en[0x1]; 11333 u8 rd_en[0x1]; 11334 }; 11335 11336 struct mlx5_ifc_query_wol_rol_out_bits { 11337 u8 status[0x8]; 11338 u8 reserved_at_8[0x18]; 11339 11340 u8 syndrome[0x20]; 11341 11342 u8 reserved_at_40[0x10]; 11343 u8 rol_mode[0x8]; 11344 u8 wol_mode[0x8]; 11345 11346 u8 reserved_at_60[0x20]; 11347 }; 11348 11349 struct mlx5_ifc_query_wol_rol_in_bits { 11350 u8 opcode[0x10]; 11351 u8 reserved_at_10[0x10]; 11352 11353 u8 reserved_at_20[0x10]; 11354 u8 op_mod[0x10]; 11355 11356 u8 reserved_at_40[0x40]; 11357 }; 11358 11359 struct mlx5_ifc_set_wol_rol_out_bits { 11360 u8 status[0x8]; 11361 u8 reserved_at_8[0x18]; 11362 11363 u8 syndrome[0x20]; 11364 11365 u8 reserved_at_40[0x40]; 11366 }; 11367 11368 struct mlx5_ifc_set_wol_rol_in_bits { 11369 u8 opcode[0x10]; 11370 u8 reserved_at_10[0x10]; 11371 11372 u8 reserved_at_20[0x10]; 11373 u8 op_mod[0x10]; 11374 11375 u8 rol_mode_valid[0x1]; 11376 u8 wol_mode_valid[0x1]; 11377 u8 reserved_at_42[0xe]; 11378 u8 rol_mode[0x8]; 11379 u8 wol_mode[0x8]; 11380 11381 u8 reserved_at_60[0x20]; 11382 }; 11383 11384 enum { 11385 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11386 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11387 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11388 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11389 }; 11390 11391 enum { 11392 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11393 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11394 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11395 }; 11396 11397 enum { 11398 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11399 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11400 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11401 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11402 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11403 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11404 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11405 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11406 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11407 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11408 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11409 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11410 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11411 }; 11412 11413 struct mlx5_ifc_initial_seg_bits { 11414 u8 fw_rev_minor[0x10]; 11415 u8 fw_rev_major[0x10]; 11416 11417 u8 cmd_interface_rev[0x10]; 11418 u8 fw_rev_subminor[0x10]; 11419 11420 u8 reserved_at_40[0x40]; 11421 11422 u8 cmdq_phy_addr_63_32[0x20]; 11423 11424 u8 cmdq_phy_addr_31_12[0x14]; 11425 u8 reserved_at_b4[0x2]; 11426 u8 nic_interface[0x2]; 11427 u8 log_cmdq_size[0x4]; 11428 u8 log_cmdq_stride[0x4]; 11429 11430 u8 command_doorbell_vector[0x20]; 11431 11432 u8 reserved_at_e0[0xf00]; 11433 11434 u8 initializing[0x1]; 11435 u8 reserved_at_fe1[0x4]; 11436 u8 nic_interface_supported[0x3]; 11437 u8 embedded_cpu[0x1]; 11438 u8 reserved_at_fe9[0x17]; 11439 11440 struct mlx5_ifc_health_buffer_bits health_buffer; 11441 11442 u8 no_dram_nic_offset[0x20]; 11443 11444 u8 reserved_at_1220[0x6e40]; 11445 11446 u8 reserved_at_8060[0x1f]; 11447 u8 clear_int[0x1]; 11448 11449 u8 health_syndrome[0x8]; 11450 u8 health_counter[0x18]; 11451 11452 u8 reserved_at_80a0[0x17fc0]; 11453 }; 11454 11455 struct mlx5_ifc_mtpps_reg_bits { 11456 u8 reserved_at_0[0xc]; 11457 u8 cap_number_of_pps_pins[0x4]; 11458 u8 reserved_at_10[0x4]; 11459 u8 cap_max_num_of_pps_in_pins[0x4]; 11460 u8 reserved_at_18[0x4]; 11461 u8 cap_max_num_of_pps_out_pins[0x4]; 11462 11463 u8 reserved_at_20[0x13]; 11464 u8 cap_log_min_npps_period[0x5]; 11465 u8 reserved_at_38[0x3]; 11466 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11467 11468 u8 reserved_at_40[0x4]; 11469 u8 cap_pin_3_mode[0x4]; 11470 u8 reserved_at_48[0x4]; 11471 u8 cap_pin_2_mode[0x4]; 11472 u8 reserved_at_50[0x4]; 11473 u8 cap_pin_1_mode[0x4]; 11474 u8 reserved_at_58[0x4]; 11475 u8 cap_pin_0_mode[0x4]; 11476 11477 u8 reserved_at_60[0x4]; 11478 u8 cap_pin_7_mode[0x4]; 11479 u8 reserved_at_68[0x4]; 11480 u8 cap_pin_6_mode[0x4]; 11481 u8 reserved_at_70[0x4]; 11482 u8 cap_pin_5_mode[0x4]; 11483 u8 reserved_at_78[0x4]; 11484 u8 cap_pin_4_mode[0x4]; 11485 11486 u8 field_select[0x20]; 11487 u8 reserved_at_a0[0x20]; 11488 11489 u8 npps_period[0x40]; 11490 11491 u8 enable[0x1]; 11492 u8 reserved_at_101[0xb]; 11493 u8 pattern[0x4]; 11494 u8 reserved_at_110[0x4]; 11495 u8 pin_mode[0x4]; 11496 u8 pin[0x8]; 11497 11498 u8 reserved_at_120[0x2]; 11499 u8 out_pulse_duration_ns[0x1e]; 11500 11501 u8 time_stamp[0x40]; 11502 11503 u8 out_pulse_duration[0x10]; 11504 u8 out_periodic_adjustment[0x10]; 11505 u8 enhanced_out_periodic_adjustment[0x20]; 11506 11507 u8 reserved_at_1c0[0x20]; 11508 }; 11509 11510 struct mlx5_ifc_mtppse_reg_bits { 11511 u8 reserved_at_0[0x18]; 11512 u8 pin[0x8]; 11513 u8 event_arm[0x1]; 11514 u8 reserved_at_21[0x1b]; 11515 u8 event_generation_mode[0x4]; 11516 u8 reserved_at_40[0x40]; 11517 }; 11518 11519 struct mlx5_ifc_mcqs_reg_bits { 11520 u8 last_index_flag[0x1]; 11521 u8 reserved_at_1[0x7]; 11522 u8 fw_device[0x8]; 11523 u8 component_index[0x10]; 11524 11525 u8 reserved_at_20[0x10]; 11526 u8 identifier[0x10]; 11527 11528 u8 reserved_at_40[0x17]; 11529 u8 component_status[0x5]; 11530 u8 component_update_state[0x4]; 11531 11532 u8 last_update_state_changer_type[0x4]; 11533 u8 last_update_state_changer_host_id[0x4]; 11534 u8 reserved_at_68[0x18]; 11535 }; 11536 11537 struct mlx5_ifc_mcqi_cap_bits { 11538 u8 supported_info_bitmask[0x20]; 11539 11540 u8 component_size[0x20]; 11541 11542 u8 max_component_size[0x20]; 11543 11544 u8 log_mcda_word_size[0x4]; 11545 u8 reserved_at_64[0xc]; 11546 u8 mcda_max_write_size[0x10]; 11547 11548 u8 rd_en[0x1]; 11549 u8 reserved_at_81[0x1]; 11550 u8 match_chip_id[0x1]; 11551 u8 match_psid[0x1]; 11552 u8 check_user_timestamp[0x1]; 11553 u8 match_base_guid_mac[0x1]; 11554 u8 reserved_at_86[0x1a]; 11555 }; 11556 11557 struct mlx5_ifc_mcqi_version_bits { 11558 u8 reserved_at_0[0x2]; 11559 u8 build_time_valid[0x1]; 11560 u8 user_defined_time_valid[0x1]; 11561 u8 reserved_at_4[0x14]; 11562 u8 version_string_length[0x8]; 11563 11564 u8 version[0x20]; 11565 11566 u8 build_time[0x40]; 11567 11568 u8 user_defined_time[0x40]; 11569 11570 u8 build_tool_version[0x20]; 11571 11572 u8 reserved_at_e0[0x20]; 11573 11574 u8 version_string[92][0x8]; 11575 }; 11576 11577 struct mlx5_ifc_mcqi_activation_method_bits { 11578 u8 pending_server_ac_power_cycle[0x1]; 11579 u8 pending_server_dc_power_cycle[0x1]; 11580 u8 pending_server_reboot[0x1]; 11581 u8 pending_fw_reset[0x1]; 11582 u8 auto_activate[0x1]; 11583 u8 all_hosts_sync[0x1]; 11584 u8 device_hw_reset[0x1]; 11585 u8 reserved_at_7[0x19]; 11586 }; 11587 11588 union mlx5_ifc_mcqi_reg_data_bits { 11589 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11590 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11591 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11592 }; 11593 11594 struct mlx5_ifc_mcqi_reg_bits { 11595 u8 read_pending_component[0x1]; 11596 u8 reserved_at_1[0xf]; 11597 u8 component_index[0x10]; 11598 11599 u8 reserved_at_20[0x20]; 11600 11601 u8 reserved_at_40[0x1b]; 11602 u8 info_type[0x5]; 11603 11604 u8 info_size[0x20]; 11605 11606 u8 offset[0x20]; 11607 11608 u8 reserved_at_a0[0x10]; 11609 u8 data_size[0x10]; 11610 11611 union mlx5_ifc_mcqi_reg_data_bits data[]; 11612 }; 11613 11614 struct mlx5_ifc_mcc_reg_bits { 11615 u8 reserved_at_0[0x4]; 11616 u8 time_elapsed_since_last_cmd[0xc]; 11617 u8 reserved_at_10[0x8]; 11618 u8 instruction[0x8]; 11619 11620 u8 reserved_at_20[0x10]; 11621 u8 component_index[0x10]; 11622 11623 u8 reserved_at_40[0x8]; 11624 u8 update_handle[0x18]; 11625 11626 u8 handle_owner_type[0x4]; 11627 u8 handle_owner_host_id[0x4]; 11628 u8 reserved_at_68[0x1]; 11629 u8 control_progress[0x7]; 11630 u8 error_code[0x8]; 11631 u8 reserved_at_78[0x4]; 11632 u8 control_state[0x4]; 11633 11634 u8 component_size[0x20]; 11635 11636 u8 reserved_at_a0[0x60]; 11637 }; 11638 11639 struct mlx5_ifc_mcda_reg_bits { 11640 u8 reserved_at_0[0x8]; 11641 u8 update_handle[0x18]; 11642 11643 u8 offset[0x20]; 11644 11645 u8 reserved_at_40[0x10]; 11646 u8 size[0x10]; 11647 11648 u8 reserved_at_60[0x20]; 11649 11650 u8 data[][0x20]; 11651 }; 11652 11653 enum { 11654 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11655 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11656 }; 11657 11658 enum { 11659 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11660 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11661 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11662 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11663 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11664 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11665 }; 11666 11667 enum { 11668 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11669 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11670 }; 11671 11672 enum { 11673 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11674 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11675 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11676 }; 11677 11678 struct mlx5_ifc_mfrl_reg_bits { 11679 u8 reserved_at_0[0x20]; 11680 11681 u8 reserved_at_20[0x2]; 11682 u8 pci_sync_for_fw_update_start[0x1]; 11683 u8 pci_sync_for_fw_update_resp[0x2]; 11684 u8 rst_type_sel[0x3]; 11685 u8 pci_reset_req_method[0x3]; 11686 u8 reserved_at_2b[0x1]; 11687 u8 reset_state[0x4]; 11688 u8 reset_type[0x8]; 11689 u8 reset_level[0x8]; 11690 }; 11691 11692 struct mlx5_ifc_mirc_reg_bits { 11693 u8 reserved_at_0[0x18]; 11694 u8 status_code[0x8]; 11695 11696 u8 reserved_at_20[0x20]; 11697 }; 11698 11699 struct mlx5_ifc_pddr_monitor_opcode_bits { 11700 u8 reserved_at_0[0x10]; 11701 u8 monitor_opcode[0x10]; 11702 }; 11703 11704 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11705 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11706 u8 reserved_at_0[0x20]; 11707 }; 11708 11709 enum { 11710 /* Monitor opcodes */ 11711 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11712 }; 11713 11714 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11715 u8 reserved_at_0[0x10]; 11716 u8 group_opcode[0x10]; 11717 11718 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11719 11720 u8 reserved_at_40[0x20]; 11721 11722 u8 status_message[59][0x20]; 11723 }; 11724 11725 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11726 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11727 u8 reserved_at_0[0x7c0]; 11728 }; 11729 11730 enum { 11731 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11732 }; 11733 11734 struct mlx5_ifc_pddr_reg_bits { 11735 u8 reserved_at_0[0x8]; 11736 u8 local_port[0x8]; 11737 u8 pnat[0x2]; 11738 u8 reserved_at_12[0xe]; 11739 11740 u8 reserved_at_20[0x18]; 11741 u8 page_select[0x8]; 11742 11743 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11744 }; 11745 11746 struct mlx5_ifc_mrtc_reg_bits { 11747 u8 time_synced[0x1]; 11748 u8 reserved_at_1[0x1f]; 11749 11750 u8 reserved_at_20[0x20]; 11751 11752 u8 time_h[0x20]; 11753 11754 u8 time_l[0x20]; 11755 }; 11756 11757 struct mlx5_ifc_mtcap_reg_bits { 11758 u8 reserved_at_0[0x19]; 11759 u8 sensor_count[0x7]; 11760 11761 u8 reserved_at_20[0x20]; 11762 11763 u8 sensor_map[0x40]; 11764 }; 11765 11766 struct mlx5_ifc_mtmp_reg_bits { 11767 u8 reserved_at_0[0x14]; 11768 u8 sensor_index[0xc]; 11769 11770 u8 reserved_at_20[0x10]; 11771 u8 temperature[0x10]; 11772 11773 u8 mte[0x1]; 11774 u8 mtr[0x1]; 11775 u8 reserved_at_42[0xe]; 11776 u8 max_temperature[0x10]; 11777 11778 u8 tee[0x2]; 11779 u8 reserved_at_62[0xe]; 11780 u8 temp_threshold_hi[0x10]; 11781 11782 u8 reserved_at_80[0x10]; 11783 u8 temp_threshold_lo[0x10]; 11784 11785 u8 reserved_at_a0[0x20]; 11786 11787 u8 sensor_name_hi[0x20]; 11788 u8 sensor_name_lo[0x20]; 11789 }; 11790 11791 struct mlx5_ifc_mtptm_reg_bits { 11792 u8 reserved_at_0[0x10]; 11793 u8 psta[0x1]; 11794 u8 reserved_at_11[0xf]; 11795 11796 u8 reserved_at_20[0x60]; 11797 }; 11798 11799 enum { 11800 MLX5_MTCTR_REQUEST_NOP = 0x0, 11801 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11802 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11803 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11804 }; 11805 11806 struct mlx5_ifc_mtctr_reg_bits { 11807 u8 first_clock_timestamp_request[0x8]; 11808 u8 second_clock_timestamp_request[0x8]; 11809 u8 reserved_at_10[0x10]; 11810 11811 u8 first_clock_valid[0x1]; 11812 u8 second_clock_valid[0x1]; 11813 u8 reserved_at_22[0x1e]; 11814 11815 u8 first_clock_timestamp[0x40]; 11816 u8 second_clock_timestamp[0x40]; 11817 }; 11818 11819 struct mlx5_ifc_bin_range_layout_bits { 11820 u8 reserved_at_0[0xa]; 11821 u8 high_val[0x6]; 11822 u8 reserved_at_10[0xa]; 11823 u8 low_val[0x6]; 11824 }; 11825 11826 struct mlx5_ifc_pphcr_reg_bits { 11827 u8 active_hist_type[0x4]; 11828 u8 reserved_at_4[0x4]; 11829 u8 local_port[0x8]; 11830 u8 reserved_at_10[0x10]; 11831 11832 u8 reserved_at_20[0x8]; 11833 u8 num_of_bins[0x8]; 11834 u8 reserved_at_30[0x10]; 11835 11836 u8 reserved_at_40[0x40]; 11837 11838 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11839 }; 11840 11841 union mlx5_ifc_ports_control_registers_document_bits { 11842 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11843 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11844 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11845 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11846 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11847 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11848 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11849 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11850 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11851 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11852 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11853 struct mlx5_ifc_paos_reg_bits paos_reg; 11854 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11855 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11856 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11857 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11858 struct mlx5_ifc_peir_reg_bits peir_reg; 11859 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11860 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11861 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11862 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11863 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11864 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11865 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11866 struct mlx5_ifc_plib_reg_bits plib_reg; 11867 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11868 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11869 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11870 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11871 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11872 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11873 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11874 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11875 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11876 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11877 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11878 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11879 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11880 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11881 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11882 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11883 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11884 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11885 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11886 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11887 struct mlx5_ifc_pude_reg_bits pude_reg; 11888 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11889 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11890 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11891 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11892 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11893 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11894 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11895 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11896 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11897 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11898 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11899 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11900 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11901 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11902 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11903 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11904 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11905 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11906 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11907 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11908 u8 reserved_at_0[0x60e0]; 11909 }; 11910 11911 union mlx5_ifc_debug_enhancements_document_bits { 11912 struct mlx5_ifc_health_buffer_bits health_buffer; 11913 u8 reserved_at_0[0x200]; 11914 }; 11915 11916 union mlx5_ifc_uplink_pci_interface_document_bits { 11917 struct mlx5_ifc_initial_seg_bits initial_seg; 11918 u8 reserved_at_0[0x20060]; 11919 }; 11920 11921 struct mlx5_ifc_set_flow_table_root_out_bits { 11922 u8 status[0x8]; 11923 u8 reserved_at_8[0x18]; 11924 11925 u8 syndrome[0x20]; 11926 11927 u8 reserved_at_40[0x40]; 11928 }; 11929 11930 struct mlx5_ifc_set_flow_table_root_in_bits { 11931 u8 opcode[0x10]; 11932 u8 reserved_at_10[0x10]; 11933 11934 u8 reserved_at_20[0x10]; 11935 u8 op_mod[0x10]; 11936 11937 u8 other_vport[0x1]; 11938 u8 other_eswitch[0x1]; 11939 u8 reserved_at_42[0xe]; 11940 u8 vport_number[0x10]; 11941 11942 u8 reserved_at_60[0x10]; 11943 u8 eswitch_owner_vhca_id[0x10]; 11944 11945 u8 table_type[0x8]; 11946 u8 reserved_at_88[0x7]; 11947 u8 table_of_other_vport[0x1]; 11948 u8 table_vport_number[0x10]; 11949 11950 u8 reserved_at_a0[0x8]; 11951 u8 table_id[0x18]; 11952 11953 u8 reserved_at_c0[0x8]; 11954 u8 underlay_qpn[0x18]; 11955 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11956 u8 reserved_at_e1[0xf]; 11957 u8 table_eswitch_owner_vhca_id[0x10]; 11958 u8 reserved_at_100[0x100]; 11959 }; 11960 11961 enum { 11962 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11963 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11964 }; 11965 11966 struct mlx5_ifc_modify_flow_table_out_bits { 11967 u8 status[0x8]; 11968 u8 reserved_at_8[0x18]; 11969 11970 u8 syndrome[0x20]; 11971 11972 u8 reserved_at_40[0x40]; 11973 }; 11974 11975 struct mlx5_ifc_modify_flow_table_in_bits { 11976 u8 opcode[0x10]; 11977 u8 reserved_at_10[0x10]; 11978 11979 u8 reserved_at_20[0x10]; 11980 u8 op_mod[0x10]; 11981 11982 u8 other_vport[0x1]; 11983 u8 other_eswitch[0x1]; 11984 u8 reserved_at_42[0xe]; 11985 u8 vport_number[0x10]; 11986 11987 u8 reserved_at_60[0x10]; 11988 u8 modify_field_select[0x10]; 11989 11990 u8 table_type[0x8]; 11991 u8 reserved_at_88[0x8]; 11992 u8 eswitch_owner_vhca_id[0x10]; 11993 11994 u8 reserved_at_a0[0x8]; 11995 u8 table_id[0x18]; 11996 11997 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11998 }; 11999 12000 struct mlx5_ifc_ets_tcn_config_reg_bits { 12001 u8 g[0x1]; 12002 u8 b[0x1]; 12003 u8 r[0x1]; 12004 u8 reserved_at_3[0x9]; 12005 u8 group[0x4]; 12006 u8 reserved_at_10[0x9]; 12007 u8 bw_allocation[0x7]; 12008 12009 u8 reserved_at_20[0xc]; 12010 u8 max_bw_units[0x4]; 12011 u8 max_bw_value[0x10]; 12012 }; 12013 12014 struct mlx5_ifc_ets_global_config_reg_bits { 12015 u8 reserved_at_0[0x2]; 12016 u8 r[0x1]; 12017 u8 reserved_at_3[0x1d]; 12018 12019 u8 reserved_at_20[0xc]; 12020 u8 max_bw_units[0x4]; 12021 u8 reserved_at_30[0x8]; 12022 u8 max_bw_value[0x8]; 12023 }; 12024 12025 struct mlx5_ifc_qetc_reg_bits { 12026 u8 reserved_at_0[0x8]; 12027 u8 port_number[0x8]; 12028 u8 reserved_at_10[0x30]; 12029 12030 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 12031 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 12032 }; 12033 12034 struct mlx5_ifc_qpdpm_dscp_reg_bits { 12035 u8 e[0x1]; 12036 u8 reserved_at_01[0x0b]; 12037 u8 prio[0x04]; 12038 }; 12039 12040 struct mlx5_ifc_qpdpm_reg_bits { 12041 u8 reserved_at_0[0x8]; 12042 u8 local_port[0x8]; 12043 u8 reserved_at_10[0x10]; 12044 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 12045 }; 12046 12047 struct mlx5_ifc_qpts_reg_bits { 12048 u8 reserved_at_0[0x8]; 12049 u8 local_port[0x8]; 12050 u8 reserved_at_10[0x2d]; 12051 u8 trust_state[0x3]; 12052 }; 12053 12054 struct mlx5_ifc_pptb_reg_bits { 12055 u8 reserved_at_0[0x2]; 12056 u8 mm[0x2]; 12057 u8 reserved_at_4[0x4]; 12058 u8 local_port[0x8]; 12059 u8 reserved_at_10[0x6]; 12060 u8 cm[0x1]; 12061 u8 um[0x1]; 12062 u8 pm[0x8]; 12063 12064 u8 prio_x_buff[0x20]; 12065 12066 u8 pm_msb[0x8]; 12067 u8 reserved_at_48[0x10]; 12068 u8 ctrl_buff[0x4]; 12069 u8 untagged_buff[0x4]; 12070 }; 12071 12072 struct mlx5_ifc_sbcam_reg_bits { 12073 u8 reserved_at_0[0x8]; 12074 u8 feature_group[0x8]; 12075 u8 reserved_at_10[0x8]; 12076 u8 access_reg_group[0x8]; 12077 12078 u8 reserved_at_20[0x20]; 12079 12080 u8 sb_access_reg_cap_mask[4][0x20]; 12081 12082 u8 reserved_at_c0[0x80]; 12083 12084 u8 sb_feature_cap_mask[4][0x20]; 12085 12086 u8 reserved_at_1c0[0x40]; 12087 12088 u8 cap_total_buffer_size[0x20]; 12089 12090 u8 cap_cell_size[0x10]; 12091 u8 cap_max_pg_buffers[0x8]; 12092 u8 cap_num_pool_supported[0x8]; 12093 12094 u8 reserved_at_240[0x8]; 12095 u8 cap_sbsr_stat_size[0x8]; 12096 u8 cap_max_tclass_data[0x8]; 12097 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12098 }; 12099 12100 struct mlx5_ifc_pbmc_reg_bits { 12101 u8 reserved_at_0[0x8]; 12102 u8 local_port[0x8]; 12103 u8 reserved_at_10[0x10]; 12104 12105 u8 xoff_timer_value[0x10]; 12106 u8 xoff_refresh[0x10]; 12107 12108 u8 reserved_at_40[0x9]; 12109 u8 fullness_threshold[0x7]; 12110 u8 port_buffer_size[0x10]; 12111 12112 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12113 struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool; 12114 12115 u8 reserved_at_320[0x40]; 12116 }; 12117 12118 struct mlx5_ifc_sbpr_reg_bits { 12119 u8 desc[0x1]; 12120 u8 snap[0x1]; 12121 u8 reserved_at_2[0x4]; 12122 u8 dir[0x2]; 12123 u8 reserved_at_8[0x14]; 12124 u8 pool[0x4]; 12125 12126 u8 infi_size[0x1]; 12127 u8 reserved_at_21[0x7]; 12128 u8 size[0x18]; 12129 12130 u8 reserved_at_40[0x1c]; 12131 u8 mode[0x4]; 12132 12133 u8 reserved_at_60[0x8]; 12134 u8 buff_occupancy[0x18]; 12135 12136 u8 clr[0x1]; 12137 u8 reserved_at_81[0x7]; 12138 u8 max_buff_occupancy[0x18]; 12139 12140 u8 reserved_at_a0[0x8]; 12141 u8 ext_buff_occupancy[0x18]; 12142 }; 12143 12144 struct mlx5_ifc_sbcm_reg_bits { 12145 u8 desc[0x1]; 12146 u8 snap[0x1]; 12147 u8 reserved_at_2[0x6]; 12148 u8 local_port[0x8]; 12149 u8 pnat[0x2]; 12150 u8 pg_buff[0x6]; 12151 u8 reserved_at_18[0x6]; 12152 u8 dir[0x2]; 12153 12154 u8 reserved_at_20[0x1f]; 12155 u8 exc[0x1]; 12156 12157 u8 reserved_at_40[0x40]; 12158 12159 u8 reserved_at_80[0x8]; 12160 u8 buff_occupancy[0x18]; 12161 12162 u8 clr[0x1]; 12163 u8 reserved_at_a1[0x7]; 12164 u8 max_buff_occupancy[0x18]; 12165 12166 u8 reserved_at_c0[0x8]; 12167 u8 min_buff[0x18]; 12168 12169 u8 infi_max[0x1]; 12170 u8 reserved_at_e1[0x7]; 12171 u8 max_buff[0x18]; 12172 12173 u8 reserved_at_100[0x20]; 12174 12175 u8 reserved_at_120[0x1c]; 12176 u8 pool[0x4]; 12177 }; 12178 12179 struct mlx5_ifc_qtct_reg_bits { 12180 u8 reserved_at_0[0x8]; 12181 u8 port_number[0x8]; 12182 u8 reserved_at_10[0xd]; 12183 u8 prio[0x3]; 12184 12185 u8 reserved_at_20[0x1d]; 12186 u8 tclass[0x3]; 12187 }; 12188 12189 struct mlx5_ifc_mcia_reg_bits { 12190 u8 l[0x1]; 12191 u8 reserved_at_1[0x7]; 12192 u8 module[0x8]; 12193 u8 reserved_at_10[0x8]; 12194 u8 status[0x8]; 12195 12196 u8 i2c_device_address[0x8]; 12197 u8 page_number[0x8]; 12198 u8 device_address[0x10]; 12199 12200 u8 reserved_at_40[0x10]; 12201 u8 size[0x10]; 12202 12203 u8 reserved_at_60[0x20]; 12204 12205 u8 dword_0[0x20]; 12206 u8 dword_1[0x20]; 12207 u8 dword_2[0x20]; 12208 u8 dword_3[0x20]; 12209 u8 dword_4[0x20]; 12210 u8 dword_5[0x20]; 12211 u8 dword_6[0x20]; 12212 u8 dword_7[0x20]; 12213 u8 dword_8[0x20]; 12214 u8 dword_9[0x20]; 12215 u8 dword_10[0x20]; 12216 u8 dword_11[0x20]; 12217 }; 12218 12219 struct mlx5_ifc_dcbx_param_bits { 12220 u8 dcbx_cee_cap[0x1]; 12221 u8 dcbx_ieee_cap[0x1]; 12222 u8 dcbx_standby_cap[0x1]; 12223 u8 reserved_at_3[0x5]; 12224 u8 port_number[0x8]; 12225 u8 reserved_at_10[0xa]; 12226 u8 max_application_table_size[6]; 12227 u8 reserved_at_20[0x15]; 12228 u8 version_oper[0x3]; 12229 u8 reserved_at_38[5]; 12230 u8 version_admin[0x3]; 12231 u8 willing_admin[0x1]; 12232 u8 reserved_at_41[0x3]; 12233 u8 pfc_cap_oper[0x4]; 12234 u8 reserved_at_48[0x4]; 12235 u8 pfc_cap_admin[0x4]; 12236 u8 reserved_at_50[0x4]; 12237 u8 num_of_tc_oper[0x4]; 12238 u8 reserved_at_58[0x4]; 12239 u8 num_of_tc_admin[0x4]; 12240 u8 remote_willing[0x1]; 12241 u8 reserved_at_61[3]; 12242 u8 remote_pfc_cap[4]; 12243 u8 reserved_at_68[0x14]; 12244 u8 remote_num_of_tc[0x4]; 12245 u8 reserved_at_80[0x18]; 12246 u8 error[0x8]; 12247 u8 reserved_at_a0[0x160]; 12248 }; 12249 12250 enum { 12251 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12252 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12253 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12254 }; 12255 12256 struct mlx5_ifc_lagc_bits { 12257 u8 fdb_selection_mode[0x1]; 12258 u8 reserved_at_1[0x14]; 12259 u8 port_select_mode[0x3]; 12260 u8 reserved_at_18[0x5]; 12261 u8 lag_state[0x3]; 12262 12263 u8 reserved_at_20[0xc]; 12264 u8 active_port[0x4]; 12265 u8 reserved_at_30[0x4]; 12266 u8 tx_remap_affinity_2[0x4]; 12267 u8 reserved_at_38[0x4]; 12268 u8 tx_remap_affinity_1[0x4]; 12269 }; 12270 12271 struct mlx5_ifc_create_lag_out_bits { 12272 u8 status[0x8]; 12273 u8 reserved_at_8[0x18]; 12274 12275 u8 syndrome[0x20]; 12276 12277 u8 reserved_at_40[0x40]; 12278 }; 12279 12280 struct mlx5_ifc_create_lag_in_bits { 12281 u8 opcode[0x10]; 12282 u8 reserved_at_10[0x10]; 12283 12284 u8 reserved_at_20[0x10]; 12285 u8 op_mod[0x10]; 12286 12287 struct mlx5_ifc_lagc_bits ctx; 12288 }; 12289 12290 struct mlx5_ifc_modify_lag_out_bits { 12291 u8 status[0x8]; 12292 u8 reserved_at_8[0x18]; 12293 12294 u8 syndrome[0x20]; 12295 12296 u8 reserved_at_40[0x40]; 12297 }; 12298 12299 struct mlx5_ifc_modify_lag_in_bits { 12300 u8 opcode[0x10]; 12301 u8 reserved_at_10[0x10]; 12302 12303 u8 reserved_at_20[0x10]; 12304 u8 op_mod[0x10]; 12305 12306 u8 reserved_at_40[0x20]; 12307 u8 field_select[0x20]; 12308 12309 struct mlx5_ifc_lagc_bits ctx; 12310 }; 12311 12312 struct mlx5_ifc_query_lag_out_bits { 12313 u8 status[0x8]; 12314 u8 reserved_at_8[0x18]; 12315 12316 u8 syndrome[0x20]; 12317 12318 struct mlx5_ifc_lagc_bits ctx; 12319 }; 12320 12321 struct mlx5_ifc_query_lag_in_bits { 12322 u8 opcode[0x10]; 12323 u8 reserved_at_10[0x10]; 12324 12325 u8 reserved_at_20[0x10]; 12326 u8 op_mod[0x10]; 12327 12328 u8 reserved_at_40[0x40]; 12329 }; 12330 12331 struct mlx5_ifc_destroy_lag_out_bits { 12332 u8 status[0x8]; 12333 u8 reserved_at_8[0x18]; 12334 12335 u8 syndrome[0x20]; 12336 12337 u8 reserved_at_40[0x40]; 12338 }; 12339 12340 struct mlx5_ifc_destroy_lag_in_bits { 12341 u8 opcode[0x10]; 12342 u8 reserved_at_10[0x10]; 12343 12344 u8 reserved_at_20[0x10]; 12345 u8 op_mod[0x10]; 12346 12347 u8 reserved_at_40[0x40]; 12348 }; 12349 12350 struct mlx5_ifc_create_vport_lag_out_bits { 12351 u8 status[0x8]; 12352 u8 reserved_at_8[0x18]; 12353 12354 u8 syndrome[0x20]; 12355 12356 u8 reserved_at_40[0x40]; 12357 }; 12358 12359 struct mlx5_ifc_create_vport_lag_in_bits { 12360 u8 opcode[0x10]; 12361 u8 reserved_at_10[0x10]; 12362 12363 u8 reserved_at_20[0x10]; 12364 u8 op_mod[0x10]; 12365 12366 u8 reserved_at_40[0x40]; 12367 }; 12368 12369 struct mlx5_ifc_destroy_vport_lag_out_bits { 12370 u8 status[0x8]; 12371 u8 reserved_at_8[0x18]; 12372 12373 u8 syndrome[0x20]; 12374 12375 u8 reserved_at_40[0x40]; 12376 }; 12377 12378 struct mlx5_ifc_destroy_vport_lag_in_bits { 12379 u8 opcode[0x10]; 12380 u8 reserved_at_10[0x10]; 12381 12382 u8 reserved_at_20[0x10]; 12383 u8 op_mod[0x10]; 12384 12385 u8 reserved_at_40[0x40]; 12386 }; 12387 12388 enum { 12389 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12390 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12391 }; 12392 12393 struct mlx5_ifc_modify_memic_in_bits { 12394 u8 opcode[0x10]; 12395 u8 uid[0x10]; 12396 12397 u8 reserved_at_20[0x10]; 12398 u8 op_mod[0x10]; 12399 12400 u8 reserved_at_40[0x20]; 12401 12402 u8 reserved_at_60[0x18]; 12403 u8 memic_operation_type[0x8]; 12404 12405 u8 memic_start_addr[0x40]; 12406 12407 u8 reserved_at_c0[0x140]; 12408 }; 12409 12410 struct mlx5_ifc_modify_memic_out_bits { 12411 u8 status[0x8]; 12412 u8 reserved_at_8[0x18]; 12413 12414 u8 syndrome[0x20]; 12415 12416 u8 reserved_at_40[0x40]; 12417 12418 u8 memic_operation_addr[0x40]; 12419 12420 u8 reserved_at_c0[0x140]; 12421 }; 12422 12423 struct mlx5_ifc_alloc_memic_in_bits { 12424 u8 opcode[0x10]; 12425 u8 reserved_at_10[0x10]; 12426 12427 u8 reserved_at_20[0x10]; 12428 u8 op_mod[0x10]; 12429 12430 u8 reserved_at_30[0x20]; 12431 12432 u8 reserved_at_40[0x18]; 12433 u8 log_memic_addr_alignment[0x8]; 12434 12435 u8 range_start_addr[0x40]; 12436 12437 u8 range_size[0x20]; 12438 12439 u8 memic_size[0x20]; 12440 }; 12441 12442 struct mlx5_ifc_alloc_memic_out_bits { 12443 u8 status[0x8]; 12444 u8 reserved_at_8[0x18]; 12445 12446 u8 syndrome[0x20]; 12447 12448 u8 memic_start_addr[0x40]; 12449 }; 12450 12451 struct mlx5_ifc_dealloc_memic_in_bits { 12452 u8 opcode[0x10]; 12453 u8 reserved_at_10[0x10]; 12454 12455 u8 reserved_at_20[0x10]; 12456 u8 op_mod[0x10]; 12457 12458 u8 reserved_at_40[0x40]; 12459 12460 u8 memic_start_addr[0x40]; 12461 12462 u8 memic_size[0x20]; 12463 12464 u8 reserved_at_e0[0x20]; 12465 }; 12466 12467 struct mlx5_ifc_dealloc_memic_out_bits { 12468 u8 status[0x8]; 12469 u8 reserved_at_8[0x18]; 12470 12471 u8 syndrome[0x20]; 12472 12473 u8 reserved_at_40[0x40]; 12474 }; 12475 12476 struct mlx5_ifc_umem_bits { 12477 u8 reserved_at_0[0x80]; 12478 12479 u8 ats[0x1]; 12480 u8 reserved_at_81[0x1a]; 12481 u8 log_page_size[0x5]; 12482 12483 u8 page_offset[0x20]; 12484 12485 u8 num_of_mtt[0x40]; 12486 12487 struct mlx5_ifc_mtt_bits mtt[]; 12488 }; 12489 12490 struct mlx5_ifc_uctx_bits { 12491 u8 cap[0x20]; 12492 12493 u8 reserved_at_20[0x160]; 12494 }; 12495 12496 struct mlx5_ifc_sw_icm_bits { 12497 u8 modify_field_select[0x40]; 12498 12499 u8 reserved_at_40[0x18]; 12500 u8 log_sw_icm_size[0x8]; 12501 12502 u8 reserved_at_60[0x20]; 12503 12504 u8 sw_icm_start_addr[0x40]; 12505 12506 u8 reserved_at_c0[0x140]; 12507 }; 12508 12509 struct mlx5_ifc_geneve_tlv_option_bits { 12510 u8 modify_field_select[0x40]; 12511 12512 u8 reserved_at_40[0x18]; 12513 u8 geneve_option_fte_index[0x8]; 12514 12515 u8 option_class[0x10]; 12516 u8 option_type[0x8]; 12517 u8 reserved_at_78[0x3]; 12518 u8 option_data_length[0x5]; 12519 12520 u8 reserved_at_80[0x180]; 12521 }; 12522 12523 struct mlx5_ifc_create_umem_in_bits { 12524 u8 opcode[0x10]; 12525 u8 uid[0x10]; 12526 12527 u8 reserved_at_20[0x10]; 12528 u8 op_mod[0x10]; 12529 12530 u8 reserved_at_40[0x40]; 12531 12532 struct mlx5_ifc_umem_bits umem; 12533 }; 12534 12535 struct mlx5_ifc_create_umem_out_bits { 12536 u8 status[0x8]; 12537 u8 reserved_at_8[0x18]; 12538 12539 u8 syndrome[0x20]; 12540 12541 u8 reserved_at_40[0x8]; 12542 u8 umem_id[0x18]; 12543 12544 u8 reserved_at_60[0x20]; 12545 }; 12546 12547 struct mlx5_ifc_destroy_umem_in_bits { 12548 u8 opcode[0x10]; 12549 u8 uid[0x10]; 12550 12551 u8 reserved_at_20[0x10]; 12552 u8 op_mod[0x10]; 12553 12554 u8 reserved_at_40[0x8]; 12555 u8 umem_id[0x18]; 12556 12557 u8 reserved_at_60[0x20]; 12558 }; 12559 12560 struct mlx5_ifc_destroy_umem_out_bits { 12561 u8 status[0x8]; 12562 u8 reserved_at_8[0x18]; 12563 12564 u8 syndrome[0x20]; 12565 12566 u8 reserved_at_40[0x40]; 12567 }; 12568 12569 struct mlx5_ifc_create_uctx_in_bits { 12570 u8 opcode[0x10]; 12571 u8 reserved_at_10[0x10]; 12572 12573 u8 reserved_at_20[0x10]; 12574 u8 op_mod[0x10]; 12575 12576 u8 reserved_at_40[0x40]; 12577 12578 struct mlx5_ifc_uctx_bits uctx; 12579 }; 12580 12581 struct mlx5_ifc_create_uctx_out_bits { 12582 u8 status[0x8]; 12583 u8 reserved_at_8[0x18]; 12584 12585 u8 syndrome[0x20]; 12586 12587 u8 reserved_at_40[0x10]; 12588 u8 uid[0x10]; 12589 12590 u8 reserved_at_60[0x20]; 12591 }; 12592 12593 struct mlx5_ifc_destroy_uctx_in_bits { 12594 u8 opcode[0x10]; 12595 u8 reserved_at_10[0x10]; 12596 12597 u8 reserved_at_20[0x10]; 12598 u8 op_mod[0x10]; 12599 12600 u8 reserved_at_40[0x10]; 12601 u8 uid[0x10]; 12602 12603 u8 reserved_at_60[0x20]; 12604 }; 12605 12606 struct mlx5_ifc_destroy_uctx_out_bits { 12607 u8 status[0x8]; 12608 u8 reserved_at_8[0x18]; 12609 12610 u8 syndrome[0x20]; 12611 12612 u8 reserved_at_40[0x40]; 12613 }; 12614 12615 struct mlx5_ifc_create_sw_icm_in_bits { 12616 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12617 struct mlx5_ifc_sw_icm_bits sw_icm; 12618 }; 12619 12620 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12621 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12622 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12623 }; 12624 12625 struct mlx5_ifc_mtrc_string_db_param_bits { 12626 u8 string_db_base_address[0x20]; 12627 12628 u8 reserved_at_20[0x8]; 12629 u8 string_db_size[0x18]; 12630 }; 12631 12632 struct mlx5_ifc_mtrc_cap_bits { 12633 u8 trace_owner[0x1]; 12634 u8 trace_to_memory[0x1]; 12635 u8 reserved_at_2[0x4]; 12636 u8 trc_ver[0x2]; 12637 u8 reserved_at_8[0x14]; 12638 u8 num_string_db[0x4]; 12639 12640 u8 first_string_trace[0x8]; 12641 u8 num_string_trace[0x8]; 12642 u8 reserved_at_30[0x28]; 12643 12644 u8 log_max_trace_buffer_size[0x8]; 12645 12646 u8 reserved_at_60[0x20]; 12647 12648 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12649 12650 u8 reserved_at_280[0x180]; 12651 }; 12652 12653 struct mlx5_ifc_mtrc_conf_bits { 12654 u8 reserved_at_0[0x1c]; 12655 u8 trace_mode[0x4]; 12656 u8 reserved_at_20[0x18]; 12657 u8 log_trace_buffer_size[0x8]; 12658 u8 trace_mkey[0x20]; 12659 u8 reserved_at_60[0x3a0]; 12660 }; 12661 12662 struct mlx5_ifc_mtrc_stdb_bits { 12663 u8 string_db_index[0x4]; 12664 u8 reserved_at_4[0x4]; 12665 u8 read_size[0x18]; 12666 u8 start_offset[0x20]; 12667 u8 string_db_data[]; 12668 }; 12669 12670 struct mlx5_ifc_mtrc_ctrl_bits { 12671 u8 trace_status[0x2]; 12672 u8 reserved_at_2[0x2]; 12673 u8 arm_event[0x1]; 12674 u8 reserved_at_5[0xb]; 12675 u8 modify_field_select[0x10]; 12676 u8 reserved_at_20[0x2b]; 12677 u8 current_timestamp52_32[0x15]; 12678 u8 current_timestamp31_0[0x20]; 12679 u8 reserved_at_80[0x180]; 12680 }; 12681 12682 struct mlx5_ifc_host_params_context_bits { 12683 u8 host_number[0x8]; 12684 u8 reserved_at_8[0x5]; 12685 u8 host_pf_not_exist[0x1]; 12686 u8 reserved_at_14[0x1]; 12687 u8 host_pf_disabled[0x1]; 12688 u8 host_num_of_vfs[0x10]; 12689 12690 u8 host_total_vfs[0x10]; 12691 u8 host_pci_bus[0x10]; 12692 12693 u8 reserved_at_40[0x10]; 12694 u8 host_pci_device[0x10]; 12695 12696 u8 reserved_at_60[0x10]; 12697 u8 host_pci_function[0x10]; 12698 12699 u8 reserved_at_80[0x180]; 12700 }; 12701 12702 struct mlx5_ifc_query_esw_functions_in_bits { 12703 u8 opcode[0x10]; 12704 u8 reserved_at_10[0x10]; 12705 12706 u8 reserved_at_20[0x10]; 12707 u8 op_mod[0x10]; 12708 12709 u8 reserved_at_40[0x40]; 12710 }; 12711 12712 struct mlx5_ifc_query_esw_functions_out_bits { 12713 u8 status[0x8]; 12714 u8 reserved_at_8[0x18]; 12715 12716 u8 syndrome[0x20]; 12717 12718 u8 reserved_at_40[0x40]; 12719 12720 struct mlx5_ifc_host_params_context_bits host_params_context; 12721 12722 u8 reserved_at_280[0x180]; 12723 u8 host_sf_enable[][0x40]; 12724 }; 12725 12726 struct mlx5_ifc_sf_partition_bits { 12727 u8 reserved_at_0[0x10]; 12728 u8 log_num_sf[0x8]; 12729 u8 log_sf_bar_size[0x8]; 12730 }; 12731 12732 struct mlx5_ifc_query_sf_partitions_out_bits { 12733 u8 status[0x8]; 12734 u8 reserved_at_8[0x18]; 12735 12736 u8 syndrome[0x20]; 12737 12738 u8 reserved_at_40[0x18]; 12739 u8 num_sf_partitions[0x8]; 12740 12741 u8 reserved_at_60[0x20]; 12742 12743 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12744 }; 12745 12746 struct mlx5_ifc_query_sf_partitions_in_bits { 12747 u8 opcode[0x10]; 12748 u8 reserved_at_10[0x10]; 12749 12750 u8 reserved_at_20[0x10]; 12751 u8 op_mod[0x10]; 12752 12753 u8 reserved_at_40[0x40]; 12754 }; 12755 12756 struct mlx5_ifc_dealloc_sf_out_bits { 12757 u8 status[0x8]; 12758 u8 reserved_at_8[0x18]; 12759 12760 u8 syndrome[0x20]; 12761 12762 u8 reserved_at_40[0x40]; 12763 }; 12764 12765 struct mlx5_ifc_dealloc_sf_in_bits { 12766 u8 opcode[0x10]; 12767 u8 reserved_at_10[0x10]; 12768 12769 u8 reserved_at_20[0x10]; 12770 u8 op_mod[0x10]; 12771 12772 u8 reserved_at_40[0x10]; 12773 u8 function_id[0x10]; 12774 12775 u8 reserved_at_60[0x20]; 12776 }; 12777 12778 struct mlx5_ifc_alloc_sf_out_bits { 12779 u8 status[0x8]; 12780 u8 reserved_at_8[0x18]; 12781 12782 u8 syndrome[0x20]; 12783 12784 u8 reserved_at_40[0x40]; 12785 }; 12786 12787 struct mlx5_ifc_alloc_sf_in_bits { 12788 u8 opcode[0x10]; 12789 u8 reserved_at_10[0x10]; 12790 12791 u8 reserved_at_20[0x10]; 12792 u8 op_mod[0x10]; 12793 12794 u8 reserved_at_40[0x10]; 12795 u8 function_id[0x10]; 12796 12797 u8 reserved_at_60[0x20]; 12798 }; 12799 12800 struct mlx5_ifc_affiliated_event_header_bits { 12801 u8 reserved_at_0[0x10]; 12802 u8 obj_type[0x10]; 12803 12804 u8 obj_id[0x20]; 12805 }; 12806 12807 enum { 12808 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12809 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12810 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12811 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12812 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12813 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12814 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12815 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12816 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12817 }; 12818 12819 enum { 12820 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12821 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12822 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12823 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12824 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12825 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12826 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12827 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12828 }; 12829 12830 enum { 12831 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12832 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12833 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12834 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12835 }; 12836 12837 enum { 12838 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12839 }; 12840 12841 enum { 12842 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12843 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12844 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12845 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12846 }; 12847 12848 enum { 12849 MLX5_IPSEC_ASO_MODE = 0x0, 12850 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12851 MLX5_IPSEC_ASO_INC_SN = 0x2, 12852 }; 12853 12854 enum { 12855 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12856 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12857 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12858 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12859 }; 12860 12861 struct mlx5_ifc_ipsec_aso_bits { 12862 u8 valid[0x1]; 12863 u8 reserved_at_201[0x1]; 12864 u8 mode[0x2]; 12865 u8 window_sz[0x2]; 12866 u8 soft_lft_arm[0x1]; 12867 u8 hard_lft_arm[0x1]; 12868 u8 remove_flow_enable[0x1]; 12869 u8 esn_event_arm[0x1]; 12870 u8 reserved_at_20a[0x16]; 12871 12872 u8 remove_flow_pkt_cnt[0x20]; 12873 12874 u8 remove_flow_soft_lft[0x20]; 12875 12876 u8 reserved_at_260[0x80]; 12877 12878 u8 mode_parameter[0x20]; 12879 12880 u8 replay_protection_window[0x100]; 12881 }; 12882 12883 struct mlx5_ifc_ipsec_obj_bits { 12884 u8 modify_field_select[0x40]; 12885 u8 full_offload[0x1]; 12886 u8 reserved_at_41[0x1]; 12887 u8 esn_en[0x1]; 12888 u8 esn_overlap[0x1]; 12889 u8 reserved_at_44[0x2]; 12890 u8 icv_length[0x2]; 12891 u8 reserved_at_48[0x4]; 12892 u8 aso_return_reg[0x4]; 12893 u8 reserved_at_50[0x10]; 12894 12895 u8 esn_msb[0x20]; 12896 12897 u8 reserved_at_80[0x8]; 12898 u8 dekn[0x18]; 12899 12900 u8 salt[0x20]; 12901 12902 u8 implicit_iv[0x40]; 12903 12904 u8 reserved_at_100[0x8]; 12905 u8 ipsec_aso_access_pd[0x18]; 12906 u8 reserved_at_120[0xe0]; 12907 12908 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12909 }; 12910 12911 struct mlx5_ifc_create_ipsec_obj_in_bits { 12912 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12913 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12914 }; 12915 12916 enum { 12917 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12918 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12919 }; 12920 12921 struct mlx5_ifc_query_ipsec_obj_out_bits { 12922 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12923 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12924 }; 12925 12926 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12927 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12928 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12929 }; 12930 12931 enum { 12932 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12933 }; 12934 12935 enum { 12936 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12937 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12938 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12939 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12940 }; 12941 12942 #define MLX5_MACSEC_ASO_INC_SN 0x2 12943 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12944 12945 struct mlx5_ifc_macsec_aso_bits { 12946 u8 valid[0x1]; 12947 u8 reserved_at_1[0x1]; 12948 u8 mode[0x2]; 12949 u8 window_size[0x2]; 12950 u8 soft_lifetime_arm[0x1]; 12951 u8 hard_lifetime_arm[0x1]; 12952 u8 remove_flow_enable[0x1]; 12953 u8 epn_event_arm[0x1]; 12954 u8 reserved_at_a[0x16]; 12955 12956 u8 remove_flow_packet_count[0x20]; 12957 12958 u8 remove_flow_soft_lifetime[0x20]; 12959 12960 u8 reserved_at_60[0x80]; 12961 12962 u8 mode_parameter[0x20]; 12963 12964 u8 replay_protection_window[8][0x20]; 12965 }; 12966 12967 struct mlx5_ifc_macsec_offload_obj_bits { 12968 u8 modify_field_select[0x40]; 12969 12970 u8 confidentiality_en[0x1]; 12971 u8 reserved_at_41[0x1]; 12972 u8 epn_en[0x1]; 12973 u8 epn_overlap[0x1]; 12974 u8 reserved_at_44[0x2]; 12975 u8 confidentiality_offset[0x2]; 12976 u8 reserved_at_48[0x4]; 12977 u8 aso_return_reg[0x4]; 12978 u8 reserved_at_50[0x10]; 12979 12980 u8 epn_msb[0x20]; 12981 12982 u8 reserved_at_80[0x8]; 12983 u8 dekn[0x18]; 12984 12985 u8 reserved_at_a0[0x20]; 12986 12987 u8 sci[0x40]; 12988 12989 u8 reserved_at_100[0x8]; 12990 u8 macsec_aso_access_pd[0x18]; 12991 12992 u8 reserved_at_120[0x60]; 12993 12994 u8 salt[3][0x20]; 12995 12996 u8 reserved_at_1e0[0x20]; 12997 12998 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12999 }; 13000 13001 struct mlx5_ifc_create_macsec_obj_in_bits { 13002 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13003 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13004 }; 13005 13006 struct mlx5_ifc_modify_macsec_obj_in_bits { 13007 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13008 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13009 }; 13010 13011 enum { 13012 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 13013 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 13014 }; 13015 13016 struct mlx5_ifc_query_macsec_obj_out_bits { 13017 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13018 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13019 }; 13020 13021 struct mlx5_ifc_wrapped_dek_bits { 13022 u8 gcm_iv[0x60]; 13023 13024 u8 reserved_at_60[0x20]; 13025 13026 u8 const0[0x1]; 13027 u8 key_size[0x1]; 13028 u8 reserved_at_82[0x2]; 13029 u8 key2_invalid[0x1]; 13030 u8 reserved_at_85[0x3]; 13031 u8 pd[0x18]; 13032 13033 u8 key_purpose[0x5]; 13034 u8 reserved_at_a5[0x13]; 13035 u8 kek_id[0x8]; 13036 13037 u8 reserved_at_c0[0x40]; 13038 13039 u8 key1[0x8][0x20]; 13040 13041 u8 key2[0x8][0x20]; 13042 13043 u8 reserved_at_300[0x40]; 13044 13045 u8 const1[0x1]; 13046 u8 reserved_at_341[0x1f]; 13047 13048 u8 reserved_at_360[0x20]; 13049 13050 u8 auth_tag[0x80]; 13051 }; 13052 13053 struct mlx5_ifc_encryption_key_obj_bits { 13054 u8 modify_field_select[0x40]; 13055 13056 u8 state[0x8]; 13057 u8 sw_wrapped[0x1]; 13058 u8 reserved_at_49[0xb]; 13059 u8 key_size[0x4]; 13060 u8 reserved_at_58[0x4]; 13061 u8 key_purpose[0x4]; 13062 13063 u8 reserved_at_60[0x8]; 13064 u8 pd[0x18]; 13065 13066 u8 reserved_at_80[0x100]; 13067 13068 u8 opaque[0x40]; 13069 13070 u8 reserved_at_1c0[0x40]; 13071 13072 u8 key[8][0x80]; 13073 13074 u8 sw_wrapped_dek[8][0x80]; 13075 13076 u8 reserved_at_a00[0x600]; 13077 }; 13078 13079 struct mlx5_ifc_create_encryption_key_in_bits { 13080 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13081 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13082 }; 13083 13084 struct mlx5_ifc_modify_encryption_key_in_bits { 13085 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13086 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13087 }; 13088 13089 enum { 13090 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13091 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13092 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13093 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13094 }; 13095 13096 struct mlx5_ifc_flow_meter_parameters_bits { 13097 u8 valid[0x1]; 13098 u8 bucket_overflow[0x1]; 13099 u8 start_color[0x2]; 13100 u8 both_buckets_on_green[0x1]; 13101 u8 reserved_at_5[0x1]; 13102 u8 meter_mode[0x2]; 13103 u8 reserved_at_8[0x18]; 13104 13105 u8 reserved_at_20[0x20]; 13106 13107 u8 reserved_at_40[0x3]; 13108 u8 cbs_exponent[0x5]; 13109 u8 cbs_mantissa[0x8]; 13110 u8 reserved_at_50[0x3]; 13111 u8 cir_exponent[0x5]; 13112 u8 cir_mantissa[0x8]; 13113 13114 u8 reserved_at_60[0x20]; 13115 13116 u8 reserved_at_80[0x3]; 13117 u8 ebs_exponent[0x5]; 13118 u8 ebs_mantissa[0x8]; 13119 u8 reserved_at_90[0x3]; 13120 u8 eir_exponent[0x5]; 13121 u8 eir_mantissa[0x8]; 13122 13123 u8 reserved_at_a0[0x60]; 13124 }; 13125 13126 struct mlx5_ifc_flow_meter_aso_obj_bits { 13127 u8 modify_field_select[0x40]; 13128 13129 u8 reserved_at_40[0x40]; 13130 13131 u8 reserved_at_80[0x8]; 13132 u8 meter_aso_access_pd[0x18]; 13133 13134 u8 reserved_at_a0[0x160]; 13135 13136 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13137 }; 13138 13139 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13140 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13141 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13142 }; 13143 13144 struct mlx5_ifc_int_kek_obj_bits { 13145 u8 modify_field_select[0x40]; 13146 13147 u8 state[0x8]; 13148 u8 auto_gen[0x1]; 13149 u8 reserved_at_49[0xb]; 13150 u8 key_size[0x4]; 13151 u8 reserved_at_58[0x8]; 13152 13153 u8 reserved_at_60[0x8]; 13154 u8 pd[0x18]; 13155 13156 u8 reserved_at_80[0x180]; 13157 u8 key[8][0x80]; 13158 13159 u8 reserved_at_600[0x200]; 13160 }; 13161 13162 struct mlx5_ifc_create_int_kek_obj_in_bits { 13163 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13164 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13165 }; 13166 13167 struct mlx5_ifc_create_int_kek_obj_out_bits { 13168 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13169 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13170 }; 13171 13172 struct mlx5_ifc_sampler_obj_bits { 13173 u8 modify_field_select[0x40]; 13174 13175 u8 table_type[0x8]; 13176 u8 level[0x8]; 13177 u8 reserved_at_50[0xf]; 13178 u8 ignore_flow_level[0x1]; 13179 13180 u8 sample_ratio[0x20]; 13181 13182 u8 reserved_at_80[0x8]; 13183 u8 sample_table_id[0x18]; 13184 13185 u8 reserved_at_a0[0x8]; 13186 u8 default_table_id[0x18]; 13187 13188 u8 sw_steering_icm_address_rx[0x40]; 13189 u8 sw_steering_icm_address_tx[0x40]; 13190 13191 u8 reserved_at_140[0xa0]; 13192 }; 13193 13194 struct mlx5_ifc_create_sampler_obj_in_bits { 13195 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13196 struct mlx5_ifc_sampler_obj_bits sampler_object; 13197 }; 13198 13199 struct mlx5_ifc_query_sampler_obj_out_bits { 13200 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13201 struct mlx5_ifc_sampler_obj_bits sampler_object; 13202 }; 13203 13204 enum { 13205 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13206 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13207 }; 13208 13209 enum { 13210 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13211 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13212 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13213 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13214 }; 13215 13216 struct mlx5_ifc_tls_static_params_bits { 13217 u8 const_2[0x2]; 13218 u8 tls_version[0x4]; 13219 u8 const_1[0x2]; 13220 u8 reserved_at_8[0x14]; 13221 u8 encryption_standard[0x4]; 13222 13223 u8 reserved_at_20[0x20]; 13224 13225 u8 initial_record_number[0x40]; 13226 13227 u8 resync_tcp_sn[0x20]; 13228 13229 u8 gcm_iv[0x20]; 13230 13231 u8 implicit_iv[0x40]; 13232 13233 u8 reserved_at_100[0x8]; 13234 u8 dek_index[0x18]; 13235 13236 u8 reserved_at_120[0xe0]; 13237 }; 13238 13239 struct mlx5_ifc_tls_progress_params_bits { 13240 u8 next_record_tcp_sn[0x20]; 13241 13242 u8 hw_resync_tcp_sn[0x20]; 13243 13244 u8 record_tracker_state[0x2]; 13245 u8 auth_state[0x2]; 13246 u8 reserved_at_44[0x4]; 13247 u8 hw_offset_record_number[0x18]; 13248 }; 13249 13250 enum { 13251 MLX5_MTT_PERM_READ = 1 << 0, 13252 MLX5_MTT_PERM_WRITE = 1 << 1, 13253 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13254 }; 13255 13256 enum { 13257 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13258 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13259 }; 13260 13261 struct mlx5_ifc_suspend_vhca_in_bits { 13262 u8 opcode[0x10]; 13263 u8 uid[0x10]; 13264 13265 u8 reserved_at_20[0x10]; 13266 u8 op_mod[0x10]; 13267 13268 u8 reserved_at_40[0x10]; 13269 u8 vhca_id[0x10]; 13270 13271 u8 reserved_at_60[0x20]; 13272 }; 13273 13274 struct mlx5_ifc_suspend_vhca_out_bits { 13275 u8 status[0x8]; 13276 u8 reserved_at_8[0x18]; 13277 13278 u8 syndrome[0x20]; 13279 13280 u8 reserved_at_40[0x40]; 13281 }; 13282 13283 enum { 13284 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13285 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13286 }; 13287 13288 struct mlx5_ifc_resume_vhca_in_bits { 13289 u8 opcode[0x10]; 13290 u8 uid[0x10]; 13291 13292 u8 reserved_at_20[0x10]; 13293 u8 op_mod[0x10]; 13294 13295 u8 reserved_at_40[0x10]; 13296 u8 vhca_id[0x10]; 13297 13298 u8 reserved_at_60[0x20]; 13299 }; 13300 13301 struct mlx5_ifc_resume_vhca_out_bits { 13302 u8 status[0x8]; 13303 u8 reserved_at_8[0x18]; 13304 13305 u8 syndrome[0x20]; 13306 13307 u8 reserved_at_40[0x40]; 13308 }; 13309 13310 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13311 u8 opcode[0x10]; 13312 u8 uid[0x10]; 13313 13314 u8 reserved_at_20[0x10]; 13315 u8 op_mod[0x10]; 13316 13317 u8 incremental[0x1]; 13318 u8 chunk[0x1]; 13319 u8 reserved_at_42[0xe]; 13320 u8 vhca_id[0x10]; 13321 13322 u8 reserved_at_60[0x20]; 13323 }; 13324 13325 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13326 u8 status[0x8]; 13327 u8 reserved_at_8[0x18]; 13328 13329 u8 syndrome[0x20]; 13330 13331 u8 reserved_at_40[0x40]; 13332 13333 u8 required_umem_size[0x20]; 13334 13335 u8 reserved_at_a0[0x20]; 13336 13337 u8 remaining_total_size[0x40]; 13338 13339 u8 reserved_at_100[0x100]; 13340 }; 13341 13342 struct mlx5_ifc_save_vhca_state_in_bits { 13343 u8 opcode[0x10]; 13344 u8 uid[0x10]; 13345 13346 u8 reserved_at_20[0x10]; 13347 u8 op_mod[0x10]; 13348 13349 u8 incremental[0x1]; 13350 u8 set_track[0x1]; 13351 u8 reserved_at_42[0xe]; 13352 u8 vhca_id[0x10]; 13353 13354 u8 reserved_at_60[0x20]; 13355 13356 u8 va[0x40]; 13357 13358 u8 mkey[0x20]; 13359 13360 u8 size[0x20]; 13361 }; 13362 13363 struct mlx5_ifc_save_vhca_state_out_bits { 13364 u8 status[0x8]; 13365 u8 reserved_at_8[0x18]; 13366 13367 u8 syndrome[0x20]; 13368 13369 u8 actual_image_size[0x20]; 13370 13371 u8 next_required_umem_size[0x20]; 13372 }; 13373 13374 struct mlx5_ifc_load_vhca_state_in_bits { 13375 u8 opcode[0x10]; 13376 u8 uid[0x10]; 13377 13378 u8 reserved_at_20[0x10]; 13379 u8 op_mod[0x10]; 13380 13381 u8 reserved_at_40[0x10]; 13382 u8 vhca_id[0x10]; 13383 13384 u8 reserved_at_60[0x20]; 13385 13386 u8 va[0x40]; 13387 13388 u8 mkey[0x20]; 13389 13390 u8 size[0x20]; 13391 }; 13392 13393 struct mlx5_ifc_load_vhca_state_out_bits { 13394 u8 status[0x8]; 13395 u8 reserved_at_8[0x18]; 13396 13397 u8 syndrome[0x20]; 13398 13399 u8 reserved_at_40[0x40]; 13400 }; 13401 13402 struct mlx5_ifc_adv_rdma_cap_bits { 13403 u8 rdma_transport_manager[0x1]; 13404 u8 rdma_transport_manager_other_eswitch[0x1]; 13405 u8 reserved_at_2[0x1e]; 13406 13407 u8 rcx_type[0x8]; 13408 u8 reserved_at_28[0x2]; 13409 u8 ps_entry_log_max_value[0x6]; 13410 u8 reserved_at_30[0x6]; 13411 u8 qp_max_ps_num_entry[0xa]; 13412 13413 u8 mp_max_num_queues[0x8]; 13414 u8 ps_user_context_max_log_size[0x8]; 13415 u8 message_based_qp_and_striding_wq[0x8]; 13416 u8 reserved_at_58[0x8]; 13417 13418 u8 max_receive_send_message_size_stride[0x10]; 13419 u8 reserved_at_70[0x10]; 13420 13421 u8 max_receive_send_message_size_byte[0x20]; 13422 13423 u8 reserved_at_a0[0x160]; 13424 13425 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13426 13427 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13428 13429 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13430 13431 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13432 13433 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13434 13435 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13436 13437 u8 reserved_at_800[0x3800]; 13438 }; 13439 13440 struct mlx5_ifc_adv_virtualization_cap_bits { 13441 u8 reserved_at_0[0x3]; 13442 u8 pg_track_log_max_num[0x5]; 13443 u8 pg_track_max_num_range[0x8]; 13444 u8 pg_track_log_min_addr_space[0x8]; 13445 u8 pg_track_log_max_addr_space[0x8]; 13446 13447 u8 reserved_at_20[0x3]; 13448 u8 pg_track_log_min_msg_size[0x5]; 13449 u8 reserved_at_28[0x3]; 13450 u8 pg_track_log_max_msg_size[0x5]; 13451 u8 reserved_at_30[0x3]; 13452 u8 pg_track_log_min_page_size[0x5]; 13453 u8 reserved_at_38[0x3]; 13454 u8 pg_track_log_max_page_size[0x5]; 13455 13456 u8 reserved_at_40[0x7c0]; 13457 }; 13458 13459 struct mlx5_ifc_page_track_report_entry_bits { 13460 u8 dirty_address_high[0x20]; 13461 13462 u8 dirty_address_low[0x20]; 13463 }; 13464 13465 enum { 13466 MLX5_PAGE_TRACK_STATE_TRACKING, 13467 MLX5_PAGE_TRACK_STATE_REPORTING, 13468 MLX5_PAGE_TRACK_STATE_ERROR, 13469 }; 13470 13471 struct mlx5_ifc_page_track_range_bits { 13472 u8 start_address[0x40]; 13473 13474 u8 length[0x40]; 13475 }; 13476 13477 struct mlx5_ifc_page_track_bits { 13478 u8 modify_field_select[0x40]; 13479 13480 u8 reserved_at_40[0x10]; 13481 u8 vhca_id[0x10]; 13482 13483 u8 reserved_at_60[0x20]; 13484 13485 u8 state[0x4]; 13486 u8 track_type[0x4]; 13487 u8 log_addr_space_size[0x8]; 13488 u8 reserved_at_90[0x3]; 13489 u8 log_page_size[0x5]; 13490 u8 reserved_at_98[0x3]; 13491 u8 log_msg_size[0x5]; 13492 13493 u8 reserved_at_a0[0x8]; 13494 u8 reporting_qpn[0x18]; 13495 13496 u8 reserved_at_c0[0x18]; 13497 u8 num_ranges[0x8]; 13498 13499 u8 reserved_at_e0[0x20]; 13500 13501 u8 range_start_address[0x40]; 13502 13503 u8 length[0x40]; 13504 13505 struct mlx5_ifc_page_track_range_bits track_range[0]; 13506 }; 13507 13508 struct mlx5_ifc_create_page_track_obj_in_bits { 13509 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13510 struct mlx5_ifc_page_track_bits obj_context; 13511 }; 13512 13513 struct mlx5_ifc_modify_page_track_obj_in_bits { 13514 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13515 struct mlx5_ifc_page_track_bits obj_context; 13516 }; 13517 13518 struct mlx5_ifc_query_page_track_obj_out_bits { 13519 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13520 struct mlx5_ifc_page_track_bits obj_context; 13521 }; 13522 13523 struct mlx5_ifc_msecq_reg_bits { 13524 u8 reserved_at_0[0x20]; 13525 13526 u8 reserved_at_20[0x12]; 13527 u8 network_option[0x2]; 13528 u8 local_ssm_code[0x4]; 13529 u8 local_enhanced_ssm_code[0x8]; 13530 13531 u8 local_clock_identity[0x40]; 13532 13533 u8 reserved_at_80[0x180]; 13534 }; 13535 13536 enum { 13537 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13538 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13539 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13540 }; 13541 13542 enum mlx5_msees_admin_status { 13543 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13544 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13545 }; 13546 13547 enum mlx5_msees_oper_status { 13548 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13549 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13550 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13551 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13552 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13553 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13554 }; 13555 13556 enum mlx5_msees_failure_reason { 13557 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13558 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13559 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13560 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13561 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13562 }; 13563 13564 struct mlx5_ifc_msees_reg_bits { 13565 u8 reserved_at_0[0x8]; 13566 u8 local_port[0x8]; 13567 u8 pnat[0x2]; 13568 u8 lp_msb[0x2]; 13569 u8 reserved_at_14[0xc]; 13570 13571 u8 field_select[0x20]; 13572 13573 u8 admin_status[0x4]; 13574 u8 oper_status[0x4]; 13575 u8 ho_acq[0x1]; 13576 u8 reserved_at_49[0xc]; 13577 u8 admin_freq_measure[0x1]; 13578 u8 oper_freq_measure[0x1]; 13579 u8 failure_reason[0x9]; 13580 13581 u8 frequency_diff[0x20]; 13582 13583 u8 reserved_at_80[0x180]; 13584 }; 13585 13586 struct mlx5_ifc_mrtcq_reg_bits { 13587 u8 reserved_at_0[0x40]; 13588 13589 u8 rt_clock_identity[0x40]; 13590 13591 u8 reserved_at_80[0x180]; 13592 }; 13593 13594 struct mlx5_ifc_pcie_cong_event_obj_bits { 13595 u8 modify_select_field[0x40]; 13596 13597 u8 inbound_event_en[0x1]; 13598 u8 outbound_event_en[0x1]; 13599 u8 reserved_at_42[0x1e]; 13600 13601 u8 reserved_at_60[0x1]; 13602 u8 inbound_cong_state[0x3]; 13603 u8 reserved_at_64[0x1]; 13604 u8 outbound_cong_state[0x3]; 13605 u8 reserved_at_68[0x18]; 13606 13607 u8 inbound_cong_low_threshold[0x10]; 13608 u8 inbound_cong_high_threshold[0x10]; 13609 13610 u8 outbound_cong_low_threshold[0x10]; 13611 u8 outbound_cong_high_threshold[0x10]; 13612 13613 u8 reserved_at_e0[0x340]; 13614 }; 13615 13616 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13617 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13618 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13619 }; 13620 13621 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13622 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13623 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13624 }; 13625 13626 enum mlx5e_pcie_cong_event_mod_field { 13627 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13628 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13629 }; 13630 13631 struct mlx5_ifc_psp_rotate_key_in_bits { 13632 u8 opcode[0x10]; 13633 u8 uid[0x10]; 13634 13635 u8 reserved_at_20[0x10]; 13636 u8 op_mod[0x10]; 13637 13638 u8 reserved_at_40[0x40]; 13639 }; 13640 13641 struct mlx5_ifc_psp_rotate_key_out_bits { 13642 u8 status[0x8]; 13643 u8 reserved_at_8[0x18]; 13644 13645 u8 syndrome[0x20]; 13646 13647 u8 reserved_at_40[0x40]; 13648 }; 13649 13650 enum mlx5_psp_gen_spi_in_key_size { 13651 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13652 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13653 }; 13654 13655 struct mlx5_ifc_key_spi_bits { 13656 u8 spi[0x20]; 13657 13658 u8 reserved_at_20[0x60]; 13659 13660 u8 key[8][0x20]; 13661 }; 13662 13663 struct mlx5_ifc_psp_gen_spi_in_bits { 13664 u8 opcode[0x10]; 13665 u8 uid[0x10]; 13666 13667 u8 reserved_at_20[0x10]; 13668 u8 op_mod[0x10]; 13669 13670 u8 reserved_at_40[0x20]; 13671 13672 u8 key_size[0x2]; 13673 u8 reserved_at_62[0xe]; 13674 u8 num_of_spi[0x10]; 13675 }; 13676 13677 struct mlx5_ifc_psp_gen_spi_out_bits { 13678 u8 status[0x8]; 13679 u8 reserved_at_8[0x18]; 13680 13681 u8 syndrome[0x20]; 13682 13683 u8 reserved_at_40[0x10]; 13684 u8 num_of_spi[0x10]; 13685 13686 u8 reserved_at_60[0x20]; 13687 13688 struct mlx5_ifc_key_spi_bits key_spi[]; 13689 }; 13690 13691 #endif /* MLX5_IFC_H */ 13692