1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8 #ifndef _ASUS_ARMOURY_H_ 9 #define _ASUS_ARMOURY_H_ 10 11 #include <linux/dmi.h> 12 #include <linux/platform_device.h> 13 #include <linux/sysfs.h> 14 #include <linux/types.h> 15 16 #define DRIVER_NAME "asus-armoury" 17 18 /** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41 ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45 /** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57 ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60 #define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66 #define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72 #define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75 #define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84 #define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91 /* Create functions and attributes for use in other macros or on their own */ 92 93 /* Shows a formatted static variable */ 94 #define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103 #define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122 #define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143 /* Boolean style enumeration, base macro. Requires adding show/store */ 144 #define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160 #define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164 #define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167 #define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170 /* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173 #define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178 /* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182 #define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201 #define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217 /* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222 #define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236 #define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254 #define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286 #define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309 /* Default is always the maximum value unless *_def is specified */ 310 struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336 }; 337 338 struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342 }; 343 344 /* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348 static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401UM"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 80, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 80, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 80, 361 .nv_dynamic_boost_min = 5, 362 .nv_dynamic_boost_max = 15, 363 .nv_temp_target_min = 75, 364 .nv_temp_target_max = 87, 365 }, 366 .dc_data = &(struct power_limits) { 367 .ppt_pl1_spl_min = 25, 368 .ppt_pl1_spl_max = 35, 369 .ppt_pl2_sppt_min = 31, 370 .ppt_pl2_sppt_max = 44, 371 .ppt_pl3_fppt_min = 45, 372 .ppt_pl3_fppt_max = 65, 373 .nv_temp_target_min = 75, 374 .nv_temp_target_max = 87, 375 }, 376 }, 377 }, 378 { 379 .matches = { 380 DMI_MATCH(DMI_BOARD_NAME, "FA401UV"), 381 }, 382 .driver_data = &(struct power_data) { 383 .ac_data = &(struct power_limits) { 384 .ppt_pl1_spl_min = 15, 385 .ppt_pl1_spl_max = 80, 386 .ppt_pl2_sppt_min = 35, 387 .ppt_pl2_sppt_max = 80, 388 .ppt_pl3_fppt_min = 35, 389 .ppt_pl3_fppt_max = 80, 390 .nv_dynamic_boost_min = 5, 391 .nv_dynamic_boost_max = 25, 392 .nv_temp_target_min = 75, 393 .nv_temp_target_max = 87, 394 .nv_tgp_min = 55, 395 .nv_tgp_max = 75, 396 }, 397 .dc_data = &(struct power_limits) { 398 .ppt_pl1_spl_min = 25, 399 .ppt_pl1_spl_max = 35, 400 .ppt_pl2_sppt_min = 31, 401 .ppt_pl2_sppt_max = 44, 402 .ppt_pl3_fppt_min = 45, 403 .ppt_pl3_fppt_max = 65, 404 .nv_temp_target_min = 75, 405 .nv_temp_target_max = 87, 406 }, 407 }, 408 }, 409 { 410 .matches = { 411 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 412 }, 413 .driver_data = &(struct power_data) { 414 .ac_data = &(struct power_limits) { 415 .ppt_pl1_spl_min = 15, 416 .ppt_pl1_spl_max = 80, 417 .ppt_pl2_sppt_min = 35, 418 .ppt_pl2_sppt_max = 80, 419 .ppt_pl3_fppt_min = 35, 420 .ppt_pl3_fppt_max = 80, 421 .nv_dynamic_boost_min = 5, 422 .nv_dynamic_boost_max = 25, 423 .nv_temp_target_min = 75, 424 .nv_temp_target_max = 87, 425 .nv_tgp_min = 55, 426 .nv_tgp_max = 75, 427 }, 428 .dc_data = &(struct power_limits) { 429 .ppt_pl1_spl_min = 25, 430 .ppt_pl1_spl_max = 30, 431 .ppt_pl2_sppt_min = 31, 432 .ppt_pl2_sppt_max = 44, 433 .ppt_pl3_fppt_min = 45, 434 .ppt_pl3_fppt_max = 65, 435 .nv_temp_target_min = 75, 436 .nv_temp_target_max = 87, 437 }, 438 }, 439 }, 440 { 441 .matches = { 442 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 443 }, 444 .driver_data = &(struct power_data) { 445 .ac_data = &(struct power_limits) { 446 .ppt_pl1_spl_min = 15, 447 .ppt_pl1_spl_max = 80, 448 .ppt_pl2_sppt_min = 35, 449 .ppt_pl2_sppt_max = 80, 450 .ppt_pl3_fppt_min = 35, 451 .ppt_pl3_fppt_max = 80, 452 .nv_dynamic_boost_min = 5, 453 .nv_dynamic_boost_max = 25, 454 .nv_temp_target_min = 75, 455 .nv_temp_target_max = 87, 456 }, 457 .dc_data = &(struct power_limits) { 458 .ppt_pl1_spl_min = 15, 459 .ppt_pl1_spl_def = 45, 460 .ppt_pl1_spl_max = 65, 461 .ppt_pl2_sppt_min = 35, 462 .ppt_pl2_sppt_def = 54, 463 .ppt_pl2_sppt_max = 65, 464 .ppt_pl3_fppt_min = 35, 465 .ppt_pl3_fppt_max = 65, 466 .nv_temp_target_min = 75, 467 .nv_temp_target_max = 87, 468 }, 469 }, 470 }, 471 { 472 .matches = { 473 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 474 }, 475 .driver_data = &(struct power_data) { 476 .ac_data = &(struct power_limits) { 477 .ppt_pl1_spl_min = 15, 478 .ppt_pl1_spl_max = 80, 479 .ppt_pl2_sppt_min = 35, 480 .ppt_pl2_sppt_max = 80, 481 .ppt_pl3_fppt_min = 35, 482 .ppt_pl3_fppt_max = 80, 483 .nv_dynamic_boost_min = 5, 484 .nv_dynamic_boost_max = 25, 485 .nv_temp_target_min = 75, 486 .nv_temp_target_max = 87, 487 .nv_tgp_min = 55, 488 .nv_tgp_max = 115, 489 }, 490 .dc_data = &(struct power_limits) { 491 .ppt_pl1_spl_min = 15, 492 .ppt_pl1_spl_def = 45, 493 .ppt_pl1_spl_max = 65, 494 .ppt_pl2_sppt_min = 35, 495 .ppt_pl2_sppt_def = 54, 496 .ppt_pl2_sppt_max = 65, 497 .ppt_pl3_fppt_min = 35, 498 .ppt_pl3_fppt_max = 65, 499 .nv_temp_target_min = 75, 500 .nv_temp_target_max = 87, 501 }, 502 }, 503 }, 504 { 505 .matches = { 506 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 507 }, 508 .driver_data = &(struct power_data) { 509 .ac_data = &(struct power_limits) { 510 .ppt_pl1_spl_min = 15, 511 .ppt_pl1_spl_max = 80, 512 .ppt_pl2_sppt_min = 35, 513 .ppt_pl2_sppt_max = 80, 514 .ppt_pl3_fppt_min = 35, 515 .ppt_pl3_fppt_max = 80, 516 .nv_dynamic_boost_min = 5, 517 .nv_dynamic_boost_max = 25, 518 .nv_temp_target_min = 75, 519 .nv_temp_target_max = 87, 520 }, 521 .dc_data = &(struct power_limits) { 522 .ppt_pl1_spl_min = 15, 523 .ppt_pl1_spl_def = 45, 524 .ppt_pl1_spl_max = 65, 525 .ppt_pl2_sppt_min = 35, 526 .ppt_pl2_sppt_def = 54, 527 .ppt_pl2_sppt_max = 65, 528 .ppt_pl3_fppt_min = 35, 529 .ppt_pl3_fppt_max = 65, 530 .nv_temp_target_min = 75, 531 .nv_temp_target_max = 87, 532 }, 533 }, 534 }, 535 { 536 .matches = { 537 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 538 }, 539 .driver_data = &(struct power_data) { 540 .ac_data = &(struct power_limits) { 541 .ppt_pl1_spl_min = 15, 542 .ppt_pl1_spl_max = 80, 543 .ppt_pl2_sppt_min = 35, 544 .ppt_pl2_sppt_max = 80, 545 .ppt_pl3_fppt_min = 35, 546 .ppt_pl3_fppt_max = 80, 547 .nv_dynamic_boost_min = 5, 548 .nv_dynamic_boost_max = 20, 549 .nv_temp_target_min = 75, 550 .nv_temp_target_max = 87, 551 .nv_tgp_min = 55, 552 .nv_tgp_max = 85, 553 }, 554 .dc_data = &(struct power_limits) { 555 .ppt_pl1_spl_min = 15, 556 .ppt_pl1_spl_def = 45, 557 .ppt_pl1_spl_max = 65, 558 .ppt_pl2_sppt_min = 35, 559 .ppt_pl2_sppt_def = 54, 560 .ppt_pl2_sppt_max = 65, 561 .ppt_pl3_fppt_min = 35, 562 .ppt_pl3_fppt_max = 65, 563 .nv_temp_target_min = 75, 564 .nv_temp_target_max = 87, 565 }, 566 }, 567 }, 568 { 569 .matches = { 570 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 571 }, 572 .driver_data = &(struct power_data) { 573 .ac_data = &(struct power_limits) { 574 .ppt_pl1_spl_min = 28, 575 .ppt_pl1_spl_max = 65, 576 .ppt_pl2_sppt_min = 28, 577 .ppt_pl2_sppt_max = 105, 578 .nv_dynamic_boost_min = 5, 579 .nv_dynamic_boost_max = 15, 580 .nv_temp_target_min = 75, 581 .nv_temp_target_max = 87, 582 .nv_tgp_min = 55, 583 .nv_tgp_max = 85, 584 }, 585 .dc_data = &(struct power_limits) { 586 .ppt_pl1_spl_min = 25, 587 .ppt_pl1_spl_max = 45, 588 .ppt_pl2_sppt_min = 35, 589 .ppt_pl2_sppt_max = 60, 590 .nv_temp_target_min = 75, 591 .nv_temp_target_max = 87, 592 }, 593 }, 594 }, 595 { 596 .matches = { 597 DMI_MATCH(DMI_BOARD_NAME, "FA607NU"), 598 }, 599 .driver_data = &(struct power_data) { 600 .ac_data = &(struct power_limits) { 601 .ppt_pl1_spl_min = 15, 602 .ppt_pl1_spl_max = 80, 603 .ppt_pl2_sppt_min = 35, 604 .ppt_pl2_sppt_max = 80, 605 .ppt_pl3_fppt_min = 35, 606 .ppt_pl3_fppt_max = 80, 607 .nv_dynamic_boost_min = 5, 608 .nv_dynamic_boost_max = 25, 609 .nv_temp_target_min = 75, 610 .nv_temp_target_max = 87, 611 }, 612 .dc_data = &(struct power_limits) { 613 .ppt_pl1_spl_min = 25, 614 .ppt_pl1_spl_def = 45, 615 .ppt_pl1_spl_max = 65, 616 .ppt_pl2_sppt_min = 25, 617 .ppt_pl2_sppt_def = 54, 618 .ppt_pl2_sppt_max = 65, 619 .ppt_pl3_fppt_min = 25, 620 .ppt_pl3_fppt_max = 65, 621 .nv_temp_target_min = 75, 622 .nv_temp_target_max = 87, 623 }, 624 }, 625 }, 626 { 627 .matches = { 628 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 629 }, 630 .driver_data = &(struct power_data) { 631 .ac_data = &(struct power_limits) { 632 .ppt_pl1_spl_min = 30, 633 .ppt_pl1_spl_def = 100, 634 .ppt_pl1_spl_max = 135, 635 .ppt_pl2_sppt_min = 30, 636 .ppt_pl2_sppt_def = 115, 637 .ppt_pl2_sppt_max = 135, 638 .ppt_pl3_fppt_min = 30, 639 .ppt_pl3_fppt_max = 135, 640 .nv_dynamic_boost_min = 5, 641 .nv_dynamic_boost_max = 25, 642 .nv_temp_target_min = 75, 643 .nv_temp_target_max = 87, 644 .nv_tgp_min = 55, 645 .nv_tgp_max = 115, 646 }, 647 .dc_data = &(struct power_limits) { 648 .ppt_pl1_spl_min = 25, 649 .ppt_pl1_spl_def = 45, 650 .ppt_pl1_spl_max = 80, 651 .ppt_pl2_sppt_min = 25, 652 .ppt_pl2_sppt_def = 60, 653 .ppt_pl2_sppt_max = 80, 654 .ppt_pl3_fppt_min = 25, 655 .ppt_pl3_fppt_max = 80, 656 .nv_temp_target_min = 75, 657 .nv_temp_target_max = 87, 658 }, 659 }, 660 }, 661 { 662 .matches = { 663 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 664 }, 665 .driver_data = &(struct power_data) { 666 .ac_data = &(struct power_limits) { 667 .ppt_pl1_spl_min = 15, 668 .ppt_pl1_spl_def = 45, 669 .ppt_pl1_spl_max = 90, 670 .ppt_pl2_sppt_min = 35, 671 .ppt_pl2_sppt_def = 54, 672 .ppt_pl2_sppt_max = 90, 673 .ppt_pl3_fppt_min = 35, 674 .ppt_pl3_fppt_def = 65, 675 .ppt_pl3_fppt_max = 90, 676 .nv_dynamic_boost_min = 10, 677 .nv_dynamic_boost_max = 15, 678 .nv_temp_target_min = 75, 679 .nv_temp_target_max = 87, 680 .nv_tgp_min = 55, 681 .nv_tgp_max = 100, 682 }, 683 .dc_data = &(struct power_limits) { 684 .ppt_pl1_spl_min = 15, 685 .ppt_pl1_spl_def = 45, 686 .ppt_pl1_spl_max = 65, 687 .ppt_pl2_sppt_min = 35, 688 .ppt_pl2_sppt_def = 54, 689 .ppt_pl2_sppt_max = 65, 690 .ppt_pl3_fppt_min = 35, 691 .ppt_pl3_fppt_max = 65, 692 .nv_temp_target_min = 75, 693 .nv_temp_target_max = 87, 694 }, 695 }, 696 }, 697 { 698 .matches = { 699 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 700 }, 701 .driver_data = &(struct power_data) { 702 .ac_data = &(struct power_limits) { 703 .ppt_pl1_spl_min = 15, 704 .ppt_pl1_spl_def = 90, 705 .ppt_pl1_spl_max = 90, 706 .ppt_pl2_sppt_min = 35, 707 .ppt_pl2_sppt_def = 90, 708 .ppt_pl2_sppt_max = 90, 709 .ppt_pl3_fppt_min = 35, 710 .ppt_pl3_fppt_def = 90, 711 .ppt_pl3_fppt_max = 90, 712 .nv_dynamic_boost_min = 5, 713 .nv_dynamic_boost_max = 25, 714 .nv_temp_target_min = 75, 715 .nv_temp_target_max = 87, 716 .nv_tgp_min = 55, 717 .nv_tgp_max = 115, 718 }, 719 .dc_data = &(struct power_limits) { 720 .ppt_pl1_spl_min = 15, 721 .ppt_pl1_spl_def = 45, 722 .ppt_pl1_spl_max = 65, 723 .ppt_pl2_sppt_min = 35, 724 .ppt_pl2_sppt_def = 54, 725 .ppt_pl2_sppt_max = 65, 726 .ppt_pl3_fppt_min = 35, 727 .ppt_pl3_fppt_def = 65, 728 .ppt_pl3_fppt_max = 65, 729 .nv_temp_target_min = 75, 730 .nv_temp_target_max = 87, 731 }, 732 }, 733 }, 734 { 735 .matches = { 736 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 737 }, 738 .driver_data = &(struct power_data) { 739 .ac_data = &(struct power_limits) { 740 .ppt_apu_sppt_min = 15, 741 .ppt_apu_sppt_max = 80, 742 .ppt_platform_sppt_min = 30, 743 .ppt_platform_sppt_max = 120, 744 }, 745 .dc_data = &(struct power_limits) { 746 .ppt_apu_sppt_min = 25, 747 .ppt_apu_sppt_max = 35, 748 .ppt_platform_sppt_min = 45, 749 .ppt_platform_sppt_max = 100, 750 }, 751 }, 752 }, 753 { 754 .matches = { 755 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 756 }, 757 .driver_data = &(struct power_data) { 758 .ac_data = &(struct power_limits) { 759 .ppt_apu_sppt_min = 15, 760 .ppt_apu_sppt_max = 80, 761 .ppt_platform_sppt_min = 30, 762 .ppt_platform_sppt_max = 115, 763 }, 764 .dc_data = &(struct power_limits) { 765 .ppt_apu_sppt_min = 15, 766 .ppt_apu_sppt_max = 45, 767 .ppt_platform_sppt_min = 30, 768 .ppt_platform_sppt_max = 50, 769 }, 770 }, 771 }, 772 { 773 .matches = { 774 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 775 }, 776 .driver_data = &(struct power_data) { 777 .ac_data = &(struct power_limits) { 778 .ppt_apu_sppt_min = 15, 779 .ppt_apu_sppt_max = 80, 780 .ppt_platform_sppt_min = 30, 781 .ppt_platform_sppt_max = 120, 782 .nv_temp_target_min = 75, 783 .nv_temp_target_max = 87, 784 }, 785 .dc_data = &(struct power_limits) { 786 .ppt_apu_sppt_min = 25, 787 .ppt_apu_sppt_max = 35, 788 .ppt_platform_sppt_min = 45, 789 .ppt_platform_sppt_max = 100, 790 .nv_temp_target_min = 75, 791 .nv_temp_target_max = 87, 792 }, 793 }, 794 }, 795 { 796 .matches = { 797 DMI_MATCH(DMI_BOARD_NAME, "FA617XT"), 798 }, 799 .driver_data = &(struct power_data) { 800 .ac_data = &(struct power_limits) { 801 .ppt_apu_sppt_min = 15, 802 .ppt_apu_sppt_max = 80, 803 .ppt_platform_sppt_min = 30, 804 .ppt_platform_sppt_max = 145, 805 }, 806 .dc_data = &(struct power_limits) { 807 .ppt_apu_sppt_min = 25, 808 .ppt_apu_sppt_max = 35, 809 .ppt_platform_sppt_min = 45, 810 .ppt_platform_sppt_max = 100, 811 }, 812 }, 813 }, 814 { 815 .matches = { 816 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 817 }, 818 .driver_data = &(struct power_data) { 819 .ac_data = &(struct power_limits) { 820 .ppt_pl1_spl_min = 28, 821 .ppt_pl1_spl_max = 135, 822 .ppt_pl2_sppt_min = 28, 823 .ppt_pl2_sppt_max = 135, 824 .nv_dynamic_boost_min = 5, 825 .nv_dynamic_boost_max = 25, 826 .nv_temp_target_min = 75, 827 .nv_temp_target_max = 87, 828 }, 829 .dc_data = &(struct power_limits) { 830 .ppt_pl1_spl_min = 25, 831 .ppt_pl1_spl_max = 45, 832 .ppt_pl2_sppt_min = 35, 833 .ppt_pl2_sppt_max = 60, 834 .nv_temp_target_min = 75, 835 .nv_temp_target_max = 87, 836 }, 837 .requires_fan_curve = true, 838 }, 839 }, 840 { 841 .matches = { 842 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 843 }, 844 .driver_data = &(struct power_data) { 845 .ac_data = &(struct power_limits) { 846 .ppt_pl1_spl_min = 28, 847 .ppt_pl1_spl_def = 115, 848 .ppt_pl1_spl_max = 135, 849 .ppt_pl2_sppt_min = 28, 850 .ppt_pl2_sppt_max = 135, 851 .nv_dynamic_boost_min = 5, 852 .nv_dynamic_boost_max = 25, 853 .nv_temp_target_min = 75, 854 .nv_temp_target_max = 87, 855 }, 856 .dc_data = &(struct power_limits) { 857 .ppt_pl1_spl_min = 25, 858 .ppt_pl1_spl_max = 45, 859 .ppt_pl2_sppt_min = 35, 860 .ppt_pl2_sppt_max = 60, 861 .nv_temp_target_min = 75, 862 .nv_temp_target_max = 87, 863 }, 864 .requires_fan_curve = true, 865 }, 866 }, 867 { 868 .matches = { 869 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 870 }, 871 .driver_data = &(struct power_data) { 872 .ac_data = &(struct power_limits) { 873 .ppt_pl1_spl_min = 28, 874 .ppt_pl1_spl_max = 90, 875 .ppt_pl2_sppt_min = 28, 876 .ppt_pl2_sppt_max = 135, 877 .nv_dynamic_boost_min = 5, 878 .nv_dynamic_boost_max = 15, 879 }, 880 .dc_data = &(struct power_limits) { 881 .ppt_pl1_spl_min = 25, 882 .ppt_pl1_spl_max = 45, 883 .ppt_pl2_sppt_min = 35, 884 .ppt_pl2_sppt_max = 60, 885 }, 886 .requires_fan_curve = true, 887 }, 888 }, 889 { 890 .matches = { 891 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 892 }, 893 .driver_data = &(struct power_data) { 894 .ac_data = &(struct power_limits) { 895 .ppt_pl1_spl_min = 15, 896 .ppt_pl1_spl_max = 80, 897 .ppt_pl2_sppt_min = 15, 898 .ppt_pl2_sppt_max = 80, 899 }, 900 .dc_data = NULL, 901 }, 902 }, 903 { 904 .matches = { 905 // This model is full AMD. No Nvidia dGPU. 906 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 907 }, 908 .driver_data = &(struct power_data) { 909 .ac_data = &(struct power_limits) { 910 .ppt_apu_sppt_min = 15, 911 .ppt_apu_sppt_max = 80, 912 .ppt_platform_sppt_min = 30, 913 .ppt_platform_sppt_max = 115, 914 }, 915 .dc_data = &(struct power_limits) { 916 .ppt_apu_sppt_min = 25, 917 .ppt_apu_sppt_def = 30, 918 .ppt_apu_sppt_max = 45, 919 .ppt_platform_sppt_min = 40, 920 .ppt_platform_sppt_max = 60, 921 }, 922 }, 923 }, 924 { 925 .matches = { 926 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 927 }, 928 .driver_data = &(struct power_data) { 929 .ac_data = &(struct power_limits) { 930 .ppt_pl1_spl_min = 15, 931 .ppt_pl1_spl_def = 35, 932 .ppt_pl1_spl_max = 80, 933 .ppt_pl2_sppt_min = 25, 934 .ppt_pl2_sppt_def = 65, 935 .ppt_pl2_sppt_max = 80, 936 .ppt_pl3_fppt_min = 35, 937 .ppt_pl3_fppt_max = 80, 938 .nv_temp_target_min = 75, 939 .nv_temp_target_max = 87, 940 }, 941 .dc_data = &(struct power_limits) { 942 .ppt_pl1_spl_min = 15, 943 .ppt_pl1_spl_max = 35, 944 .ppt_pl2_sppt_min = 25, 945 .ppt_pl2_sppt_max = 35, 946 .ppt_pl3_fppt_min = 35, 947 .ppt_pl3_fppt_max = 65, 948 .nv_temp_target_min = 75, 949 .nv_temp_target_max = 87, 950 }, 951 .requires_fan_curve = true, 952 }, 953 }, 954 { 955 .matches = { 956 DMI_MATCH(DMI_BOARD_NAME, "GA403UI"), 957 }, 958 .driver_data = &(struct power_data) { 959 .ac_data = &(struct power_limits) { 960 .ppt_pl1_spl_min = 15, 961 .ppt_pl1_spl_max = 80, 962 .ppt_pl2_sppt_min = 25, 963 .ppt_pl2_sppt_max = 80, 964 .ppt_pl3_fppt_min = 35, 965 .ppt_pl3_fppt_max = 80, 966 .nv_dynamic_boost_min = 5, 967 .nv_dynamic_boost_max = 25, 968 .nv_temp_target_min = 75, 969 .nv_temp_target_max = 87, 970 .nv_tgp_min = 55, 971 .nv_tgp_max = 65, 972 }, 973 .dc_data = &(struct power_limits) { 974 .ppt_pl1_spl_min = 15, 975 .ppt_pl1_spl_max = 35, 976 .ppt_pl2_sppt_min = 25, 977 .ppt_pl2_sppt_max = 35, 978 .ppt_pl3_fppt_min = 35, 979 .ppt_pl3_fppt_max = 65, 980 .nv_temp_target_min = 75, 981 .nv_temp_target_max = 87, 982 }, 983 .requires_fan_curve = true, 984 }, 985 }, 986 { 987 .matches = { 988 DMI_MATCH(DMI_BOARD_NAME, "GA403UV"), 989 }, 990 .driver_data = &(struct power_data) { 991 .ac_data = &(struct power_limits) { 992 .ppt_pl1_spl_min = 15, 993 .ppt_pl1_spl_max = 80, 994 .ppt_pl2_sppt_min = 25, 995 .ppt_pl2_sppt_max = 80, 996 .ppt_pl3_fppt_min = 35, 997 .ppt_pl3_fppt_max = 80, 998 .nv_dynamic_boost_min = 5, 999 .nv_dynamic_boost_max = 25, 1000 .nv_temp_target_min = 75, 1001 .nv_temp_target_max = 87, 1002 .nv_tgp_min = 55, 1003 .nv_tgp_max = 65, 1004 }, 1005 .dc_data = &(struct power_limits) { 1006 .ppt_pl1_spl_min = 15, 1007 .ppt_pl1_spl_max = 35, 1008 .ppt_pl2_sppt_min = 25, 1009 .ppt_pl2_sppt_max = 35, 1010 .ppt_pl3_fppt_min = 35, 1011 .ppt_pl3_fppt_max = 65, 1012 .nv_temp_target_min = 75, 1013 .nv_temp_target_max = 87, 1014 }, 1015 .requires_fan_curve = true, 1016 }, 1017 }, 1018 { 1019 .matches = { 1020 DMI_MATCH(DMI_BOARD_NAME, "GA403WM"), 1021 }, 1022 .driver_data = &(struct power_data) { 1023 .ac_data = &(struct power_limits) { 1024 .ppt_pl1_spl_min = 15, 1025 .ppt_pl1_spl_max = 80, 1026 .ppt_pl2_sppt_min = 25, 1027 .ppt_pl2_sppt_max = 80, 1028 .ppt_pl3_fppt_min = 35, 1029 .ppt_pl3_fppt_max = 80, 1030 .nv_dynamic_boost_min = 0, 1031 .nv_dynamic_boost_max = 15, 1032 .nv_temp_target_min = 75, 1033 .nv_temp_target_max = 87, 1034 .nv_tgp_min = 55, 1035 .nv_tgp_max = 85, 1036 }, 1037 .dc_data = &(struct power_limits) { 1038 .ppt_pl1_spl_min = 15, 1039 .ppt_pl1_spl_max = 35, 1040 .ppt_pl2_sppt_min = 25, 1041 .ppt_pl2_sppt_max = 35, 1042 .ppt_pl3_fppt_min = 35, 1043 .ppt_pl3_fppt_max = 65, 1044 .nv_temp_target_min = 75, 1045 .nv_temp_target_max = 87, 1046 }, 1047 .requires_fan_curve = true, 1048 }, 1049 }, 1050 { 1051 .matches = { 1052 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 1053 }, 1054 .driver_data = &(struct power_data) { 1055 .ac_data = &(struct power_limits) { 1056 .ppt_pl1_spl_min = 15, 1057 .ppt_pl1_spl_max = 80, 1058 .ppt_pl2_sppt_min = 25, 1059 .ppt_pl2_sppt_max = 80, 1060 .ppt_pl3_fppt_min = 35, 1061 .ppt_pl3_fppt_max = 80, 1062 .nv_dynamic_boost_min = 0, 1063 .nv_dynamic_boost_max = 25, 1064 .nv_temp_target_min = 75, 1065 .nv_temp_target_max = 87, 1066 .nv_tgp_min = 80, 1067 .nv_tgp_max = 95, 1068 }, 1069 .dc_data = &(struct power_limits) { 1070 .ppt_pl1_spl_min = 15, 1071 .ppt_pl1_spl_max = 35, 1072 .ppt_pl2_sppt_min = 25, 1073 .ppt_pl2_sppt_max = 35, 1074 .ppt_pl3_fppt_min = 35, 1075 .ppt_pl3_fppt_max = 65, 1076 .nv_temp_target_min = 75, 1077 .nv_temp_target_max = 87, 1078 }, 1079 .requires_fan_curve = true, 1080 }, 1081 }, 1082 { 1083 .matches = { 1084 DMI_MATCH(DMI_BOARD_NAME, "GA403WW"), 1085 }, 1086 .driver_data = &(struct power_data) { 1087 .ac_data = &(struct power_limits) { 1088 .ppt_pl1_spl_min = 15, 1089 .ppt_pl1_spl_max = 80, 1090 .ppt_pl2_sppt_min = 25, 1091 .ppt_pl2_sppt_max = 80, 1092 .ppt_pl3_fppt_min = 35, 1093 .ppt_pl3_fppt_max = 80, 1094 .nv_dynamic_boost_min = 0, 1095 .nv_dynamic_boost_max = 25, 1096 .nv_temp_target_min = 75, 1097 .nv_temp_target_max = 87, 1098 .nv_tgp_min = 80, 1099 .nv_tgp_max = 95, 1100 }, 1101 .dc_data = &(struct power_limits) { 1102 .ppt_pl1_spl_min = 15, 1103 .ppt_pl1_spl_max = 35, 1104 .ppt_pl2_sppt_min = 25, 1105 .ppt_pl2_sppt_max = 35, 1106 .ppt_pl3_fppt_min = 35, 1107 .ppt_pl3_fppt_max = 65, 1108 .nv_temp_target_min = 75, 1109 .nv_temp_target_max = 87, 1110 }, 1111 .requires_fan_curve = true, 1112 }, 1113 }, 1114 { 1115 .matches = { 1116 DMI_MATCH(DMI_BOARD_NAME, "GA503QM"), 1117 }, 1118 .driver_data = &(struct power_data) { 1119 .ac_data = &(struct power_limits) { 1120 .ppt_pl1_spl_min = 15, 1121 .ppt_pl1_spl_def = 35, 1122 .ppt_pl1_spl_max = 80, 1123 .ppt_pl2_sppt_min = 65, 1124 .ppt_pl2_sppt_max = 80, 1125 }, 1126 }, 1127 }, 1128 { 1129 .matches = { 1130 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 1131 }, 1132 .driver_data = &(struct power_data) { 1133 .ac_data = &(struct power_limits) { 1134 .ppt_pl1_spl_min = 15, 1135 .ppt_pl1_spl_def = 35, 1136 .ppt_pl1_spl_max = 80, 1137 .ppt_pl2_sppt_min = 65, 1138 .ppt_pl2_sppt_max = 80, 1139 }, 1140 }, 1141 }, 1142 { 1143 .matches = { 1144 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 1145 }, 1146 .driver_data = &(struct power_data) { 1147 .ac_data = &(struct power_limits) { 1148 .ppt_pl1_spl_min = 15, 1149 .ppt_pl1_spl_def = 35, 1150 .ppt_pl1_spl_max = 80, 1151 .ppt_pl2_sppt_min = 35, 1152 .ppt_pl2_sppt_def = 65, 1153 .ppt_pl2_sppt_max = 80, 1154 .ppt_pl3_fppt_min = 35, 1155 .ppt_pl3_fppt_max = 80, 1156 .nv_dynamic_boost_min = 5, 1157 .nv_dynamic_boost_max = 20, 1158 .nv_temp_target_min = 75, 1159 .nv_temp_target_max = 87, 1160 }, 1161 .dc_data = &(struct power_limits) { 1162 .ppt_pl1_spl_min = 15, 1163 .ppt_pl1_spl_def = 25, 1164 .ppt_pl1_spl_max = 65, 1165 .ppt_pl2_sppt_min = 35, 1166 .ppt_pl2_sppt_def = 54, 1167 .ppt_pl2_sppt_max = 60, 1168 .ppt_pl3_fppt_min = 35, 1169 .ppt_pl3_fppt_max = 65, 1170 }, 1171 }, 1172 }, 1173 { 1174 .matches = { 1175 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 1176 }, 1177 .driver_data = &(struct power_data) { 1178 .ac_data = &(struct power_limits) { 1179 .ppt_pl1_spl_min = 15, 1180 .ppt_pl1_spl_max = 80, 1181 .ppt_pl2_sppt_min = 35, 1182 .ppt_pl2_sppt_max = 80, 1183 .ppt_pl3_fppt_min = 35, 1184 .ppt_pl3_fppt_max = 80, 1185 .nv_dynamic_boost_min = 5, 1186 .nv_dynamic_boost_max = 20, 1187 .nv_temp_target_min = 75, 1188 .nv_temp_target_max = 87, 1189 .nv_tgp_min = 55, 1190 .nv_tgp_max = 85, 1191 }, 1192 .dc_data = &(struct power_limits) { 1193 .ppt_pl1_spl_min = 25, 1194 .ppt_pl1_spl_max = 35, 1195 .ppt_pl2_sppt_min = 31, 1196 .ppt_pl2_sppt_max = 44, 1197 .ppt_pl3_fppt_min = 45, 1198 .ppt_pl3_fppt_max = 65, 1199 .nv_temp_target_min = 75, 1200 .nv_temp_target_max = 87, 1201 }, 1202 .requires_fan_curve = true, 1203 }, 1204 }, 1205 { 1206 .matches = { 1207 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 1208 }, 1209 .driver_data = &(struct power_data) { 1210 .ac_data = &(struct power_limits) { 1211 .ppt_pl1_spl_min = 25, 1212 .ppt_pl1_spl_max = 60, 1213 .ppt_pl2_sppt_min = 25, 1214 .ppt_pl2_sppt_max = 135, 1215 .nv_dynamic_boost_min = 5, 1216 .nv_dynamic_boost_max = 20, 1217 .nv_temp_target_min = 75, 1218 .nv_temp_target_max = 87, 1219 }, 1220 .dc_data = &(struct power_limits) { 1221 .ppt_pl1_spl_min = 25, 1222 .ppt_pl1_spl_max = 40, 1223 .ppt_pl2_sppt_min = 25, 1224 .ppt_pl2_sppt_max = 40, 1225 .nv_temp_target_min = 75, 1226 .nv_temp_target_max = 87, 1227 } 1228 }, 1229 }, 1230 { 1231 .matches = { 1232 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1233 }, 1234 .driver_data = &(struct power_data) { 1235 .ac_data = &(struct power_limits) { 1236 .ppt_pl1_spl_min = 65, 1237 .ppt_pl1_spl_max = 120, 1238 .ppt_pl2_sppt_min = 65, 1239 .ppt_pl2_sppt_max = 150, 1240 .nv_dynamic_boost_min = 5, 1241 .nv_dynamic_boost_max = 25, 1242 .nv_temp_target_min = 75, 1243 .nv_temp_target_max = 87, 1244 }, 1245 .dc_data = &(struct power_limits) { 1246 .ppt_pl1_spl_min = 25, 1247 .ppt_pl1_spl_max = 40, 1248 .ppt_pl2_sppt_min = 35, 1249 .ppt_pl2_sppt_def = 40, 1250 .ppt_pl2_sppt_max = 60, 1251 .nv_temp_target_min = 75, 1252 .nv_temp_target_max = 87, 1253 }, 1254 }, 1255 }, 1256 { 1257 .matches = { 1258 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1259 }, 1260 .driver_data = &(struct power_data) { 1261 .ac_data = &(struct power_limits) { 1262 .ppt_pl1_spl_min = 30, 1263 .ppt_pl1_spl_max = 85, 1264 .ppt_pl2_sppt_min = 38, 1265 .ppt_pl2_sppt_max = 110, 1266 .nv_dynamic_boost_min = 5, 1267 .nv_dynamic_boost_max = 20, 1268 .nv_temp_target_min = 75, 1269 .nv_temp_target_max = 87, 1270 .nv_tgp_min = 80, 1271 .nv_tgp_def = 90, 1272 .nv_tgp_max = 105, 1273 }, 1274 .dc_data = &(struct power_limits) { 1275 .ppt_pl1_spl_min = 30, 1276 .ppt_pl1_spl_max = 85, 1277 .ppt_pl2_sppt_min = 38, 1278 .ppt_pl2_sppt_max = 110, 1279 .nv_temp_target_min = 75, 1280 .nv_temp_target_max = 87, 1281 }, 1282 .requires_fan_curve = true, 1283 }, 1284 }, 1285 { 1286 .matches = { 1287 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1288 }, 1289 .driver_data = &(struct power_data) { 1290 .ac_data = &(struct power_limits) { 1291 .ppt_pl1_spl_min = 45, 1292 .ppt_pl1_spl_max = 85, 1293 .ppt_pl2_sppt_min = 56, 1294 .ppt_pl2_sppt_max = 110, 1295 .nv_dynamic_boost_min = 5, 1296 .nv_dynamic_boost_max = 20, 1297 .nv_temp_target_min = 75, 1298 .nv_temp_target_max = 87, 1299 .nv_tgp_min = 80, 1300 .nv_tgp_def = 90, 1301 .nv_tgp_max = 110, 1302 }, 1303 .dc_data = &(struct power_limits) { 1304 .ppt_pl1_spl_min = 25, 1305 .ppt_pl1_spl_max = 85, 1306 .ppt_pl2_sppt_min = 32, 1307 .ppt_pl2_sppt_max = 110, 1308 .nv_temp_target_min = 75, 1309 .nv_temp_target_max = 87, 1310 }, 1311 .requires_fan_curve = true, 1312 }, 1313 }, 1314 { 1315 .matches = { 1316 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1317 }, 1318 .driver_data = &(struct power_data) { 1319 .ac_data = &(struct power_limits) { 1320 .ppt_pl1_spl_min = 45, 1321 .ppt_pl1_spl_max = 85, 1322 .ppt_pl2_sppt_min = 56, 1323 .ppt_pl2_sppt_max = 110, 1324 .nv_dynamic_boost_min = 5, 1325 .nv_dynamic_boost_max = 20, 1326 .nv_temp_target_min = 7, 1327 .nv_temp_target_max = 87, 1328 .nv_tgp_min = 95, 1329 .nv_tgp_def = 100, 1330 .nv_tgp_max = 110, 1331 }, 1332 .dc_data = &(struct power_limits) { 1333 .ppt_pl1_spl_min = 25, 1334 .ppt_pl1_spl_max = 85, 1335 .ppt_pl2_sppt_min = 32, 1336 .ppt_pl2_sppt_max = 110, 1337 .nv_temp_target_min = 75, 1338 .nv_temp_target_max = 87, 1339 }, 1340 .requires_fan_curve = true, 1341 }, 1342 }, 1343 { 1344 .matches = { 1345 DMI_MATCH(DMI_BOARD_NAME, "GU605MU"), 1346 }, 1347 .driver_data = &(struct power_data) { 1348 .ac_data = &(struct power_limits) { 1349 .ppt_pl1_spl_min = 28, 1350 .ppt_pl1_spl_max = 90, 1351 .ppt_pl2_sppt_min = 28, 1352 .ppt_pl2_sppt_max = 135, 1353 .nv_dynamic_boost_min = 5, 1354 .nv_dynamic_boost_max = 20, 1355 .nv_temp_target_min = 75, 1356 .nv_temp_target_max = 87, 1357 .nv_tgp_min = 55, 1358 .nv_tgp_max = 85, 1359 }, 1360 .dc_data = &(struct power_limits) { 1361 .ppt_pl1_spl_min = 25, 1362 .ppt_pl1_spl_max = 35, 1363 .ppt_pl2_sppt_min = 38, 1364 .ppt_pl2_sppt_max = 53, 1365 .nv_temp_target_min = 75, 1366 .nv_temp_target_max = 87, 1367 }, 1368 .requires_fan_curve = true, 1369 }, 1370 }, 1371 { 1372 .matches = { 1373 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1374 }, 1375 .driver_data = &(struct power_data) { 1376 .ac_data = &(struct power_limits) { 1377 .ppt_pl1_spl_min = 28, 1378 .ppt_pl1_spl_max = 90, 1379 .ppt_pl2_sppt_min = 28, 1380 .ppt_pl2_sppt_max = 135, 1381 .nv_dynamic_boost_min = 5, 1382 .nv_dynamic_boost_max = 20, 1383 .nv_temp_target_min = 75, 1384 .nv_temp_target_max = 87, 1385 }, 1386 .dc_data = &(struct power_limits) { 1387 .ppt_pl1_spl_min = 25, 1388 .ppt_pl1_spl_max = 35, 1389 .ppt_pl2_sppt_min = 38, 1390 .ppt_pl2_sppt_max = 53, 1391 .nv_temp_target_min = 75, 1392 .nv_temp_target_max = 87, 1393 }, 1394 .requires_fan_curve = true, 1395 }, 1396 }, 1397 { 1398 .matches = { 1399 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1400 }, 1401 .driver_data = &(struct power_data) { 1402 .ac_data = &(struct power_limits) { 1403 .ppt_pl1_spl_min = 15, 1404 .ppt_pl1_spl_max = 45, 1405 .ppt_pl2_sppt_min = 65, 1406 .ppt_pl2_sppt_max = 80, 1407 }, 1408 .dc_data = NULL, 1409 }, 1410 }, 1411 { 1412 .matches = { 1413 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1414 }, 1415 .driver_data = &(struct power_data) { 1416 .ac_data = &(struct power_limits) { 1417 .ppt_pl1_spl_min = 15, 1418 .ppt_pl1_spl_max = 45, 1419 .ppt_pl2_sppt_min = 25, 1420 .ppt_pl2_sppt_max = 54, 1421 .ppt_pl3_fppt_min = 35, 1422 .ppt_pl3_fppt_max = 65, 1423 .nv_temp_target_min = 75, 1424 .nv_temp_target_max = 87, 1425 }, 1426 .dc_data = &(struct power_limits) { 1427 .ppt_pl1_spl_min = 15, 1428 .ppt_pl1_spl_max = 35, 1429 .ppt_pl2_sppt_min = 25, 1430 .ppt_pl2_sppt_max = 35, 1431 .ppt_pl3_fppt_min = 35, 1432 .ppt_pl3_fppt_max = 65, 1433 .nv_temp_target_min = 75, 1434 .nv_temp_target_max = 87, 1435 }, 1436 }, 1437 }, 1438 { 1439 .matches = { 1440 DMI_MATCH(DMI_BOARD_NAME, "GV302XU"), 1441 }, 1442 .driver_data = &(struct power_data) { 1443 .ac_data = &(struct power_limits) { 1444 .ppt_pl1_spl_min = 15, 1445 .ppt_pl1_spl_max = 55, 1446 .ppt_pl2_sppt_min = 25, 1447 .ppt_pl2_sppt_max = 60, 1448 .ppt_pl3_fppt_min = 35, 1449 .ppt_pl3_fppt_max = 65, 1450 .nv_temp_target_min = 75, 1451 .nv_temp_target_max = 87, 1452 }, 1453 .dc_data = &(struct power_limits) { 1454 .ppt_pl1_spl_min = 15, 1455 .ppt_pl1_spl_max = 35, 1456 .ppt_pl2_sppt_min = 25, 1457 .ppt_pl2_sppt_max = 35, 1458 .ppt_pl3_fppt_min = 35, 1459 .ppt_pl3_fppt_max = 65, 1460 .nv_temp_target_min = 75, 1461 .nv_temp_target_max = 87, 1462 }, 1463 }, 1464 }, 1465 { 1466 .matches = { 1467 DMI_MATCH(DMI_BOARD_NAME, "GV302XV"), 1468 }, 1469 .driver_data = &(struct power_data) { 1470 .ac_data = &(struct power_limits) { 1471 .ppt_pl1_spl_min = 15, 1472 .ppt_pl1_spl_max = 55, 1473 .ppt_pl2_sppt_min = 25, 1474 .ppt_pl2_sppt_max = 60, 1475 .ppt_pl3_fppt_min = 35, 1476 .ppt_pl3_fppt_max = 65, 1477 .nv_temp_target_min = 75, 1478 .nv_temp_target_max = 87, 1479 }, 1480 .dc_data = &(struct power_limits) { 1481 .ppt_pl1_spl_min = 15, 1482 .ppt_pl1_spl_max = 35, 1483 .ppt_pl2_sppt_min = 25, 1484 .ppt_pl2_sppt_max = 35, 1485 .ppt_pl3_fppt_min = 35, 1486 .ppt_pl3_fppt_max = 65, 1487 .nv_temp_target_min = 75, 1488 .nv_temp_target_max = 87, 1489 }, 1490 }, 1491 }, 1492 { 1493 .matches = { 1494 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1495 }, 1496 .driver_data = &(struct power_data) { 1497 .ac_data = &(struct power_limits) { 1498 .ppt_pl1_spl_min = 15, 1499 .ppt_pl1_spl_def = 35, 1500 .ppt_pl1_spl_max = 90, 1501 .ppt_pl2_sppt_min = 35, 1502 .ppt_pl2_sppt_def = 54, 1503 .ppt_pl2_sppt_max = 100, 1504 .ppt_pl3_fppt_min = 35, 1505 .ppt_pl3_fppt_def = 80, 1506 .ppt_pl3_fppt_max = 125, 1507 .nv_dynamic_boost_min = 5, 1508 .nv_dynamic_boost_max = 25, 1509 .nv_temp_target_min = 75, 1510 .nv_temp_target_max = 87, 1511 }, 1512 .dc_data = &(struct power_limits) { 1513 .ppt_pl1_spl_min = 15, 1514 .ppt_pl1_spl_def = 28, 1515 .ppt_pl1_spl_max = 65, 1516 .ppt_pl2_sppt_min = 35, 1517 .ppt_pl2_sppt_def = 54, 1518 .ppt_pl2_sppt_max = 60, 1519 .ppt_pl3_fppt_min = 35, 1520 .ppt_pl3_fppt_def = 80, 1521 .ppt_pl3_fppt_max = 65, 1522 .nv_temp_target_min = 75, 1523 .nv_temp_target_max = 87, 1524 }, 1525 }, 1526 }, 1527 { 1528 .matches = { 1529 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1530 }, 1531 .driver_data = &(struct power_data) { 1532 .ac_data = &(struct power_limits) { 1533 .ppt_pl1_spl_min = 28, 1534 .ppt_pl1_spl_def = 100, 1535 .ppt_pl1_spl_max = 110, 1536 .ppt_pl2_sppt_min = 28, 1537 .ppt_pl2_sppt_max = 135, 1538 .nv_dynamic_boost_min = 5, 1539 .nv_dynamic_boost_max = 20, 1540 .nv_temp_target_min = 75, 1541 .nv_temp_target_max = 87, 1542 }, 1543 .dc_data = &(struct power_limits) { 1544 .ppt_pl1_spl_min = 25, 1545 .ppt_pl1_spl_max = 40, 1546 .ppt_pl2_sppt_min = 35, 1547 .ppt_pl2_sppt_def = 40, 1548 .ppt_pl2_sppt_max = 60, 1549 .nv_temp_target_min = 75, 1550 .nv_temp_target_max = 87, 1551 }, 1552 }, 1553 }, 1554 { 1555 .matches = { 1556 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1557 }, 1558 .driver_data = &(struct power_data) { 1559 .ac_data = &(struct power_limits) { 1560 .ppt_pl1_spl_min = 15, 1561 .ppt_pl1_spl_def = 110, 1562 .ppt_pl1_spl_max = 130, 1563 .ppt_pl2_sppt_min = 35, 1564 .ppt_pl2_sppt_def = 125, 1565 .ppt_pl2_sppt_max = 130, 1566 .ppt_pl3_fppt_min = 35, 1567 .ppt_pl3_fppt_def = 125, 1568 .ppt_pl3_fppt_max = 135, 1569 .nv_dynamic_boost_min = 5, 1570 .nv_dynamic_boost_max = 25, 1571 .nv_temp_target_min = 75, 1572 .nv_temp_target_max = 87, 1573 }, 1574 .dc_data = &(struct power_limits) { 1575 .ppt_pl1_spl_min = 15, 1576 .ppt_pl1_spl_def = 25, 1577 .ppt_pl1_spl_max = 65, 1578 .ppt_pl2_sppt_min = 35, 1579 .ppt_pl2_sppt_def = 35, 1580 .ppt_pl2_sppt_max = 65, 1581 .ppt_pl3_fppt_min = 35, 1582 .ppt_pl3_fppt_def = 42, 1583 .ppt_pl3_fppt_max = 65, 1584 .nv_temp_target_min = 75, 1585 .nv_temp_target_max = 87, 1586 }, 1587 }, 1588 }, 1589 { 1590 .matches = { 1591 DMI_MATCH(DMI_BOARD_NAME, "GX650RX"), 1592 }, 1593 .driver_data = &(struct power_data) { 1594 .ac_data = &(struct power_limits) { 1595 .ppt_pl1_spl_min = 28, 1596 .ppt_pl1_spl_def = 70, 1597 .ppt_pl1_spl_max = 90, 1598 .ppt_pl2_sppt_min = 28, 1599 .ppt_pl2_sppt_def = 70, 1600 .ppt_pl2_sppt_max = 100, 1601 .ppt_pl3_fppt_min = 28, 1602 .ppt_pl3_fppt_def = 110, 1603 .ppt_pl3_fppt_max = 125, 1604 .nv_dynamic_boost_min = 5, 1605 .nv_dynamic_boost_max = 25, 1606 .nv_temp_target_min = 76, 1607 .nv_temp_target_max = 87, 1608 }, 1609 .dc_data = &(struct power_limits) { 1610 .ppt_pl1_spl_min = 28, 1611 .ppt_pl1_spl_max = 50, 1612 .ppt_pl2_sppt_min = 28, 1613 .ppt_pl2_sppt_max = 50, 1614 .ppt_pl3_fppt_min = 28, 1615 .ppt_pl3_fppt_max = 65, 1616 .nv_temp_target_min = 76, 1617 .nv_temp_target_max = 87, 1618 }, 1619 }, 1620 }, 1621 { 1622 .matches = { 1623 DMI_MATCH(DMI_BOARD_NAME, "GZ302EA"), 1624 }, 1625 .driver_data = &(struct power_data) { 1626 .ac_data = &(struct power_limits) { 1627 .ppt_pl1_spl_min = 28, 1628 .ppt_pl1_spl_def = 60, 1629 .ppt_pl1_spl_max = 80, 1630 .ppt_pl2_sppt_min = 32, 1631 .ppt_pl2_sppt_def = 75, 1632 .ppt_pl2_sppt_max = 92, 1633 .ppt_pl3_fppt_min = 45, 1634 .ppt_pl3_fppt_def = 86, 1635 .ppt_pl3_fppt_max = 93, 1636 }, 1637 .dc_data = &(struct power_limits) { 1638 .ppt_pl1_spl_min = 28, 1639 .ppt_pl1_spl_def = 45, 1640 .ppt_pl1_spl_max = 80, 1641 .ppt_pl2_sppt_min = 32, 1642 .ppt_pl2_sppt_def = 52, 1643 .ppt_pl2_sppt_max = 92, 1644 .ppt_pl3_fppt_min = 45, 1645 .ppt_pl3_fppt_def = 71, 1646 .ppt_pl3_fppt_max = 93, 1647 }, 1648 }, 1649 }, 1650 { 1651 .matches = { 1652 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1653 }, 1654 .driver_data = &(struct power_data) { 1655 .ac_data = &(struct power_limits) { 1656 /* Yes this laptop is very limited */ 1657 .ppt_pl1_spl_min = 15, 1658 .ppt_pl1_spl_max = 80, 1659 .ppt_pl2_sppt_min = 15, 1660 .ppt_pl2_sppt_max = 80, 1661 }, 1662 .dc_data = NULL, 1663 .requires_fan_curve = true, 1664 }, 1665 }, 1666 { 1667 .matches = { 1668 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1669 }, 1670 .driver_data = &(struct power_data) { 1671 .ac_data = &(struct power_limits) { 1672 /* Yes this laptop is very limited */ 1673 .ppt_pl1_spl_min = 15, 1674 .ppt_pl1_spl_max = 100, 1675 .ppt_pl2_sppt_min = 15, 1676 .ppt_pl2_sppt_max = 190, 1677 }, 1678 .dc_data = NULL, 1679 .requires_fan_curve = true, 1680 }, 1681 }, 1682 { 1683 .matches = { 1684 DMI_MATCH(DMI_BOARD_NAME, "G513QY"), 1685 }, 1686 .driver_data = &(struct power_data) { 1687 .ac_data = &(struct power_limits) { 1688 /* Advantage Edition Laptop, no PL1 or PL2 limits */ 1689 .ppt_apu_sppt_min = 15, 1690 .ppt_apu_sppt_max = 100, 1691 .ppt_platform_sppt_min = 70, 1692 .ppt_platform_sppt_max = 190, 1693 }, 1694 .dc_data = NULL, 1695 .requires_fan_curve = true, 1696 }, 1697 }, 1698 { 1699 .matches = { 1700 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1701 }, 1702 .driver_data = &(struct power_data) { 1703 .ac_data = &(struct power_limits) { 1704 .ppt_pl1_spl_min = 35, 1705 .ppt_pl1_spl_max = 90, 1706 .ppt_pl2_sppt_min = 54, 1707 .ppt_pl2_sppt_max = 100, 1708 .ppt_pl3_fppt_min = 54, 1709 .ppt_pl3_fppt_max = 125, 1710 .nv_dynamic_boost_min = 5, 1711 .nv_dynamic_boost_max = 25, 1712 .nv_temp_target_min = 75, 1713 .nv_temp_target_max = 87, 1714 }, 1715 .dc_data = &(struct power_limits) { 1716 .ppt_pl1_spl_min = 28, 1717 .ppt_pl1_spl_max = 50, 1718 .ppt_pl2_sppt_min = 28, 1719 .ppt_pl2_sppt_max = 50, 1720 .ppt_pl3_fppt_min = 28, 1721 .ppt_pl3_fppt_max = 65, 1722 .nv_temp_target_min = 75, 1723 .nv_temp_target_max = 87, 1724 }, 1725 .requires_fan_curve = true, 1726 }, 1727 }, 1728 { 1729 .matches = { 1730 DMI_MATCH(DMI_BOARD_NAME, "G614FP"), 1731 }, 1732 .driver_data = &(struct power_data) { 1733 .ac_data = &(struct power_limits) { 1734 .ppt_pl1_spl_min = 30, 1735 .ppt_pl1_spl_max = 120, 1736 .ppt_pl2_sppt_min = 65, 1737 .ppt_pl2_sppt_def = 140, 1738 .ppt_pl2_sppt_max = 165, 1739 .ppt_pl3_fppt_min = 65, 1740 .ppt_pl3_fppt_def = 140, 1741 .ppt_pl3_fppt_max = 165, 1742 .nv_temp_target_min = 75, 1743 .nv_temp_target_max = 87, 1744 .nv_dynamic_boost_min = 5, 1745 .nv_dynamic_boost_max = 15, 1746 .nv_tgp_min = 50, 1747 .nv_tgp_max = 100, 1748 }, 1749 .dc_data = &(struct power_limits) { 1750 .ppt_pl1_spl_min = 25, 1751 .ppt_pl1_spl_max = 65, 1752 .ppt_pl2_sppt_min = 25, 1753 .ppt_pl2_sppt_max = 65, 1754 .ppt_pl3_fppt_min = 35, 1755 .ppt_pl3_fppt_max = 75, 1756 .nv_temp_target_min = 75, 1757 .nv_temp_target_max = 87, 1758 }, 1759 .requires_fan_curve = true, 1760 }, 1761 }, 1762 { 1763 .matches = { 1764 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 1765 }, 1766 .driver_data = &(struct power_data) { 1767 .ac_data = &(struct power_limits) { 1768 .ppt_pl1_spl_min = 28, 1769 .ppt_pl1_spl_max = 140, 1770 .ppt_pl2_sppt_min = 28, 1771 .ppt_pl2_sppt_max = 175, 1772 .nv_temp_target_min = 75, 1773 .nv_temp_target_max = 87, 1774 .nv_dynamic_boost_min = 5, 1775 .nv_dynamic_boost_max = 25, 1776 }, 1777 .dc_data = &(struct power_limits) { 1778 .ppt_pl1_spl_min = 25, 1779 .ppt_pl1_spl_max = 55, 1780 .ppt_pl2_sppt_min = 25, 1781 .ppt_pl2_sppt_max = 70, 1782 .nv_temp_target_min = 75, 1783 .nv_temp_target_max = 87, 1784 }, 1785 .requires_fan_curve = true, 1786 }, 1787 }, 1788 { 1789 .matches = { 1790 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 1791 }, 1792 .driver_data = &(struct power_data) { 1793 .ac_data = &(struct power_limits) { 1794 .ppt_pl1_spl_min = 28, 1795 .ppt_pl1_spl_def = 140, 1796 .ppt_pl1_spl_max = 175, 1797 .ppt_pl2_sppt_min = 28, 1798 .ppt_pl2_sppt_max = 175, 1799 .nv_temp_target_min = 75, 1800 .nv_temp_target_max = 87, 1801 .nv_dynamic_boost_min = 5, 1802 .nv_dynamic_boost_max = 25, 1803 .nv_tgp_min = 65, 1804 .nv_tgp_max = 115, 1805 }, 1806 .dc_data = &(struct power_limits) { 1807 .ppt_pl1_spl_min = 25, 1808 .ppt_pl1_spl_max = 55, 1809 .ppt_pl2_sppt_min = 25, 1810 .ppt_pl2_sppt_max = 70, 1811 .nv_temp_target_min = 75, 1812 .nv_temp_target_max = 87, 1813 }, 1814 .requires_fan_curve = true, 1815 }, 1816 }, 1817 { 1818 .matches = { 1819 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 1820 }, 1821 .driver_data = &(struct power_data) { 1822 .ac_data = &(struct power_limits) { 1823 .ppt_pl1_spl_min = 28, 1824 .ppt_pl1_spl_max = 140, 1825 .ppt_pl2_sppt_min = 28, 1826 .ppt_pl2_sppt_max = 175, 1827 .nv_temp_target_min = 75, 1828 .nv_temp_target_max = 87, 1829 .nv_dynamic_boost_min = 5, 1830 .nv_dynamic_boost_max = 25, 1831 }, 1832 .dc_data = &(struct power_limits) { 1833 .ppt_pl1_spl_min = 25, 1834 .ppt_pl1_spl_max = 55, 1835 .ppt_pl2_sppt_min = 25, 1836 .ppt_pl2_sppt_max = 70, 1837 .nv_temp_target_min = 75, 1838 .nv_temp_target_max = 87, 1839 }, 1840 .requires_fan_curve = true, 1841 }, 1842 }, 1843 { 1844 .matches = { 1845 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 1846 }, 1847 .driver_data = &(struct power_data) { 1848 .ac_data = &(struct power_limits) { 1849 .ppt_pl1_spl_min = 30, 1850 .ppt_pl1_spl_def = 120, 1851 .ppt_pl1_spl_max = 130, 1852 .ppt_pl2_sppt_min = 65, 1853 .ppt_pl2_sppt_def = 125, 1854 .ppt_pl2_sppt_max = 130, 1855 .ppt_pl3_fppt_min = 65, 1856 .ppt_pl3_fppt_def = 125, 1857 .ppt_pl3_fppt_max = 130, 1858 .nv_temp_target_min = 75, 1859 .nv_temp_target_max = 87, 1860 .nv_dynamic_boost_min = 5, 1861 .nv_dynamic_boost_max = 25, 1862 }, 1863 .dc_data = &(struct power_limits) { 1864 .ppt_pl1_spl_min = 25, 1865 .ppt_pl1_spl_max = 65, 1866 .ppt_pl2_sppt_min = 25, 1867 .ppt_pl2_sppt_max = 65, 1868 .ppt_pl3_fppt_min = 35, 1869 .ppt_pl3_fppt_max = 75, 1870 .nv_temp_target_min = 75, 1871 .nv_temp_target_max = 87, 1872 }, 1873 .requires_fan_curve = true, 1874 }, 1875 }, 1876 { 1877 .matches = { 1878 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 1879 }, 1880 .driver_data = &(struct power_data) { 1881 .ac_data = &(struct power_limits) { 1882 .ppt_pl1_spl_min = 28, 1883 .ppt_pl1_spl_max = 170, 1884 .ppt_pl2_sppt_min = 28, 1885 .ppt_pl2_sppt_max = 175, 1886 .nv_temp_target_min = 75, 1887 .nv_temp_target_max = 87, 1888 .nv_dynamic_boost_min = 5, 1889 .nv_dynamic_boost_max = 25, 1890 }, 1891 .dc_data = &(struct power_limits) { 1892 .ppt_pl1_spl_min = 28, 1893 .ppt_pl1_spl_max = 35, 1894 .ppt_pl2_sppt_min = 28, 1895 .ppt_pl2_sppt_max = 35, 1896 .nv_temp_target_min = 75, 1897 .nv_temp_target_max = 87, 1898 }, 1899 .requires_fan_curve = true, 1900 }, 1901 }, 1902 { 1903 .matches = { 1904 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 1905 }, 1906 .driver_data = &(struct power_data) { 1907 .ac_data = &(struct power_limits) { 1908 .ppt_pl1_spl_min = 30, 1909 .ppt_pl1_spl_def = 100, 1910 .ppt_pl1_spl_max = 130, 1911 .ppt_pl2_sppt_min = 65, 1912 .ppt_pl2_sppt_def = 125, 1913 .ppt_pl2_sppt_max = 130, 1914 .ppt_pl3_fppt_min = 65, 1915 .ppt_pl3_fppt_def = 125, 1916 .ppt_pl3_fppt_max = 130, 1917 .nv_temp_target_min = 75, 1918 .nv_temp_target_max = 87, 1919 .nv_dynamic_boost_min = 5, 1920 .nv_dynamic_boost_max = 25, 1921 }, 1922 .dc_data = &(struct power_limits) { 1923 .ppt_pl1_spl_min = 25, 1924 .ppt_pl1_spl_max = 65, 1925 .ppt_pl2_sppt_min = 25, 1926 .ppt_pl2_sppt_max = 65, 1927 .ppt_pl3_fppt_min = 35, 1928 .ppt_pl3_fppt_max = 75, 1929 .nv_temp_target_min = 75, 1930 .nv_temp_target_max = 87, 1931 }, 1932 .requires_fan_curve = true, 1933 }, 1934 }, 1935 { 1936 .matches = { 1937 DMI_MATCH(DMI_BOARD_NAME, "G733QS"), 1938 }, 1939 .driver_data = &(struct power_data) { 1940 .ac_data = &(struct power_limits) { 1941 .ppt_pl1_spl_min = 15, 1942 .ppt_pl1_spl_max = 80, 1943 .ppt_pl2_sppt_min = 15, 1944 .ppt_pl2_sppt_max = 80, 1945 }, 1946 .requires_fan_curve = false, 1947 }, 1948 }, 1949 { 1950 .matches = { 1951 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 1952 }, 1953 .driver_data = &(struct power_data) { 1954 .ac_data = &(struct power_limits) { 1955 .ppt_pl1_spl_min = 28, 1956 .ppt_pl1_spl_max = 140, 1957 .ppt_pl2_sppt_min = 28, 1958 .ppt_pl2_sppt_max = 140, 1959 .nv_dynamic_boost_min = 5, 1960 .nv_dynamic_boost_max = 25, 1961 }, 1962 .dc_data = &(struct power_limits) { 1963 .ppt_pl1_spl_min = 25, 1964 .ppt_pl1_spl_max = 55, 1965 .ppt_pl2_sppt_min = 25, 1966 .ppt_pl2_sppt_max = 70, 1967 }, 1968 .requires_fan_curve = true, 1969 }, 1970 }, 1971 { 1972 .matches = { 1973 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 1974 }, 1975 .driver_data = &(struct power_data) { 1976 .ac_data = &(struct power_limits) { 1977 .ppt_pl1_spl_min = 28, 1978 .ppt_pl1_spl_max = 140, 1979 .ppt_pl2_sppt_min = 28, 1980 .ppt_pl2_sppt_max = 175, 1981 .nv_dynamic_boost_min = 5, 1982 .nv_dynamic_boost_max = 25, 1983 .nv_temp_target_min = 75, 1984 .nv_temp_target_max = 87, 1985 }, 1986 .dc_data = &(struct power_limits) { 1987 .ppt_pl1_spl_min = 25, 1988 .ppt_pl1_spl_max = 55, 1989 .ppt_pl2_sppt_min = 25, 1990 .ppt_pl2_sppt_max = 70, 1991 .nv_temp_target_min = 75, 1992 .nv_temp_target_max = 87, 1993 }, 1994 .requires_fan_curve = true, 1995 }, 1996 }, 1997 { 1998 .matches = { 1999 DMI_MATCH(DMI_BOARD_NAME, "G835LR"), 2000 }, 2001 .driver_data = &(struct power_data) { 2002 .ac_data = &(struct power_limits) { 2003 .ppt_pl1_spl_min = 28, 2004 .ppt_pl1_spl_def = 140, 2005 .ppt_pl1_spl_max = 175, 2006 .ppt_pl2_sppt_min = 28, 2007 .ppt_pl2_sppt_max = 175, 2008 .nv_dynamic_boost_min = 5, 2009 .nv_dynamic_boost_max = 25, 2010 .nv_temp_target_min = 75, 2011 .nv_temp_target_max = 87, 2012 .nv_tgp_min = 65, 2013 .nv_tgp_max = 115, 2014 }, 2015 .dc_data = &(struct power_limits) { 2016 .ppt_pl1_spl_min = 25, 2017 .ppt_pl1_spl_max = 55, 2018 .ppt_pl2_sppt_min = 25, 2019 .ppt_pl2_sppt_max = 70, 2020 .nv_temp_target_min = 75, 2021 .nv_temp_target_max = 87, 2022 }, 2023 .requires_fan_curve = true, 2024 }, 2025 }, 2026 { 2027 .matches = { 2028 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 2029 }, 2030 .driver_data = &(struct power_data) { 2031 .ac_data = &(struct power_limits) { 2032 .ppt_pl1_spl_min = 28, 2033 .ppt_pl1_spl_def = 140, 2034 .ppt_pl1_spl_max = 175, 2035 .ppt_pl2_sppt_min = 28, 2036 .ppt_pl2_sppt_max = 175, 2037 .nv_dynamic_boost_min = 5, 2038 .nv_dynamic_boost_max = 25, 2039 .nv_temp_target_min = 75, 2040 .nv_temp_target_max = 87, 2041 .nv_tgp_min = 80, 2042 .nv_tgp_max = 150, 2043 }, 2044 .dc_data = &(struct power_limits) { 2045 .ppt_pl1_spl_min = 25, 2046 .ppt_pl1_spl_max = 55, 2047 .ppt_pl2_sppt_min = 25, 2048 .ppt_pl2_sppt_max = 70, 2049 .nv_temp_target_min = 75, 2050 .nv_temp_target_max = 87, 2051 }, 2052 .requires_fan_curve = true, 2053 }, 2054 }, 2055 { 2056 .matches = { 2057 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 2058 }, 2059 .driver_data = &(struct power_data) { 2060 .ac_data = &(struct power_limits) { 2061 .ppt_pl1_spl_min = 15, 2062 .ppt_pl1_spl_max = 80, 2063 .ppt_pl2_sppt_min = 35, 2064 .ppt_pl2_sppt_max = 80, 2065 .ppt_pl3_fppt_min = 35, 2066 .ppt_pl3_fppt_max = 80, 2067 .nv_dynamic_boost_min = 5, 2068 .nv_dynamic_boost_max = 20, 2069 .nv_temp_target_min = 75, 2070 .nv_temp_target_max = 87, 2071 .nv_tgp_min = 55, 2072 .nv_tgp_max = 85, 2073 }, 2074 .dc_data = &(struct power_limits) { 2075 .ppt_pl1_spl_min = 25, 2076 .ppt_pl1_spl_max = 35, 2077 .ppt_pl2_sppt_min = 31, 2078 .ppt_pl2_sppt_max = 44, 2079 .ppt_pl3_fppt_min = 45, 2080 .ppt_pl3_fppt_max = 65, 2081 .nv_temp_target_min = 75, 2082 .nv_temp_target_max = 87, 2083 }, 2084 }, 2085 }, 2086 { 2087 .matches = { 2088 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 2089 }, 2090 .driver_data = &(struct power_data) { 2091 .ac_data = &(struct power_limits) { 2092 .ppt_pl1_spl_min = 7, 2093 .ppt_pl1_spl_max = 30, 2094 .ppt_pl2_sppt_min = 15, 2095 .ppt_pl2_sppt_max = 43, 2096 .ppt_pl3_fppt_min = 15, 2097 .ppt_pl3_fppt_max = 53, 2098 }, 2099 .dc_data = &(struct power_limits) { 2100 .ppt_pl1_spl_min = 7, 2101 .ppt_pl1_spl_def = 15, 2102 .ppt_pl1_spl_max = 25, 2103 .ppt_pl2_sppt_min = 15, 2104 .ppt_pl2_sppt_def = 20, 2105 .ppt_pl2_sppt_max = 30, 2106 .ppt_pl3_fppt_min = 15, 2107 .ppt_pl3_fppt_def = 25, 2108 .ppt_pl3_fppt_max = 35, 2109 }, 2110 }, 2111 }, 2112 { 2113 .matches = { 2114 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 2115 }, 2116 .driver_data = &(struct power_data) { 2117 .ac_data = &(struct power_limits) { 2118 .ppt_pl1_spl_min = 7, 2119 .ppt_pl1_spl_max = 30, 2120 .ppt_pl2_sppt_min = 15, 2121 .ppt_pl2_sppt_max = 43, 2122 .ppt_pl3_fppt_min = 15, 2123 .ppt_pl3_fppt_max = 53, 2124 }, 2125 .dc_data = &(struct power_limits) { 2126 .ppt_pl1_spl_min = 7, 2127 .ppt_pl1_spl_def = 17, 2128 .ppt_pl1_spl_max = 25, 2129 .ppt_pl2_sppt_min = 15, 2130 .ppt_pl2_sppt_def = 24, 2131 .ppt_pl2_sppt_max = 30, 2132 .ppt_pl3_fppt_min = 15, 2133 .ppt_pl3_fppt_def = 30, 2134 .ppt_pl3_fppt_max = 35, 2135 }, 2136 }, 2137 }, 2138 { 2139 .matches = { 2140 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 2141 }, 2142 .driver_data = &(struct power_data) { 2143 .ac_data = &(struct power_limits) { 2144 .ppt_pl1_spl_min = 7, 2145 .ppt_pl1_spl_max = 35, 2146 .ppt_pl2_sppt_min = 14, 2147 .ppt_pl2_sppt_max = 45, 2148 .ppt_pl3_fppt_min = 19, 2149 .ppt_pl3_fppt_max = 55, 2150 }, 2151 .dc_data = &(struct power_limits) { 2152 .ppt_pl1_spl_min = 7, 2153 .ppt_pl1_spl_def = 17, 2154 .ppt_pl1_spl_max = 35, 2155 .ppt_pl2_sppt_min = 13, 2156 .ppt_pl2_sppt_def = 21, 2157 .ppt_pl2_sppt_max = 45, 2158 .ppt_pl3_fppt_min = 19, 2159 .ppt_pl3_fppt_def = 26, 2160 .ppt_pl3_fppt_max = 55, 2161 }, 2162 }, 2163 }, 2164 {} 2165 }; 2166 2167 #endif /* _ASUS_ARMOURY_H_ */ 2168