Home
last modified time | relevance | path

Searched refs:num_slices_h (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c181 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); in dsc_config_log()
377 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); in dsc_prepare_config()
389 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || in dsc_prepare_config()
406 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; in dsc_prepare_config()
415 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; in dsc_prepare_config()
418 …idth + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slic… in dsc_prepare_config()
609 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
615 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, in dsc_write_to_registers()
H A Ddcn20_dsc.h552 uint32_t num_slices_h; member
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h90 uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
94 const int num_slices_h,
H A Ddc_hw_types.h867 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ member
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c223 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, in dsc_write_to_registers()
229 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.c880 uint32_t num_slices_h; member
940 if (params[i].num_slices_h) in set_dsc_configs_from_fairness_vars()
941 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
1242 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in compute_mst_dsc_configs_for_link()
H A Damdgpu_dm.c7241 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in apply_dsc_policy_for_stream()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h336 void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c843 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
844 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
848 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
855 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
859 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c1071 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in dcn32_update_dsc_on_stream()
1072 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn32_update_dsc_on_stream()
1076 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in dcn32_update_dsc_on_stream()
1086 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in dcn32_update_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.h212 void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);
H A Ddcn401_dccg.c726 void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h) in dccg401_set_dto_dscclk() argument
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c2254 int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h; in hwss_dccg_set_dto_dscclk() local
2257 dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); in hwss_dccg_set_dto_dscclk()
2344 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in hwss_dsc_calculate_and_set_config()
3150 struct dccg *dccg, int inst, int num_slices_h) in hwss_add_dccg_set_dto_dscclk() argument
3156 …_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h; in hwss_add_dccg_set_dto_dscclk()
H A Ddc.c3344 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && in copy_stream_update_to_stream()
6837 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { in dc_capture_register_software_state()
6855 if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { in dc_capture_register_software_state()
6861 state->dsc[i].dsc_num_slices_h = dsc_cfg->num_slices_h; in dc_capture_register_software_state()
7050 if (timing->dsc_cfg.num_slices_h > 0) { in dc_capture_register_software_state()
7121 if (timing->dsc_cfg.num_slices_h > 0) { in dc_capture_register_software_state()
7124 state->optc[i].optc_dsc_slice_width = timing->h_addressable / timing->dsc_cfg.num_slices_h; in dc_capture_register_software_state()
H A Ddc_stream.c115 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c365 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
366 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
378 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h223 int num_slices_h; member
1724 struct dccg *dccg, int inst, int num_slices_h);
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c1655 int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt; in dcn401_add_dsc_sequence_for_odm_change() local
1660 otg_master->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
1678 odm_pipe->stream_res.dsc->inst, num_slices_h); in dcn401_add_dsc_sequence_for_odm_change()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_translation_helper.c147 timing->dsc.overrides.num_slices = stream->timing.dsc_cfg.num_slices_h; in populate_dml21_timing_config_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c790 out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1705 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1426 stream->timing.dsc_cfg.num_slices_h; in build_audio_output()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1373 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()