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Searched refs:num_levels (Results 1 – 25 of 64) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c122 clks->num_levels = 6; in get_default_clock_levels()
127 clks->num_levels = 6; in get_default_clock_levels()
132 clks->num_levels = 2; in get_default_clock_levels()
137 clks->num_levels = 0; in get_default_clock_levels()
224 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
226 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
231 for (i = 0; i < dc_clks->num_levels; i++) { in pp_to_dc_clock_levels()
244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
247 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
250 clk_level_info->num_levels in pp_to_dc_clock_levels_with_latency()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c81 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) in dcn3_init_single_clock() argument
89 *num_levels = 2; in dcn3_init_single_clock()
92 /* will set num_levels to 0 on failure */ in dcn3_init_single_clock()
93 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
95 /* if the initial message failed, num_levels will be 0 */ in dcn3_init_single_clock()
96 for (i = 0; i < *num_levels; i++) { in dcn3_init_single_clock()
112 unsigned int num_levels; in dcn3_init_clocks() local
135 &num_levels); in dcn3_init_clocks()
141 &num_levels); in dcn3_init_clocks()
146 &num_levels); in dcn3_init_clocks()
410 unsigned int num_levels; dcn3_get_memclk_states_from_smu() local
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/linux/drivers/video/backlight/
H A Dmp3309c.c205 int num_levels; in mp3309c_parse_fwnode() local
238 num_levels = ANALOG_I2C_NUM_LEVELS; in mp3309c_parse_fwnode()
251 num_levels = device_property_count_u32(dev, "brightness-levels"); in mp3309c_parse_fwnode()
252 if (num_levels < 2) in mp3309c_parse_fwnode()
256 num_levels = MP3309C_PWM_DEFAULT_NUM_LEVELS; in mp3309c_parse_fwnode()
261 pdata->levels = devm_kcalloc(dev, num_levels, sizeof(*pdata->levels), GFP_KERNEL); in mp3309c_parse_fwnode()
266 pdata->levels, num_levels); in mp3309c_parse_fwnode()
270 for (i = 0; i < num_levels; i++) in mp3309c_parse_fwnode()
274 pdata->max_brightness = num_levels - 1; in mp3309c_parse_fwnode()
H A Dpwm_bl.c222 unsigned int num_levels; in pwm_backlight_parse_dt() local
251 num_levels = length / sizeof(u32); in pwm_backlight_parse_dt()
254 if (num_levels > 0) { in pwm_backlight_parse_dt()
255 data->levels = devm_kcalloc(dev, num_levels, in pwm_backlight_parse_dt()
262 num_levels); in pwm_backlight_parse_dt()
287 unsigned int num_input_levels = num_levels; in pwm_backlight_parse_dt()
303 num_levels = (num_input_levels - 1) * num_steps + 1; in pwm_backlight_parse_dt()
305 num_levels); in pwm_backlight_parse_dt()
311 table = devm_kcalloc(dev, num_levels, sizeof(*table), in pwm_backlight_parse_dt()
344 data->max_brightness = num_levels in pwm_backlight_parse_dt()
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/linux/fs/verity/
H A Denable.c75 const int num_levels = params->num_levels; in build_merkle_tree() local
91 * Buffers 0 <= level < num_levels are for the actual tree levels. in build_merkle_tree()
92 * Buffer 'num_levels' is for the root hash. in build_merkle_tree()
94 for (level = -1; level < num_levels; level++) { in build_merkle_tree()
101 buffers[num_levels].data = root_hash; in build_merkle_tree()
102 buffers[num_levels].is_root_hash = true; in build_merkle_tree()
129 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
155 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
169 if (WARN_ON_ONCE(buffers[num_levels] in build_merkle_tree()
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H A Dopen.c104 * level to the starting block of that level. Level 'num_levels - 1' is in fsverity_init_merkle_tree_params()
112 if (params->num_levels >= FS_VERITY_MAX_LEVELS) { in fsverity_init_merkle_tree_params()
119 blocks_in_level[params->num_levels++] = blocks; in fsverity_init_merkle_tree_params()
124 for (level = (int)params->num_levels - 1; level >= 0; level--) { in fsverity_init_merkle_tree_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c1091 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1093 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1095 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1097 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1099 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1101 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1103 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1116 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1119 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, in bw_calcs_data_update_from_pplib()
1127 eng_clks.data[eng_clks.num_levels in bw_calcs_data_update_from_pplib()
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/linux/arch/arm64/kernel/
H A Dcacheinfo.c63 detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); in early_cache_level()
94 this_cpu_ci->num_levels = level; in init_cache_level()
106 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c133 unsigned int *num_levels) in dcn32_init_single_clock() argument
142 *num_levels = 2; in dcn32_init_single_clock()
145 /* will set num_levels to 0 on failure */ in dcn32_init_single_clock()
146 *num_levels = ret & 0xFF; in dcn32_init_single_clock()
148 /* if the initial message failed, num_levels will be 0 */ in dcn32_init_single_clock()
149 for (i = 0; i < *num_levels; i++) { in dcn32_init_single_clock()
165 unsigned int num_levels; in dcn32_init_clocks() local
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
225 num_levels = num_entries_per_clk->num_dppclk_levels; in dcn32_init_clocks()
237 for (i = 0; i < num_levels; in dcn32_init_clocks()
1030 unsigned int num_levels; dcn32_get_memclk_states_from_smu() local
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/linux/arch/arm/kernel/
H A Dcacheinfo.c118 return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); in early_cache_level()
144 this_cpu_ci->num_levels = level; in init_cache_level()
161 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h98 uint32_t num_levels; member
108 uint32_t num_levels; member
118 uint32_t num_levels; member
/linux/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c798 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; in trinity_program_power_levels_0_to_n()
800 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
805 for (i = new_ps->num_levels; i < n_current_state_levels; i++) in trinity_program_power_levels_0_to_n()
921 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
922 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
935 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
936 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1161 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1168 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); in trinity_dpm_force_performance_level()
1172 for (i = 0; i < ps->num_levels; in trinity_dpm_force_performance_level()
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H A Dr100_track.h44 unsigned num_levels; member
/linux/drivers/gpu/drm/amd/include/
H A Ddm_pp_interface.h174 uint32_t num_levels; member
184 uint32_t num_levels; member
/linux/drivers/gpu/drm/i915/display/
H A Dintel_wm.c148 for (level = 0; level < display->wm.num_levels; level++) { in intel_print_wm_latency()
188 for (level = 0; level < display->wm.num_levels; level++) { in wm_latency_show()
306 if (ret != display->wm.num_levels) in wm_latency_write()
311 for (level = 0; level < display->wm.num_levels; level++) in wm_latency_write()
H A Di9xx_wm.c913 display->wm.num_levels = G4X_WM_LEVEL_HPLL + 1; in g4x_setup_wm_latency()
1020 for (; level < display->wm.num_levels; level++) { in g4x_raw_plane_wm_set()
1039 for (; level < display->wm.num_levels; level++) { in g4x_raw_fbc_wm_set()
1069 for (level = 0; level < display->wm.num_levels; level++) { in g4x_raw_plane_wm_compute()
1139 if (level >= display->wm.num_levels) in g4x_raw_crtc_wm_is_valid()
1491 display->wm.num_levels = VLV_WM_LEVEL_PM2 + 1; in vlv_setup_wm_latency()
1497 display->wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1; in vlv_setup_wm_latency()
1633 for (; level < display->wm.num_levels; level++) { in vlv_invalidate_wms()
1662 for (; level < display->wm.num_levels; level++) { in vlv_raw_plane_wm_set()
1686 for (level = 0; level < display->wm.num_levels; leve in vlv_raw_plane_wm_compute()
3106 int level, num_levels = display->wm.num_levels; ilk_wm_merge() local
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H A Dskl_watermark.c329 for (level = display->wm.num_levels - 1; in skl_crtc_can_enable_sagv()
648 for (level = 0; level < display->wm.num_levels; level++) { in skl_cursor_allocation()
1456 for (level = display->wm.num_levels - 1; level >= 0; level--) { in skl_crtc_allocate_plane_ddb()
1540 for (level++; level < display->wm.num_levels; level++) { in skl_crtc_allocate_plane_ddb()
1947 for (level = 0; level < display->wm.num_levels; level++) { in skl_compute_wm_levels()
2282 for (level = display->wm.num_levels - 1; level >= 0; level--) { in skl_max_wm_level_for_vblank()
2320 crtc_state->wm_level_disabled = level < display->wm.num_levels - 1; in skl_wm_check_vblank()
2322 for (level++; level < display->wm.num_levels; level++) { in skl_wm_check_vblank()
2404 for (level = 0; level < display->wm.num_levels; level++) { in skl_plane_wm_equals()
2769 for (level = 0; level < display->wm.num_levels; leve in skl_plane_selected_wm_equals()
3175 adjust_wm_latency(struct intel_display * display,u16 wm[],int num_levels,int read_latency) adjust_wm_latency() argument
3219 int num_levels = display->wm.num_levels; mtl_read_wm_latency() local
3239 int num_levels = display->wm.num_levels; skl_read_wm_latency() local
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c1295 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1297 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1299 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1301 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1303 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1305 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1307 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1318 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1320 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1333 clks.clocks_in_khz[clks.num_levels>> in bw_calcs_data_update_from_pplib()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/linux/arch/s390/kernel/
H A Dcache.c142 this_cpu_ci->num_levels = level; in init_cache_level()
156 for (idx = 0, level = 0; level < this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/accel/amdxdna/
H A Daie2_solver.h95 u32 num_levels; /* available power levels */ member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c160 unsigned int *num_levels) in dcn401_init_single_clock() argument
169 *num_levels = 2; in dcn401_init_single_clock()
172 /* will set num_levels to 0 on failure */ in dcn401_init_single_clock()
173 *num_levels = ret & 0xFF; in dcn401_init_single_clock()
175 /* if the initial message failed, num_levels will be 0 */ in dcn401_init_single_clock()
176 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
1379 unsigned int num_levels; in dcn401_get_memclk_states_from_smu() local
1408 num_levels = num_entries_per_clk->num_memclk_levels; in dcn401_get_memclk_states_from_smu()
1410 num_levels = num_entries_per_clk->num_fclk_levels; in dcn401_get_memclk_states_from_smu()
1413 clk_mgr_base->bw_params->clk_table.num_entries = num_levels in dcn401_get_memclk_states_from_smu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1321 ASSERT(fclks->num_levels); in dcn_bw_update_from_pplib_fclks()
1324 vmid0p72_idx = fclks->num_levels > 2 ? fclks->num_levels - 3 : 0; in dcn_bw_update_from_pplib_fclks()
1325 vnom0p8_idx = fclks->num_levels > 1 ? fclks->num_levels - 2 : 0; in dcn_bw_update_from_pplib_fclks()
1326 vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; in dcn_bw_update_from_pplib_fclks()
1348 if (dcfclks->num_levels >= 3) { in dcn_bw_update_from_pplib_dcfclks()
1350 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib_dcfclks()
1351 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels in dcn_bw_update_from_pplib_dcfclks()
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/linux/arch/loongarch/kernel/
H A Dcacheinfo.c17 this_cpu_ci->num_levels = in init_cache_level()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.c1782 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1789 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1808 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1817 new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
2246 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2252 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2264 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2275 for (i = 0; i < ps->num_levels; i++) { in kv_apply_state_adjust_rules()
2640 ps->num_levels = 1; in kv_patch_boot_state()
2685 ps->num_levels in kv_parse_pplib_clock_info()
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