Searched refs:num_fclk_levels (Results 1 – 10 of 10) sorted by relevance
90 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1; in dcn401_is_ppclk_dpm_enabled() 325 (clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels && in dcn401_is_dc_mode_present() 416 int dramclk_khz_override, fclk_khz_override, num_fclk_levels; in dcn401_auto_dpm_test_log() local 443 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1; in dcn401_auto_dpm_test_log() 449 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000; in dcn401_auto_dpm_test_log() 836 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence() 1401 &num_entries_per_clk->num_fclk_levels); in dcn401_get_memclk_states_from_smu() 1403 if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz == in dcn401_get_memclk_states_from_smu() 1404 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels in dcn401_get_memclk_states_from_smu() [all...]
512 int dramclk_khz_override, fclk_khz_override, num_fclk_levels; in dcn32_auto_dpm_test_log() local 541 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1; in dcn32_auto_dpm_test_log() 547 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000; in dcn32_auto_dpm_test_log() 1047 &num_entries_per_clk->num_fclk_levels); in dcn32_get_memclk_states_from_smu() 1050 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { in dcn32_get_memclk_states_from_smu() 1053 num_levels = num_entries_per_clk->num_fclk_levels; in dcn32_get_memclk_states_from_smu()
169 unsigned int num_fclk_levels; member
530 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) { in dml2_init_soc_states()
131 unsigned int num_fclk_levels; member
409 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn351_update_bw_bounding_box_fpu()
376 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn35_update_bw_bounding_box_fpu()
123 if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { in override_dml_init_with_values_from_smu() 124 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in override_dml_init_with_values_from_smu()
2862 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; in build_synthetic_soc_states() 3323 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn32_update_bw_bounding_box_fpu() 3324 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn32_update_bw_bounding_box_fpu() 3347 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
1024 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()