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Searched refs:num_clk_values (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/
H A Ddcn401_soc_and_ip_translator.c45 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
47 if (i < dml_clk_table->dcfclk.num_clk_values) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
52 dml_clk_table->dcfclk.num_clk_values = i + 1; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
55 dml_clk_table->dcfclk.num_clk_values = i; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
68 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
70 if (i < dml_clk_table->fclk.num_clk_values) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
75 dml_clk_table->fclk.num_clk_values = i + 1; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
78 dml_clk_table->fclk.num_clk_values = i; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
91 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
93 if (i < dml_clk_table->uclk.num_clk_values) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/
H A Ddml2_mcg_dcn4.c50 if (soc_bb->clk_table.dcfclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
62 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_fine_grained()
67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()
76 …ies[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_table.fclk.num_clk_values); in build_min_clk_table_fine_grained()
101 ….min_dcfclk_khz, soc_bb->clk_table.dcfclk.clk_values_khz, soc_bb->clk_table.dcfclk.num_clk_values); in build_min_clk_table_fine_grained()
137 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in build_min_clk_table_coarse_grained()
142 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
158 if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) in build_min_clock_table()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/
H A Ddcn4_soc_bb.h87 .num_clk_values = 1,
91 .num_clk_values = 2,
95 .num_clk_values = 2,
99 .num_clk_values = 2,
103 .num_clk_values = 2,
107 .num_clk_values = 2,
111 .num_clk_values = 2,
115 .num_clk_values = 2,
119 .num_clk_values = 2,
123 .num_clk_values = 2,
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/
H A Ddml2_dpmm_dcn4.c282 if (clock_table->num_clk_values > 2) { in round_up_and_copy_to_next_dpm()
283 while (index < clock_table->num_clk_values && clock_table->clk_values_khz[index] < min_value) in round_up_and_copy_to_next_dpm()
286 if (index < clock_table->num_clk_values) { in round_up_and_copy_to_next_dpm()
290 } else if (clock_table->clk_values_khz[clock_table->num_clk_values - 1] >= min_value) { in round_up_and_copy_to_next_dpm()
346 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
360 for (index = 0; index < state_table->uclk.num_clk_values; index++) { in map_soc_min_clocks_to_dpm_coarse_grained()
390 if (state_table->dcfclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
394 if (state_table->fclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
398 if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values && in map_min_clocks_to_dpm()
399 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/
H A Ddml21_wrapper.c153 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
155 …_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
160 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { in dml21_calculate_rq_and_dlg_params()
162 …lk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; in dml21_calculate_rq_and_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/
H A Ddml_top_soc_parameter_types.h111 unsigned char num_clk_values; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_utils.c540 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in dml2_core_utils_get_active_min_uclk_dpm_index()
H A Ddml2_core_dcn4.c534 for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) { in lookup_uclk_dpm_index_by_freq()
H A Ddml2_core_dcn4_calcs.c7136 for (i = 0; i < clk_table->uclk.num_clk_values; i++) { in get_active_min_uclk_dpm_index()
12038 …e_lib->soc.clk_table.uclk.clk_values_khz[mode_lib->soc.clk_table.uclk.num_clk_values - 1] / 1000.0; in dml_core_mode_programming()