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Searched refs:native_wrmsrq (Results 1 – 14 of 14) sorted by relevance

/linux/arch/x86/include/asm/
H A Dmicrocode.h68 native_wrmsrq(MSR_IA32_UCODE_REV, 0); in intel_get_microcode_revision()
H A Dspec-ctrl.h87 native_wrmsrq(MSR_IA32_SPEC_CTRL, val); in __update_spec_ctrl()
H A Dmsr.h101 #define native_wrmsrq(msr, val) \ macro
137 native_wrmsrq(msr, val); in native_write_msr()
H A Dapic.h213 native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); in native_apic_msr_eoi()
/linux/arch/x86/kernel/apic/
H A Dx2apic_savic.c336 native_wrmsrq(MSR_AMD64_SAVIC_CONTROL, 0); in savic_teardown()
368 native_wrmsrq(MSR_AMD64_SAVIC_CONTROL, in savic_setup()
/linux/arch/x86/kernel/cpu/
H A Dmshyperv.c92 native_wrmsrq(reg, sint.as_uint64); in hv_set_non_nested_msr()
95 native_wrmsrq(reg, value); in hv_set_non_nested_msr()
/linux/arch/x86/events/amd/
H A Dbrs.c47 native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); in set_debug_extn_cfg()
/linux/arch/x86/kernel/cpu/resctrl/
H A Dpseudo_lock.c166 native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); in resctrl_arch_pseudo_lock_fn()
/linux/arch/x86/hyperv/
H A Dhv_crash.c104 native_wrmsrq(HV_X64_MSR_RESET, 1); /* get hyp to reboot */ in hv_panic_timeout_reboot()
H A Divm.c122 native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); in wr_ghcb_msr()
/linux/arch/x86/kernel/cpu/microcode/
H A Dintel.c667 native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in __apply_microcode()
H A Damd.c702 native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr); in __apply_microcode_amd()
/linux/arch/x86/kvm/vmx/
H A Dvmx.c415 native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH); in vmx_l1d_flush()
482 native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr); in vmx_disable_fb_clear()
493 native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl); in vmx_enable_fb_clear()
7519 native_wrmsrq(MSR_IA32_SPEC_CTRL, hostval); in vmx_spec_ctrl_restore_host()
/linux/arch/x86/kernel/cpu/mce/
H A Dcore.c1349 native_wrmsrq(MSR_IA32_MCG_STATUS, 0); in mce_check_crashing_cpu()