| /linux/drivers/mtd/nand/ |
| H A D | qpic_common.c | 24 void qcom_free_bam_transaction(struct qcom_nand_controller *nandc) in qcom_free_bam_transaction() argument
26 struct bam_transaction *bam_txn = nandc->bam_txn; in qcom_free_bam_transaction()
39 qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc) in qcom_alloc_bam_transaction() argument
43 unsigned int num_cw = nandc->max_cwperpage; in qcom_alloc_bam_transaction()
82 void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc) in qcom_clear_bam_transaction() argument
84 struct bam_transaction *bam_txn = nandc->bam_txn; in qcom_clear_bam_transaction()
86 if (!nandc->props->supports_bam) in qcom_clear_bam_transaction()
120 inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu) in qcom_nandc_dev_to_mem() argument
122 if (!nandc->props->supports_bam) in qcom_nandc_dev_to_mem()
126 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in qcom_nandc_dev_to_mem()
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| /linux/drivers/mtd/nand/raw/ |
| H A D | qcom_nandc.c | 135 static u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
137 return ioread32(nandc->base + offset); in nandc_read()
140 static void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
143 iowrite32(val, nandc->base + offset); in nandc_write()
166 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_read_loc_first() local
175 nandc->regs->read_location0 = locreg_val; in nandc_set_read_loc_first()
177 nandc->regs->read_location1 = locreg_val; in nandc_set_read_loc_first()
179 nandc->regs->read_location2 = locreg_val; in nandc_set_read_loc_first()
181 nandc->regs->read_location3 = locreg_val; in nandc_set_read_loc_first()
198 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_read_loc_last() local
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| /linux/include/linux/mtd/ |
| H A D | nand-qpic-common.h | 188 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
457 void qcom_free_bam_transaction(struct qcom_nand_controller *nandc);
458 struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc);
459 void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc);
461 void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu);
462 int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
464 int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
466 int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
468 int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off,
470 int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs,
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7623a.dtsi | 123 &nandc {
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| H A D | mt7623a-rfb-nand.dts | 184 &nandc {
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| H A D | mt2701.dtsi | 362 nandc: nand-controller@1100d000 { label
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| H A D | mt7623.dtsi | 522 nandc: nfi@1100d000 { label
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| /linux/arch/mips/boot/dts/ingenic/ |
| H A D | rs90.dts | 248 nandc: nand-controller@1 { label
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| H A D | qi_lb60.dts | 256 nandc: nand-controller@1 { label
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| H A D | ci20.dts | 411 nandc: nand-controller@1 { label
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| /linux/arch/arm/boot/dts/renesas/ |
| H A D | r9a06g032.dtsi | 336 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622-rfb1.dts | 244 &nandc {
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| H A D | mt7622-bananapi-bpi-r64.dts | 262 &nandc {
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| H A D | mt7622.dtsi | 544 nandc: nand-controller@1100d000 { label
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| H A D | mt2712e.dtsi | 563 nandc: nand-controller@1100e000 { label
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3188.dtsi | 304 * The data pins are shared between nandc and emmc and
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| H A D | rk3066a.dtsi | 416 * The data pins are shared between nandc and emmc and
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| /linux/ |
| H A D | MAINTAINERS | 21805 F: Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
22400 F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
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