1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020 ARM Ltd.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/cpu.h>
8 #include <linux/kernel.h>
9 #include <linux/mm.h>
10 #include <linux/prctl.h>
11 #include <linux/sched.h>
12 #include <linux/sched/mm.h>
13 #include <linux/string.h>
14 #include <linux/swap.h>
15 #include <linux/swapops.h>
16 #include <linux/thread_info.h>
17 #include <linux/types.h>
18 #include <linux/uaccess.h>
19 #include <linux/uio.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/mte.h>
24 #include <asm/ptrace.h>
25 #include <asm/sysreg.h>
26
27 static DEFINE_PER_CPU_READ_MOSTLY(u64, mte_tcf_preferred);
28
29 #ifdef CONFIG_KASAN_HW_TAGS
30 /*
31 * The asynchronous and asymmetric MTE modes have the same behavior for
32 * store operations. This flag is set when either of these modes is enabled.
33 */
34 DEFINE_STATIC_KEY_FALSE(mte_async_or_asymm_mode);
35 EXPORT_SYMBOL_GPL(mte_async_or_asymm_mode);
36 #endif
37
mte_sync_tags(pte_t pte,unsigned int nr_pages)38 void mte_sync_tags(pte_t pte, unsigned int nr_pages)
39 {
40 struct page *page = pte_page(pte);
41 struct folio *folio = page_folio(page);
42 unsigned long i;
43
44 if (folio_test_hugetlb(folio)) {
45 unsigned long nr = folio_nr_pages(folio);
46
47 /* Hugetlb MTE flags are set for head page only */
48 if (folio_try_hugetlb_mte_tagging(folio)) {
49 for (i = 0; i < nr; i++, page++)
50 mte_clear_page_tags(page_address(page));
51 folio_set_hugetlb_mte_tagged(folio);
52 }
53
54 /* ensure the tags are visible before the PTE is set */
55 smp_wmb();
56
57 return;
58 }
59
60 /* if PG_mte_tagged is set, tags have already been initialised */
61 for (i = 0; i < nr_pages; i++, page++) {
62 if (try_page_mte_tagging(page)) {
63 mte_clear_page_tags(page_address(page));
64 set_page_mte_tagged(page);
65 }
66 }
67
68 /* ensure the tags are visible before the PTE is set */
69 smp_wmb();
70 }
71
memcmp_pages(struct page * page1,struct page * page2)72 int memcmp_pages(struct page *page1, struct page *page2)
73 {
74 char *addr1, *addr2;
75 int ret;
76
77 addr1 = page_address(page1);
78 addr2 = page_address(page2);
79 ret = memcmp(addr1, addr2, PAGE_SIZE);
80
81 if (!system_supports_mte() || ret)
82 return ret;
83
84 /*
85 * If the page content is identical but at least one of the pages is
86 * tagged, return non-zero to avoid KSM merging. If only one of the
87 * pages is tagged, __set_ptes() may zero or change the tags of the
88 * other page via mte_sync_tags().
89 */
90 if (page_mte_tagged(page1) || page_mte_tagged(page2))
91 return addr1 != addr2;
92
93 return ret;
94 }
95
__mte_enable_kernel(const char * mode,unsigned long tcf)96 static inline void __mte_enable_kernel(const char *mode, unsigned long tcf)
97 {
98 /* Enable MTE Sync Mode for EL1. */
99 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK,
100 SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf));
101 isb();
102
103 pr_info_once("MTE: enabled in %s mode at EL1\n", mode);
104 }
105
106 #ifdef CONFIG_KASAN_HW_TAGS
mte_enable_kernel_sync(void)107 void mte_enable_kernel_sync(void)
108 {
109 /*
110 * Make sure we enter this function when no PE has set
111 * async mode previously.
112 */
113 WARN_ONCE(system_uses_mte_async_or_asymm_mode(),
114 "MTE async mode enabled system wide!");
115
116 __mte_enable_kernel("synchronous", SCTLR_EL1_TCF_SYNC);
117 }
118
mte_enable_kernel_async(void)119 void mte_enable_kernel_async(void)
120 {
121 __mte_enable_kernel("asynchronous", SCTLR_EL1_TCF_ASYNC);
122
123 /*
124 * MTE async mode is set system wide by the first PE that
125 * executes this function.
126 *
127 * Note: If in future KASAN acquires a runtime switching
128 * mode in between sync and async, this strategy needs
129 * to be reviewed.
130 */
131 if (!system_uses_mte_async_or_asymm_mode())
132 static_branch_enable(&mte_async_or_asymm_mode);
133 }
134
mte_enable_kernel_asymm(void)135 void mte_enable_kernel_asymm(void)
136 {
137 if (cpus_have_cap(ARM64_MTE_ASYMM)) {
138 __mte_enable_kernel("asymmetric", SCTLR_EL1_TCF_ASYMM);
139
140 /*
141 * MTE asymm mode behaves as async mode for store
142 * operations. The mode is set system wide by the
143 * first PE that executes this function.
144 *
145 * Note: If in future KASAN acquires a runtime switching
146 * mode in between sync and async, this strategy needs
147 * to be reviewed.
148 */
149 if (!system_uses_mte_async_or_asymm_mode())
150 static_branch_enable(&mte_async_or_asymm_mode);
151 } else {
152 /*
153 * If the CPU does not support MTE asymmetric mode the
154 * kernel falls back on synchronous mode which is the
155 * default for kasan=on.
156 */
157 mte_enable_kernel_sync();
158 }
159 }
160
mte_enable_kernel_store_only(void)161 int mte_enable_kernel_store_only(void)
162 {
163 /*
164 * If the CPU does not support MTE store only,
165 * the kernel checks all operations.
166 */
167 if (!cpus_have_cap(ARM64_MTE_STORE_ONLY))
168 return -EINVAL;
169
170 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCSO_MASK,
171 SYS_FIELD_PREP(SCTLR_EL1, TCSO, 1));
172 isb();
173
174 pr_info_once("MTE: enabled store only mode at EL1\n");
175
176 return 0;
177 }
178 #endif
179
180 #ifdef CONFIG_KASAN_HW_TAGS
mte_check_tfsr_el1(void)181 void mte_check_tfsr_el1(void)
182 {
183 u64 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
184
185 if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) {
186 /*
187 * Note: isb() is not required after this direct write
188 * because there is no indirect read subsequent to it
189 * (per ARM DDI 0487F.c table D13-1).
190 */
191 write_sysreg_s(0, SYS_TFSR_EL1);
192
193 kasan_report_async();
194 }
195 }
196 #endif
197
198 /*
199 * This is where we actually resolve the system and process MTE mode
200 * configuration into an actual value in SCTLR_EL1 that affects
201 * userspace.
202 */
mte_update_sctlr_user(struct task_struct * task)203 static void mte_update_sctlr_user(struct task_struct *task)
204 {
205 /*
206 * This must be called with preemption disabled and can only be called
207 * on the current or next task since the CPU must match where the thread
208 * is going to run. The caller is responsible for calling
209 * update_sctlr_el1() later in the same preemption disabled block.
210 */
211 unsigned long sctlr = task->thread.sctlr_user;
212 unsigned long mte_ctrl = task->thread.mte_ctrl;
213 unsigned long pref, resolved_mte_tcf;
214
215 pref = __this_cpu_read(mte_tcf_preferred);
216 /*
217 * If there is no overlap between the system preferred and
218 * program requested values go with what was requested.
219 */
220 resolved_mte_tcf = (mte_ctrl & pref) ? pref : mte_ctrl;
221 sctlr &= ~(SCTLR_EL1_TCF0_MASK | SCTLR_EL1_TCSO0_MASK);
222 /*
223 * Pick an actual setting. The order in which we check for
224 * set bits and map into register values determines our
225 * default order.
226 */
227 if (resolved_mte_tcf & MTE_CTRL_TCF_ASYMM)
228 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYMM);
229 else if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC)
230 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, ASYNC);
231 else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC)
232 sctlr |= SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF0, SYNC);
233
234 if (mte_ctrl & MTE_CTRL_STORE_ONLY)
235 sctlr |= SYS_FIELD_PREP(SCTLR_EL1, TCSO0, 1);
236
237 task->thread.sctlr_user = sctlr;
238 }
239
mte_update_gcr_excl(struct task_struct * task)240 static void mte_update_gcr_excl(struct task_struct *task)
241 {
242 /*
243 * SYS_GCR_EL1 will be set to current->thread.mte_ctrl value by
244 * mte_set_user_gcr() in kernel_exit, but only if KASAN is enabled.
245 */
246 if (kasan_hw_tags_enabled())
247 return;
248
249 write_sysreg_s(
250 ((task->thread.mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
251 SYS_GCR_EL1_EXCL_MASK) | SYS_GCR_EL1_RRND,
252 SYS_GCR_EL1);
253 }
254
255 #ifdef CONFIG_KASAN_HW_TAGS
256 /* Only called from assembly, silence sparse */
257 void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
258 __le32 *updptr, int nr_inst);
259
kasan_hw_tags_enable(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)260 void __init kasan_hw_tags_enable(struct alt_instr *alt, __le32 *origptr,
261 __le32 *updptr, int nr_inst)
262 {
263 BUG_ON(nr_inst != 1); /* Branch -> NOP */
264
265 if (kasan_hw_tags_enabled())
266 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
267 }
268 #endif
269
mte_thread_init_user(void)270 void mte_thread_init_user(void)
271 {
272 if (!system_supports_mte())
273 return;
274
275 /* clear any pending asynchronous tag fault */
276 dsb(ish);
277 write_sysreg_s(0, SYS_TFSRE0_EL1);
278 clear_thread_flag(TIF_MTE_ASYNC_FAULT);
279 /* disable tag checking and reset tag generation mask */
280 set_mte_ctrl(current, 0);
281 }
282
mte_thread_switch(struct task_struct * next)283 void mte_thread_switch(struct task_struct *next)
284 {
285 if (!system_supports_mte())
286 return;
287
288 mte_update_sctlr_user(next);
289 mte_update_gcr_excl(next);
290
291 /* TCO may not have been disabled on exception entry for the current task. */
292 mte_disable_tco_entry(next);
293
294 if (!system_uses_mte_async_or_asymm_mode())
295 return;
296
297 /*
298 * Check if an async tag exception occurred at EL1.
299 *
300 * Note: On the context switch path we rely on the dsb() present
301 * in __switch_to() to guarantee that the indirect writes to TFSR_EL1
302 * are synchronized before this point.
303 */
304 isb();
305 mte_check_tfsr_el1();
306 }
307
mte_cpu_setup(void)308 void mte_cpu_setup(void)
309 {
310 u64 rgsr;
311
312 /*
313 * CnP must be enabled only after the MAIR_EL1 register has been set
314 * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
315 * lead to the wrong memory type being used for a brief window during
316 * CPU power-up.
317 *
318 * CnP is not a boot feature so MTE gets enabled before CnP, but let's
319 * make sure that is the case.
320 */
321 BUG_ON(read_sysreg(ttbr0_el1) & TTBRx_EL1_CnP);
322 BUG_ON(read_sysreg(ttbr1_el1) & TTBRx_EL1_CnP);
323
324 /* Normal Tagged memory type at the corresponding MAIR index */
325 sysreg_clear_set(mair_el1,
326 MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED),
327 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED,
328 MT_NORMAL_TAGGED));
329
330 write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1);
331
332 /*
333 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
334 * RGSR_EL1.SEED must be non-zero for IRG to produce
335 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
336 * must initialize it.
337 */
338 rgsr = (read_sysreg(CNTVCT_EL0) & SYS_RGSR_EL1_SEED_MASK) <<
339 SYS_RGSR_EL1_SEED_SHIFT;
340 if (rgsr == 0)
341 rgsr = 1 << SYS_RGSR_EL1_SEED_SHIFT;
342 write_sysreg_s(rgsr, SYS_RGSR_EL1);
343
344 /* clear any pending tag check faults in TFSR*_EL1 */
345 write_sysreg_s(0, SYS_TFSR_EL1);
346 write_sysreg_s(0, SYS_TFSRE0_EL1);
347
348 local_flush_tlb_all();
349 }
350
mte_suspend_enter(void)351 void mte_suspend_enter(void)
352 {
353 if (!system_supports_mte())
354 return;
355
356 if (!system_uses_mte_async_or_asymm_mode())
357 return;
358
359 /*
360 * The barriers are required to guarantee that the indirect writes
361 * to TFSR_EL1 are synchronized before we report the state.
362 */
363 dsb(nsh);
364 isb();
365
366 /* Report SYS_TFSR_EL1 before suspend entry */
367 mte_check_tfsr_el1();
368 }
369
mte_suspend_exit(void)370 void mte_suspend_exit(void)
371 {
372 if (!system_supports_mte())
373 return;
374
375 mte_cpu_setup();
376 }
377
set_mte_ctrl(struct task_struct * task,unsigned long arg)378 long set_mte_ctrl(struct task_struct *task, unsigned long arg)
379 {
380 u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &
381 SYS_GCR_EL1_EXCL_MASK) << MTE_CTRL_GCR_USER_EXCL_SHIFT;
382
383 if (!system_supports_mte())
384 return 0;
385
386 if (arg & PR_MTE_TCF_ASYNC)
387 mte_ctrl |= MTE_CTRL_TCF_ASYNC;
388 if (arg & PR_MTE_TCF_SYNC)
389 mte_ctrl |= MTE_CTRL_TCF_SYNC;
390
391 /*
392 * If the system supports it and both sync and async modes are
393 * specified then implicitly enable asymmetric mode.
394 * Userspace could see a mix of both sync and async anyway due
395 * to differing or changing defaults on CPUs.
396 */
397 if (cpus_have_cap(ARM64_MTE_ASYMM) &&
398 (arg & PR_MTE_TCF_ASYNC) &&
399 (arg & PR_MTE_TCF_SYNC))
400 mte_ctrl |= MTE_CTRL_TCF_ASYMM;
401
402 if (arg & PR_MTE_STORE_ONLY)
403 mte_ctrl |= MTE_CTRL_STORE_ONLY;
404
405 task->thread.mte_ctrl = mte_ctrl;
406 if (task == current) {
407 preempt_disable();
408 mte_update_sctlr_user(task);
409 mte_update_gcr_excl(task);
410 update_sctlr_el1(task->thread.sctlr_user);
411 preempt_enable();
412 }
413
414 return 0;
415 }
416
get_mte_ctrl(struct task_struct * task)417 long get_mte_ctrl(struct task_struct *task)
418 {
419 unsigned long ret;
420 u64 mte_ctrl = task->thread.mte_ctrl;
421 u64 incl = (~mte_ctrl >> MTE_CTRL_GCR_USER_EXCL_SHIFT) &
422 SYS_GCR_EL1_EXCL_MASK;
423
424 if (!system_supports_mte())
425 return 0;
426
427 ret = incl << PR_MTE_TAG_SHIFT;
428 if (mte_ctrl & MTE_CTRL_TCF_ASYNC)
429 ret |= PR_MTE_TCF_ASYNC;
430 if (mte_ctrl & MTE_CTRL_TCF_SYNC)
431 ret |= PR_MTE_TCF_SYNC;
432 if (mte_ctrl & MTE_CTRL_STORE_ONLY)
433 ret |= PR_MTE_STORE_ONLY;
434
435 return ret;
436 }
437
438 /*
439 * Access MTE tags in another process' address space as given in mm. Update
440 * the number of tags copied. Return 0 if any tags copied, error otherwise.
441 * Inspired by __access_remote_vm().
442 */
__access_remote_tags(struct mm_struct * mm,unsigned long addr,struct iovec * kiov,unsigned int gup_flags)443 static int __access_remote_tags(struct mm_struct *mm, unsigned long addr,
444 struct iovec *kiov, unsigned int gup_flags)
445 {
446 void __user *buf = kiov->iov_base;
447 size_t len = kiov->iov_len;
448 int err = 0;
449 int write = gup_flags & FOLL_WRITE;
450
451 if (!access_ok(buf, len))
452 return -EFAULT;
453
454 if (mmap_read_lock_killable(mm))
455 return -EIO;
456
457 while (len) {
458 struct vm_area_struct *vma;
459 unsigned long tags, offset;
460 void *maddr;
461 struct page *page = get_user_page_vma_remote(mm, addr,
462 gup_flags, &vma);
463 struct folio *folio;
464
465 if (IS_ERR(page)) {
466 err = PTR_ERR(page);
467 break;
468 }
469
470 /*
471 * Only copy tags if the page has been mapped as PROT_MTE
472 * (PG_mte_tagged set). Otherwise the tags are not valid and
473 * not accessible to user. Moreover, an mprotect(PROT_MTE)
474 * would cause the existing tags to be cleared if the page
475 * was never mapped with PROT_MTE.
476 */
477 if (!(vma->vm_flags & VM_MTE)) {
478 err = -EOPNOTSUPP;
479 put_page(page);
480 break;
481 }
482
483 folio = page_folio(page);
484 if (folio_test_hugetlb(folio))
485 WARN_ON_ONCE(!folio_test_hugetlb_mte_tagged(folio) &&
486 !is_huge_zero_folio(folio));
487 else
488 WARN_ON_ONCE(!page_mte_tagged(page) && !is_zero_page(page));
489
490 /* limit access to the end of the page */
491 offset = offset_in_page(addr);
492 tags = min(len, (PAGE_SIZE - offset) / MTE_GRANULE_SIZE);
493
494 maddr = page_address(page);
495 if (write) {
496 tags = mte_copy_tags_from_user(maddr + offset, buf, tags);
497 set_page_dirty_lock(page);
498 } else {
499 tags = mte_copy_tags_to_user(buf, maddr + offset, tags);
500 }
501 put_page(page);
502
503 /* error accessing the tracer's buffer */
504 if (!tags)
505 break;
506
507 len -= tags;
508 buf += tags;
509 addr += tags * MTE_GRANULE_SIZE;
510 }
511 mmap_read_unlock(mm);
512
513 /* return an error if no tags copied */
514 kiov->iov_len = buf - kiov->iov_base;
515 if (!kiov->iov_len) {
516 /* check for error accessing the tracee's address space */
517 if (err)
518 return -EIO;
519 else
520 return -EFAULT;
521 }
522
523 return 0;
524 }
525
526 /*
527 * Copy MTE tags in another process' address space at 'addr' to/from tracer's
528 * iovec buffer. Return 0 on success. Inspired by ptrace_access_vm().
529 */
access_remote_tags(struct task_struct * tsk,unsigned long addr,struct iovec * kiov,unsigned int gup_flags)530 static int access_remote_tags(struct task_struct *tsk, unsigned long addr,
531 struct iovec *kiov, unsigned int gup_flags)
532 {
533 struct mm_struct *mm;
534 int ret;
535
536 mm = get_task_mm(tsk);
537 if (!mm)
538 return -EPERM;
539
540 if (!tsk->ptrace || (current != tsk->parent) ||
541 ((get_dumpable(mm) != SUID_DUMP_USER) &&
542 !ptracer_capable(tsk, mm->user_ns))) {
543 mmput(mm);
544 return -EPERM;
545 }
546
547 ret = __access_remote_tags(mm, addr, kiov, gup_flags);
548 mmput(mm);
549
550 return ret;
551 }
552
mte_ptrace_copy_tags(struct task_struct * child,long request,unsigned long addr,unsigned long data)553 int mte_ptrace_copy_tags(struct task_struct *child, long request,
554 unsigned long addr, unsigned long data)
555 {
556 int ret;
557 struct iovec kiov;
558 struct iovec __user *uiov = (void __user *)data;
559 unsigned int gup_flags = FOLL_FORCE;
560
561 if (!system_supports_mte())
562 return -EIO;
563
564 if (get_user(kiov.iov_base, &uiov->iov_base) ||
565 get_user(kiov.iov_len, &uiov->iov_len))
566 return -EFAULT;
567
568 if (request == PTRACE_POKEMTETAGS)
569 gup_flags |= FOLL_WRITE;
570
571 /* align addr to the MTE tag granule */
572 addr &= MTE_GRANULE_MASK;
573
574 ret = access_remote_tags(child, addr, &kiov, gup_flags);
575 if (!ret)
576 ret = put_user(kiov.iov_len, &uiov->iov_len);
577
578 return ret;
579 }
580
mte_tcf_preferred_show(struct device * dev,struct device_attribute * attr,char * buf)581 static ssize_t mte_tcf_preferred_show(struct device *dev,
582 struct device_attribute *attr, char *buf)
583 {
584 switch (per_cpu(mte_tcf_preferred, dev->id)) {
585 case MTE_CTRL_TCF_ASYNC:
586 return sysfs_emit(buf, "async\n");
587 case MTE_CTRL_TCF_SYNC:
588 return sysfs_emit(buf, "sync\n");
589 case MTE_CTRL_TCF_ASYMM:
590 return sysfs_emit(buf, "asymm\n");
591 default:
592 return sysfs_emit(buf, "???\n");
593 }
594 }
595
mte_tcf_preferred_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)596 static ssize_t mte_tcf_preferred_store(struct device *dev,
597 struct device_attribute *attr,
598 const char *buf, size_t count)
599 {
600 u64 tcf;
601
602 if (sysfs_streq(buf, "async"))
603 tcf = MTE_CTRL_TCF_ASYNC;
604 else if (sysfs_streq(buf, "sync"))
605 tcf = MTE_CTRL_TCF_SYNC;
606 else if (cpus_have_cap(ARM64_MTE_ASYMM) && sysfs_streq(buf, "asymm"))
607 tcf = MTE_CTRL_TCF_ASYMM;
608 else
609 return -EINVAL;
610
611 device_lock(dev);
612 per_cpu(mte_tcf_preferred, dev->id) = tcf;
613 device_unlock(dev);
614
615 return count;
616 }
617 static DEVICE_ATTR_RW(mte_tcf_preferred);
618
register_mte_tcf_preferred_sysctl(void)619 static int register_mte_tcf_preferred_sysctl(void)
620 {
621 unsigned int cpu;
622
623 if (!system_supports_mte())
624 return 0;
625
626 for_each_possible_cpu(cpu) {
627 per_cpu(mte_tcf_preferred, cpu) = MTE_CTRL_TCF_ASYNC;
628 device_create_file(get_cpu_device(cpu),
629 &dev_attr_mte_tcf_preferred);
630 }
631
632 return 0;
633 }
634 subsys_initcall(register_mte_tcf_preferred_sysctl);
635
636 /*
637 * Return 0 on success, the number of bytes not probed otherwise.
638 */
mte_probe_user_range(const char __user * uaddr,size_t size)639 size_t mte_probe_user_range(const char __user *uaddr, size_t size)
640 {
641 const char __user *end = uaddr + size;
642 char val;
643
644 __raw_get_user(val, uaddr, efault);
645
646 uaddr = PTR_ALIGN(uaddr, MTE_GRANULE_SIZE);
647 while (uaddr < end) {
648 /*
649 * A read is sufficient for mte, the caller should have probed
650 * for the pte write permission if required.
651 */
652 __raw_get_user(val, uaddr, efault);
653 uaddr += MTE_GRANULE_SIZE;
654 }
655 (void)val;
656
657 return 0;
658
659 efault:
660 return end - uaddr;
661 }
662