Home
last modified time | relevance | path

Searched refs:msr_offset (Results 1 – 5 of 5) sorted by relevance

/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.c788 void read_hwp_cap(int cpu, struct msr_hwp_cap *cap, unsigned int msr_offset) in read_hwp_cap() argument
792 get_msr(cpu, msr_offset, &msr); in read_hwp_cap()
823 void read_hwp_request_msr(int cpu, struct msr_hwp_request *hwp_req, unsigned int msr_offset) in read_hwp_request_msr() argument
827 get_msr(cpu, msr_offset, &msr); in read_hwp_request_msr()
837 void write_hwp_request_msr(int cpu, struct msr_hwp_request *hwp_req, unsigned int msr_offset) in write_hwp_request_msr() argument
854 put_msr(cpu, msr_offset, msr); in write_hwp_request_msr()
1097 int msr_offset = MSR_HWP_REQUEST; in update_hwp_request_msr() local
1099 read_hwp_request_msr(cpu, &req, msr_offset); in update_hwp_request_msr()
1129 write_hwp_request_msr(cpu, &req, msr_offset); in update_hwp_request_msr()
1132 read_hwp_request_msr(cpu, &req, msr_offset); in update_hwp_request_msr()
[all …]
/linux/drivers/thermal/mediatek/
H A Dlvts_thermal.c162 u16 msr_offset; member
857 if (lvts_ctrl->lvts_data->msr_offset) in lvts_calibration_init()
858 lvts_ctrl->calibration[i] += lvts_ctrl->lvts_data->msr_offset; in lvts_calibration_init()
1173 if (lvts_ctrl->lvts_data->msr_offset) in lvts_ctrl_calibrate()
1174 writel(lvts_ctrl->lvts_data->msr_offset, in lvts_ctrl_calibrate()
2158 .msr_offset = LVTS_MSR_OFFSET_MT8196,
2170 .msr_offset = LVTS_MSR_OFFSET_MT8196,
/linux/arch/x86/events/intel/
H A Duncore_nhmex.c435 .msr_offset = NHMEX_B_MSR_OFFSET,
512 .msr_offset = NHMEX_S_MSR_OFFSET,
786 msr = er->msr + type->msr_offset * box->pmu->pmu_idx; in nhmex_mbox_hw_config()
938 .msr_offset = NHMEX_M_MSR_OFFSET,
1201 .msr_offset = NHMEX_R_MSR_OFFSET,
H A Duncore_snbep.c1039 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1799 .msr_offset = SNBEP_CBO_MSR_OFFSET,
2220 .msr_offset = KNL_CHA_MSR_OFFSET,
2783 .msr_offset = HSWEP_CBO_MSR_OFFSET,
2838 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
3200 .msr_offset = HSWEP_CBO_MSR_OFFSET,
3216 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
3609 .msr_offset = HSWEP_CBO_MSR_OFFSET,
3962 .msr_offset = SKX_IIO_MSR_OFFSET,
4067 .msr_offset = SKX_IRP_MSR_OFFSET,
[all …]
H A Dcore.c3153 int msr_offset; in intel_pmu_config_acr() local
3161 msr_offset = x86_pmu.addr_offset(idx, false); in intel_pmu_config_acr()
3165 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false); in intel_pmu_config_acr()
3169 wrmsrl(msr_b + msr_offset, mask); in intel_pmu_config_acr()
3174 wrmsrl(msr_c + msr_offset, reload); in intel_pmu_config_acr()