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Searched refs:mmVGA_RENDER_CONTROL (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v7_0.c288 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
290 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
H A Dgmc_v8_0.c463 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
465 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
H A Ddce_v8_0.c408 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v8_0_set_vga_render_state()
413 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
H A Ddce_v6_0.c414 WREG32(mmVGA_RENDER_CONTROL, in dce_v6_0_set_vga_render_state()
415 RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK); in dce_v6_0_set_vga_render_state()
H A Ddce_v10_0.c457 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
462 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4400 #define mmVGA_RENDER_CONTROL 0x00C0 macro
H A Ddce_8_0_d.h5133 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_10_0_d.h6016 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_11_0_d.h6093 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_11_2_d.h7767 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_12_0_offset.h554 #define mmVGA_RENDER_CONTROL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h17 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_3_0_1_offset.h148 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_1_0_offset.h388 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_2_1_0_offset.h88 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_3_0_2_offset.h32 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_2_0_0_offset.h32 #define mmVGA_RENDER_CONTROL … macro
H A Ddcn_3_0_0_offset.h14 #define mmVGA_RENDER_CONTROL … macro