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Searched refs:mmOTG5_OTG_COUNT_CONTROL_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h7438 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_1_0_offset.h9076 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_0_0_offset.h10107 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_0_offset.h9856 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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