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Searched refs:mmAZALIA_SOCCLK_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h208 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
H A Ddcn_3_0_3_offset.h1156 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
H A Ddcn_3_0_1_offset.h1357 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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H A Ddcn_1_0_offset.h1797 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_1_0_offset.h1403 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_2_offset.h1329 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_0_0_offset.h1441 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_0_offset.h1347 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h1475 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 macro
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