1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 #include "qp.h" 29 #include "macsec.h" 30 31 #define mlx5_ib_dbg(_dev, format, arg...) \ 32 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 33 __LINE__, current->pid, ##arg) 34 35 #define mlx5_ib_err(_dev, format, arg...) \ 36 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 37 __LINE__, current->pid, ##arg) 38 39 #define mlx5_ib_warn(_dev, format, arg...) \ 40 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 41 __LINE__, current->pid, ##arg) 42 43 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 44 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 45 __func__, __LINE__, current->pid, ##arg) 46 47 #define MLX5_IB_DEFAULT_UIDX 0xffffff 48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 49 50 static __always_inline unsigned long 51 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 52 unsigned int pgsz_shift) 53 { 54 unsigned int largest_pg_shift = 55 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 56 BITS_PER_LONG - 1); 57 58 /* 59 * Despite a command allowing it, the device does not support lower than 60 * 4k page size. 61 */ 62 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 63 return GENMASK(largest_pg_shift, pgsz_shift); 64 } 65 66 static __always_inline unsigned long 67 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 68 unsigned int offset_shift) 69 { 70 unsigned int largest_offset_shift = 71 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 72 BITS_PER_LONG - 1); 73 74 return GENMASK(largest_offset_shift, offset_shift); 75 } 76 77 /* 78 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 79 * page_offset_quantized * (page_size/scale) = page_offset 80 * Which restricts allowed page sizes to ones that satisify the above. 81 */ 82 unsigned long __mlx5_umem_find_best_quantized_pgoff( 83 struct ib_umem *umem, unsigned long pgsz_bitmap, 84 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 85 unsigned int *page_offset_quantized); 86 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 87 pgsz_shift, page_offset_fld, \ 88 scale, page_offset_quantized) \ 89 __mlx5_umem_find_best_quantized_pgoff( \ 90 umem, \ 91 __mlx5_log_page_size_to_bitmap( \ 92 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 93 __mlx5_bit_sz(typ, page_offset_fld), \ 94 GENMASK(31, order_base_2(scale)), scale, \ 95 page_offset_quantized) 96 97 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 98 pgsz_shift, page_offset_fld, \ 99 scale, page_offset_quantized) \ 100 __mlx5_umem_find_best_quantized_pgoff( \ 101 umem, \ 102 __mlx5_log_page_size_to_bitmap( \ 103 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 104 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 105 page_offset_quantized) 106 107 enum { 108 MLX5_IB_MMAP_OFFSET_START = 9, 109 MLX5_IB_MMAP_OFFSET_END = 255, 110 }; 111 112 enum { 113 MLX5_IB_MMAP_CMD_SHIFT = 8, 114 MLX5_IB_MMAP_CMD_MASK = 0xff, 115 }; 116 117 enum { 118 MLX5_RES_SCAT_DATA32_CQE = 0x1, 119 MLX5_RES_SCAT_DATA64_CQE = 0x2, 120 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 121 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 122 }; 123 124 enum mlx5_ib_mad_ifc_flags { 125 MLX5_MAD_IFC_IGNORE_MKEY = 1, 126 MLX5_MAD_IFC_IGNORE_BKEY = 2, 127 MLX5_MAD_IFC_NET_VIEW = 4, 128 }; 129 130 enum { 131 MLX5_CROSS_CHANNEL_BFREG = 0, 132 }; 133 134 enum { 135 MLX5_CQE_VERSION_V0, 136 MLX5_CQE_VERSION_V1, 137 }; 138 139 enum { 140 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 141 MLX5_TM_MAX_SGE = 1, 142 }; 143 144 enum { 145 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 146 MLX5_IB_INVALID_BFREG = BIT(31), 147 }; 148 149 enum { 150 MLX5_MAX_MEMIC_PAGES = 0x100, 151 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 152 }; 153 154 enum { 155 MLX5_MEMIC_BASE_ALIGN = 6, 156 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 157 }; 158 159 enum mlx5_ib_mmap_type { 160 MLX5_IB_MMAP_TYPE_MEMIC = 1, 161 MLX5_IB_MMAP_TYPE_VAR = 2, 162 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 163 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 164 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 165 }; 166 167 struct mlx5_bfreg_info { 168 u32 *sys_pages; 169 int num_low_latency_bfregs; 170 unsigned int *count; 171 172 /* 173 * protect bfreg allocation data structs 174 */ 175 struct mutex lock; 176 u32 ver; 177 u8 lib_uar_4k : 1; 178 u8 lib_uar_dyn : 1; 179 u32 num_sys_pages; 180 u32 num_static_sys_pages; 181 u32 total_num_bfregs; 182 u32 num_dyn_bfregs; 183 }; 184 185 struct mlx5_ib_ucontext { 186 struct ib_ucontext ibucontext; 187 struct list_head db_page_list; 188 189 /* protect doorbell record alloc/free 190 */ 191 struct mutex db_page_mutex; 192 struct mlx5_bfreg_info bfregi; 193 u8 cqe_version; 194 /* Transport Domain number */ 195 u32 tdn; 196 197 u64 lib_caps; 198 u16 devx_uid; 199 /* For RoCE LAG TX affinity */ 200 atomic_t tx_port_affinity; 201 }; 202 203 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 204 { 205 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 206 } 207 208 struct mlx5_ib_pd { 209 struct ib_pd ibpd; 210 u32 pdn; 211 u16 uid; 212 }; 213 214 enum { 215 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 216 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 217 MLX5_IB_FLOW_ACTION_DECAP, 218 }; 219 220 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 221 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 222 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 223 #error "Invalid number of bypass priorities" 224 #endif 225 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 226 227 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 228 #define MLX5_IB_NUM_SNIFFER_FTS 2 229 #define MLX5_IB_NUM_EGRESS_FTS 1 230 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 231 232 struct mlx5_ib_anchor { 233 struct mlx5_flow_table *ft; 234 struct mlx5_flow_group *fg_goto_table; 235 struct mlx5_flow_group *fg_drop; 236 struct mlx5_flow_handle *rule_goto_table; 237 struct mlx5_flow_handle *rule_drop; 238 unsigned int rule_goto_table_ref; 239 }; 240 241 struct mlx5_ib_flow_prio { 242 struct mlx5_flow_table *flow_table; 243 struct mlx5_ib_anchor anchor; 244 unsigned int refcount; 245 }; 246 247 struct mlx5_ib_flow_handler { 248 struct list_head list; 249 struct ib_flow ibflow; 250 struct mlx5_ib_flow_prio *prio; 251 struct mlx5_flow_handle *rule; 252 struct ib_counters *ibcounters; 253 struct mlx5_ib_dev *dev; 254 struct mlx5_ib_flow_matcher *flow_matcher; 255 }; 256 257 struct mlx5_ib_flow_matcher { 258 struct mlx5_ib_match_params matcher_mask; 259 int mask_len; 260 enum mlx5_ib_flow_type flow_type; 261 enum mlx5_flow_namespace_type ns_type; 262 u16 priority; 263 struct mlx5_core_dev *mdev; 264 atomic_t usecnt; 265 u8 match_criteria_enable; 266 u32 ib_port; 267 }; 268 269 struct mlx5_ib_steering_anchor { 270 struct mlx5_ib_flow_prio *ft_prio; 271 struct mlx5_ib_dev *dev; 272 atomic_t usecnt; 273 }; 274 275 struct mlx5_ib_pp { 276 u16 index; 277 struct mlx5_core_dev *mdev; 278 }; 279 280 enum mlx5_ib_optional_counter_type { 281 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 282 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 283 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 284 MLX5_IB_OPCOUNTER_RDMA_TX_PACKETS, 285 MLX5_IB_OPCOUNTER_RDMA_TX_BYTES, 286 MLX5_IB_OPCOUNTER_RDMA_RX_PACKETS, 287 MLX5_IB_OPCOUNTER_RDMA_RX_BYTES, 288 289 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS_PER_QP, 290 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS_PER_QP, 291 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS_PER_QP, 292 MLX5_IB_OPCOUNTER_RDMA_TX_PACKETS_PER_QP, 293 MLX5_IB_OPCOUNTER_RDMA_TX_BYTES_PER_QP, 294 MLX5_IB_OPCOUNTER_RDMA_RX_PACKETS_PER_QP, 295 MLX5_IB_OPCOUNTER_RDMA_RX_BYTES_PER_QP, 296 297 MLX5_IB_OPCOUNTER_MAX, 298 }; 299 300 struct mlx5_ib_flow_db { 301 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 302 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 303 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 304 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 305 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 306 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 307 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 308 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 309 struct mlx5_ib_flow_prio *rdma_transport_rx[MLX5_RDMA_TRANSPORT_BYPASS_PRIO]; 310 struct mlx5_ib_flow_prio *rdma_transport_tx[MLX5_RDMA_TRANSPORT_BYPASS_PRIO]; 311 /* Protect flow steering bypass flow tables 312 * when add/del flow rules. 313 * only single add/removal of flow steering rule could be done 314 * simultaneously. 315 */ 316 struct mutex lock; 317 }; 318 319 /* Use macros here so that don't have to duplicate 320 * enum ib_qp_type for low-level driver 321 */ 322 323 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 324 /* 325 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 326 * creates the actual hardware QP. 327 */ 328 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 329 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 330 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 331 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 332 333 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 334 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 335 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 336 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 337 #define MLX5_IB_UPD_XLT_PD BIT(4) 338 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 339 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 340 #define MLX5_IB_UPD_XLT_DOWNGRADE BIT(7) 341 #define MLX5_IB_UPD_XLT_KEEP_PGSZ BIT(8) 342 343 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 344 * 345 * These flags are intended for internal use by the mlx5_ib driver, and they 346 * rely on the range reserved for that use in the ib_qp_create_flags enum. 347 */ 348 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 349 350 struct wr_list { 351 u16 opcode; 352 u16 next; 353 }; 354 355 enum mlx5_ib_rq_flags { 356 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 357 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 358 }; 359 360 struct mlx5_ib_wq { 361 struct mlx5_frag_buf_ctrl fbc; 362 u64 *wrid; 363 u32 *wr_data; 364 struct wr_list *w_list; 365 unsigned *wqe_head; 366 u16 unsig_count; 367 368 /* serialize post to the work queue 369 */ 370 spinlock_t lock; 371 int wqe_cnt; 372 int max_post; 373 int max_gs; 374 int offset; 375 int wqe_shift; 376 unsigned head; 377 unsigned tail; 378 u16 cur_post; 379 u16 last_poll; 380 void *cur_edge; 381 }; 382 383 enum mlx5_ib_wq_flags { 384 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 385 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 386 }; 387 388 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 389 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 390 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 391 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 392 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 393 394 struct mlx5_ib_rwq { 395 struct ib_wq ibwq; 396 struct mlx5_core_qp core_qp; 397 u32 rq_num_pas; 398 u32 log_rq_stride; 399 u32 log_rq_size; 400 u32 rq_page_offset; 401 u32 log_page_size; 402 u32 log_num_strides; 403 u32 two_byte_shift_en; 404 u32 single_stride_log_num_of_bytes; 405 struct ib_umem *umem; 406 size_t buf_size; 407 unsigned int page_shift; 408 struct mlx5_db db; 409 u32 user_index; 410 u32 wqe_count; 411 u32 wqe_shift; 412 int wq_sig; 413 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 414 }; 415 416 struct mlx5_ib_rwq_ind_table { 417 struct ib_rwq_ind_table ib_rwq_ind_tbl; 418 u32 rqtn; 419 u16 uid; 420 }; 421 422 struct mlx5_ib_ubuffer { 423 struct ib_umem *umem; 424 int buf_size; 425 u64 buf_addr; 426 }; 427 428 struct mlx5_ib_qp_base { 429 struct mlx5_ib_qp *container_mibqp; 430 struct mlx5_core_qp mqp; 431 struct mlx5_ib_ubuffer ubuffer; 432 }; 433 434 struct mlx5_ib_qp_trans { 435 struct mlx5_ib_qp_base base; 436 u16 xrcdn; 437 u32 alt_port; 438 u8 atomic_rd_en; 439 u8 resp_depth; 440 }; 441 442 struct mlx5_ib_rss_qp { 443 u32 tirn; 444 }; 445 446 struct mlx5_ib_rq { 447 struct mlx5_ib_qp_base base; 448 struct mlx5_ib_wq *rq; 449 struct mlx5_ib_ubuffer ubuffer; 450 struct mlx5_db *doorbell; 451 u32 tirn; 452 u8 state; 453 u32 flags; 454 }; 455 456 struct mlx5_ib_sq { 457 struct mlx5_ib_qp_base base; 458 struct mlx5_ib_wq *sq; 459 struct mlx5_ib_ubuffer ubuffer; 460 struct mlx5_db *doorbell; 461 struct mlx5_flow_handle *flow_rule; 462 u32 tisn; 463 u8 state; 464 }; 465 466 struct mlx5_ib_raw_packet_qp { 467 struct mlx5_ib_sq sq; 468 struct mlx5_ib_rq rq; 469 }; 470 471 struct mlx5_bf { 472 int buf_size; 473 unsigned long offset; 474 struct mlx5_sq_bfreg *bfreg; 475 }; 476 477 struct mlx5_ib_dct { 478 struct mlx5_core_dct mdct; 479 u32 *in; 480 }; 481 482 struct mlx5_ib_gsi_qp { 483 struct ib_qp *rx_qp; 484 u32 port_num; 485 struct ib_qp_cap cap; 486 struct ib_cq *cq; 487 struct mlx5_ib_gsi_wr *outstanding_wrs; 488 u32 outstanding_pi, outstanding_ci; 489 int num_qps; 490 /* Protects access to the tx_qps. Post send operations synchronize 491 * with tx_qp creation in setup_qp(). Also protects the 492 * outstanding_wrs array and indices. 493 */ 494 spinlock_t lock; 495 struct ib_qp **tx_qps; 496 }; 497 498 struct mlx5_ib_qp { 499 struct ib_qp ibqp; 500 union { 501 struct mlx5_ib_qp_trans trans_qp; 502 struct mlx5_ib_raw_packet_qp raw_packet_qp; 503 struct mlx5_ib_rss_qp rss_qp; 504 struct mlx5_ib_dct dct; 505 struct mlx5_ib_gsi_qp gsi; 506 }; 507 struct mlx5_frag_buf buf; 508 509 struct mlx5_db db; 510 struct mlx5_ib_wq rq; 511 512 u8 sq_signal_bits; 513 u8 next_fence; 514 struct mlx5_ib_wq sq; 515 516 /* serialize qp state modifications 517 */ 518 struct mutex mutex; 519 /* cached variant of create_flags from struct ib_qp_init_attr */ 520 u32 flags; 521 u32 port; 522 u8 state; 523 int max_inline_data; 524 struct mlx5_bf bf; 525 u8 has_rq:1; 526 u8 is_rss:1; 527 u8 is_ooo_rq:1; 528 529 /* only for user space QPs. For kernel 530 * we have it from the bf object 531 */ 532 int bfregn; 533 534 struct list_head qps_list; 535 struct list_head cq_recv_list; 536 struct list_head cq_send_list; 537 struct mlx5_rate_limit rl; 538 u32 underlay_qpn; 539 u32 flags_en; 540 /* 541 * IB/core doesn't store low-level QP types, so 542 * store both MLX and IBTA types in the field below. 543 */ 544 enum ib_qp_type type; 545 /* A flag to indicate if there's a new counter is configured 546 * but not take effective 547 */ 548 u32 counter_pending; 549 u16 gsi_lag_port; 550 }; 551 552 struct mlx5_ib_cq_buf { 553 struct mlx5_frag_buf_ctrl fbc; 554 struct mlx5_frag_buf frag_buf; 555 struct ib_umem *umem; 556 int cqe_size; 557 int nent; 558 }; 559 560 enum mlx5_ib_cq_pr_flags { 561 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 562 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 563 }; 564 565 struct mlx5_ib_cq { 566 struct ib_cq ibcq; 567 struct mlx5_core_cq mcq; 568 struct mlx5_ib_cq_buf buf; 569 struct mlx5_db db; 570 571 /* serialize access to the CQ 572 */ 573 spinlock_t lock; 574 575 /* protect resize cq 576 */ 577 struct mutex resize_mutex; 578 struct mlx5_ib_cq_buf *resize_buf; 579 struct ib_umem *resize_umem; 580 int cqe_size; 581 struct list_head list_send_qp; 582 struct list_head list_recv_qp; 583 u32 create_flags; 584 struct list_head wc_list; 585 enum ib_cq_notify_flags notify_flags; 586 struct work_struct notify_work; 587 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 588 }; 589 590 struct mlx5_ib_wc { 591 struct ib_wc wc; 592 struct list_head list; 593 }; 594 595 struct mlx5_ib_srq { 596 struct ib_srq ibsrq; 597 struct mlx5_core_srq msrq; 598 struct mlx5_frag_buf buf; 599 struct mlx5_db db; 600 struct mlx5_frag_buf_ctrl fbc; 601 u64 *wrid; 602 /* protect SRQ hanlding 603 */ 604 spinlock_t lock; 605 int head; 606 int tail; 607 u16 wqe_ctr; 608 struct ib_umem *umem; 609 /* serialize arming a SRQ 610 */ 611 struct mutex mutex; 612 int wq_sig; 613 }; 614 615 struct mlx5_ib_xrcd { 616 struct ib_xrcd ibxrcd; 617 u32 xrcdn; 618 }; 619 620 enum mlx5_ib_mtt_access_flags { 621 MLX5_IB_MTT_READ = (1 << 0), 622 MLX5_IB_MTT_WRITE = (1 << 1), 623 }; 624 625 struct mlx5_user_mmap_entry { 626 struct rdma_user_mmap_entry rdma_entry; 627 u8 mmap_flag; 628 u64 address; 629 u32 page_idx; 630 }; 631 632 enum mlx5_mkey_type { 633 MLX5_MKEY_MR = 1, 634 MLX5_MKEY_MW, 635 MLX5_MKEY_INDIRECT_DEVX, 636 MLX5_MKEY_NULL, 637 MLX5_MKEY_IMPLICIT_CHILD, 638 }; 639 640 /* Used for non-existent ph value */ 641 #define MLX5_IB_NO_PH 0xff 642 643 struct mlx5r_cache_rb_key { 644 u8 ats:1; 645 u8 ph; 646 u16 st_index; 647 unsigned int access_mode; 648 unsigned int access_flags; 649 unsigned int ndescs; 650 }; 651 652 struct mlx5_ib_mkey { 653 u32 key; 654 enum mlx5_mkey_type type; 655 unsigned int ndescs; 656 struct wait_queue_head wait; 657 refcount_t usecount; 658 /* Cacheable user Mkey must hold either a rb_key or a cache_ent. */ 659 struct mlx5r_cache_rb_key rb_key; 660 struct mlx5_cache_ent *cache_ent; 661 u8 cacheable : 1; 662 }; 663 664 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 665 666 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 667 IB_ACCESS_REMOTE_WRITE |\ 668 IB_ACCESS_REMOTE_READ |\ 669 IB_ACCESS_REMOTE_ATOMIC |\ 670 IB_ZERO_BASED) 671 672 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 673 IB_ACCESS_REMOTE_WRITE |\ 674 IB_ACCESS_REMOTE_READ |\ 675 IB_ZERO_BASED) 676 677 #define mlx5_update_odp_stats(mr, counter_name, value) \ 678 atomic64_add(value, &((mr)->odp_stats.counter_name)) 679 680 #define mlx5_update_odp_stats_with_handled(mr, counter_name, value) \ 681 do { \ 682 mlx5_update_odp_stats(mr, counter_name, value); \ 683 atomic64_add(1, &((mr)->odp_stats.counter_name##_handled)); \ 684 } while (0) 685 686 struct mlx5_ib_mr { 687 struct ib_mr ibmr; 688 struct mlx5_ib_mkey mmkey; 689 690 struct ib_umem *umem; 691 /* The mr is data direct related */ 692 u8 data_direct :1; 693 694 union { 695 /* Used only by kernel MRs (umem == NULL) */ 696 struct { 697 void *descs; 698 void *descs_alloc; 699 dma_addr_t desc_map; 700 int max_descs; 701 int desc_size; 702 int access_mode; 703 704 /* For Kernel IB_MR_TYPE_INTEGRITY */ 705 struct mlx5_core_sig_ctx *sig; 706 struct mlx5_ib_mr *pi_mr; 707 struct mlx5_ib_mr *klm_mr; 708 struct mlx5_ib_mr *mtt_mr; 709 u64 data_iova; 710 u64 pi_iova; 711 int meta_ndescs; 712 int meta_length; 713 int data_length; 714 }; 715 716 /* Used only by User MRs (umem != NULL) */ 717 struct { 718 unsigned int page_shift; 719 /* Current access_flags */ 720 int access_flags; 721 722 /* For User ODP */ 723 struct mlx5_ib_mr *parent; 724 struct xarray implicit_children; 725 union { 726 struct work_struct work; 727 } odp_destroy; 728 struct ib_odp_counters odp_stats; 729 bool is_odp_implicit; 730 /* The affilated data direct crossed mr */ 731 struct mlx5_ib_mr *dd_crossed_mr; 732 struct list_head dd_node; 733 u8 revoked :1; 734 /* Indicates previous dmabuf page fault occurred */ 735 u8 dmabuf_faulted:1; 736 struct mlx5_ib_mkey null_mmkey; 737 }; 738 }; 739 }; 740 741 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 742 { 743 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 744 mr->umem->is_odp; 745 } 746 747 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 748 { 749 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 750 mr->umem->is_dmabuf; 751 } 752 753 struct mlx5_ib_mw { 754 struct ib_mw ibmw; 755 struct mlx5_ib_mkey mmkey; 756 }; 757 758 struct mlx5_ib_umr_context { 759 struct ib_cqe cqe; 760 enum ib_wc_status status; 761 struct completion done; 762 }; 763 764 enum { 765 MLX5_UMR_STATE_UNINIT, 766 MLX5_UMR_STATE_ACTIVE, 767 MLX5_UMR_STATE_RECOVER, 768 MLX5_UMR_STATE_ERR, 769 }; 770 771 struct umr_common { 772 struct ib_pd *pd; 773 struct ib_cq *cq; 774 struct ib_qp *qp; 775 /* Protects from UMR QP overflow 776 */ 777 struct semaphore sem; 778 /* Protects from using UMR while the UMR is not active 779 */ 780 struct mutex lock; 781 unsigned int state; 782 /* Protects from repeat UMR QP creation */ 783 struct mutex init_lock; 784 }; 785 786 #define NUM_MKEYS_PER_PAGE \ 787 ((PAGE_SIZE - sizeof(struct list_head)) / sizeof(u32)) 788 789 struct mlx5_mkeys_page { 790 u32 mkeys[NUM_MKEYS_PER_PAGE]; 791 struct list_head list; 792 }; 793 static_assert(sizeof(struct mlx5_mkeys_page) == PAGE_SIZE); 794 795 struct mlx5_mkeys_queue { 796 struct list_head pages_list; 797 u32 num_pages; 798 unsigned long ci; 799 spinlock_t lock; /* sync list ops */ 800 }; 801 802 struct mlx5_cache_ent { 803 struct mlx5_mkeys_queue mkeys_queue; 804 u32 pending; 805 806 char name[4]; 807 808 struct rb_node node; 809 struct mlx5r_cache_rb_key rb_key; 810 811 u8 is_tmp:1; 812 u8 disabled:1; 813 u8 fill_to_high_water:1; 814 u8 tmp_cleanup_scheduled:1; 815 816 /* 817 * - limit is the low water mark for stored mkeys, 2* limit is the 818 * upper water mark. 819 */ 820 u32 in_use; 821 u32 limit; 822 823 /* Statistics */ 824 u32 miss; 825 826 struct mlx5_ib_dev *dev; 827 struct delayed_work dwork; 828 }; 829 830 struct mlx5r_async_create_mkey { 831 union { 832 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 833 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 834 }; 835 struct mlx5_async_work cb_work; 836 struct mlx5_cache_ent *ent; 837 u32 mkey; 838 }; 839 840 struct mlx5_mkey_cache { 841 struct workqueue_struct *wq; 842 struct rb_root rb_root; 843 struct mutex rb_lock; 844 struct dentry *fs_root; 845 unsigned long last_add; 846 }; 847 848 struct mlx5_ib_port_resources { 849 struct mlx5_ib_gsi_qp *gsi; 850 struct work_struct pkey_change_work; 851 }; 852 853 struct mlx5_data_direct_resources { 854 u32 pdn; 855 u32 mkey; 856 u32 mkey_ro; 857 u8 mkey_ro_valid :1; 858 }; 859 860 struct mlx5_ib_resources { 861 struct ib_cq *c0; 862 struct mutex cq_lock; 863 u32 xrcdn0; 864 u32 xrcdn1; 865 struct ib_pd *p0; 866 struct ib_srq *s0; 867 struct ib_srq *s1; 868 struct mutex srq_lock; 869 struct mlx5_ib_port_resources ports[2]; 870 }; 871 872 #define MAX_OPFC_RULES 2 873 874 struct mlx5_ib_op_fc { 875 struct mlx5_fc *fc; 876 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 877 }; 878 879 struct mlx5_ib_counters { 880 struct rdma_stat_desc *descs; 881 size_t *offsets; 882 u32 num_q_counters; 883 u32 num_cong_counters; 884 u32 num_ext_ppcnt_counters; 885 u32 num_op_counters; 886 u16 set_id; 887 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 888 }; 889 890 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 891 struct mlx5_ib_op_fc *opfc, 892 enum mlx5_ib_optional_counter_type type); 893 894 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 895 struct mlx5_ib_op_fc *opfc, 896 enum mlx5_ib_optional_counter_type type); 897 898 int mlx5r_fs_bind_op_fc(struct ib_qp *qp, 899 struct mlx5_fc *fc_arr[MLX5_IB_OPCOUNTER_MAX], 900 struct xarray *qpn_opfc_xa, u32 port); 901 902 void mlx5r_fs_unbind_op_fc(struct ib_qp *qp, struct xarray *qpn_opfc_xa); 903 904 void mlx5r_fs_destroy_fcs(struct mlx5_ib_dev *dev, 905 struct mlx5_fc *fc_arr[MLX5_IB_OPCOUNTER_MAX]); 906 907 struct mlx5_ib_multiport_info; 908 909 struct mlx5_ib_multiport { 910 struct mlx5_ib_multiport_info *mpi; 911 /* To be held when accessing the multiport info */ 912 spinlock_t mpi_lock; 913 }; 914 915 struct mlx5_roce { 916 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 917 * netdev pointer 918 */ 919 struct notifier_block nb; 920 struct netdev_net_notifier nn; 921 struct notifier_block mdev_nb; 922 struct net_device *tracking_netdev; 923 atomic_t tx_port_affinity; 924 enum ib_port_state last_port_state; 925 struct mlx5_ib_dev *dev; 926 u32 native_port_num; 927 }; 928 929 struct mlx5_ib_port { 930 struct mlx5_ib_counters cnts; 931 struct mlx5_ib_multiport mp; 932 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 933 struct mlx5_roce roce; 934 struct mlx5_eswitch_rep *rep; 935 #ifdef CONFIG_MLX5_MACSEC 936 struct mlx5_reserved_gids *reserved_gids; 937 #endif 938 }; 939 940 struct mlx5_ib_dbg_param { 941 int offset; 942 struct mlx5_ib_dev *dev; 943 struct dentry *dentry; 944 u32 port_num; 945 }; 946 947 enum mlx5_ib_dbg_cc_types { 948 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 949 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 950 MLX5_IB_DBG_CC_RP_TIME_RESET, 951 MLX5_IB_DBG_CC_RP_BYTE_RESET, 952 MLX5_IB_DBG_CC_RP_THRESHOLD, 953 MLX5_IB_DBG_CC_RP_AI_RATE, 954 MLX5_IB_DBG_CC_RP_MAX_RATE, 955 MLX5_IB_DBG_CC_RP_HAI_RATE, 956 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 957 MLX5_IB_DBG_CC_RP_MIN_RATE, 958 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 959 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 960 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 961 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 962 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 963 MLX5_IB_DBG_CC_RP_GD, 964 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 965 MLX5_IB_DBG_CC_NP_CNP_DSCP, 966 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 967 MLX5_IB_DBG_CC_NP_CNP_PRIO, 968 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 969 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 970 MLX5_IB_DBG_CC_MAX, 971 }; 972 973 struct mlx5_ib_dbg_cc_params { 974 struct dentry *root; 975 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 976 }; 977 978 enum { 979 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 980 }; 981 982 struct mlx5_ib_delay_drop { 983 struct mlx5_ib_dev *dev; 984 struct work_struct delay_drop_work; 985 /* serialize setting of delay drop */ 986 struct mutex lock; 987 u32 timeout; 988 bool activate; 989 atomic_t events_cnt; 990 atomic_t rqs_cnt; 991 struct dentry *dir_debugfs; 992 }; 993 994 enum mlx5_ib_stages { 995 MLX5_IB_STAGE_INIT, 996 MLX5_IB_STAGE_FS, 997 MLX5_IB_STAGE_CAPS, 998 MLX5_IB_STAGE_NON_DEFAULT_CB, 999 MLX5_IB_STAGE_ROCE, 1000 MLX5_IB_STAGE_QP, 1001 MLX5_IB_STAGE_SRQ, 1002 MLX5_IB_STAGE_DEVICE_RESOURCES, 1003 MLX5_IB_STAGE_ODP, 1004 MLX5_IB_STAGE_COUNTERS, 1005 MLX5_IB_STAGE_CONG_DEBUGFS, 1006 MLX5_IB_STAGE_BFREG, 1007 MLX5_IB_STAGE_PRE_IB_REG_UMR, 1008 MLX5_IB_STAGE_WHITELIST_UID, 1009 MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 1010 MLX5_IB_STAGE_IB_REG, 1011 MLX5_IB_STAGE_DEVICE_NOTIFIER, 1012 MLX5_IB_STAGE_POST_IB_REG_UMR, 1013 MLX5_IB_STAGE_DELAY_DROP, 1014 MLX5_IB_STAGE_RESTRACK, 1015 MLX5_IB_STAGE_MAX, 1016 }; 1017 1018 struct mlx5_ib_stage { 1019 int (*init)(struct mlx5_ib_dev *dev); 1020 void (*cleanup)(struct mlx5_ib_dev *dev); 1021 }; 1022 1023 #define STAGE_CREATE(_stage, _init, _cleanup) \ 1024 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 1025 1026 struct mlx5_ib_profile { 1027 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 1028 }; 1029 1030 struct mlx5_ib_multiport_info { 1031 struct list_head list; 1032 struct mlx5_ib_dev *ibdev; 1033 struct mlx5_core_dev *mdev; 1034 struct notifier_block mdev_events; 1035 struct completion unref_comp; 1036 u64 sys_image_guid; 1037 u32 mdev_refcnt; 1038 bool is_master; 1039 bool unaffiliate; 1040 }; 1041 1042 struct mlx5_ib_flow_action { 1043 struct ib_flow_action ib_action; 1044 union { 1045 struct { 1046 u64 ib_flags; 1047 struct mlx5_accel_esp_xfrm *ctx; 1048 } esp_aes_gcm; 1049 struct { 1050 struct mlx5_ib_dev *dev; 1051 u32 sub_type; 1052 union { 1053 struct mlx5_modify_hdr *modify_hdr; 1054 struct mlx5_pkt_reformat *pkt_reformat; 1055 }; 1056 } flow_action_raw; 1057 }; 1058 }; 1059 1060 struct mlx5_dm { 1061 struct mlx5_core_dev *dev; 1062 /* This lock is used to protect the access to the shared 1063 * allocation map when concurrent requests by different 1064 * processes are handled. 1065 */ 1066 spinlock_t lock; 1067 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 1068 }; 1069 1070 struct mlx5_read_counters_attr { 1071 struct mlx5_fc *hw_cntrs_hndl; 1072 u64 *out; 1073 u32 flags; 1074 }; 1075 1076 enum mlx5_ib_counters_type { 1077 MLX5_IB_COUNTERS_FLOW, 1078 }; 1079 1080 struct mlx5_ib_mcounters { 1081 struct ib_counters ibcntrs; 1082 enum mlx5_ib_counters_type type; 1083 /* number of counters supported for this counters type */ 1084 u32 counters_num; 1085 struct mlx5_fc *hw_cntrs_hndl; 1086 /* read function for this counters type */ 1087 int (*read_counters)(struct ib_device *ibdev, 1088 struct mlx5_read_counters_attr *read_attr); 1089 /* max index set as part of create_flow */ 1090 u32 cntrs_max_index; 1091 /* number of counters data entries (<description,index> pair) */ 1092 u32 ncounters; 1093 /* counters data array for descriptions and indexes */ 1094 struct mlx5_ib_flow_counters_desc *counters_data; 1095 /* protects access to mcounters internal data */ 1096 struct mutex mcntrs_mutex; 1097 }; 1098 1099 static inline struct mlx5_ib_mcounters * 1100 to_mcounters(struct ib_counters *ibcntrs) 1101 { 1102 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1103 } 1104 1105 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1106 bool is_egress, 1107 struct mlx5_flow_act *action); 1108 struct mlx5_ib_lb_state { 1109 /* protect the user_td */ 1110 struct mutex mutex; 1111 u32 user_td; 1112 int qps; 1113 bool enabled; 1114 bool force_enable; 1115 }; 1116 1117 struct mlx5_ib_pf_eq { 1118 struct notifier_block irq_nb; 1119 struct mlx5_ib_dev *dev; 1120 struct mlx5_eq *core; 1121 struct work_struct work; 1122 spinlock_t lock; /* Pagefaults spinlock */ 1123 struct workqueue_struct *wq; 1124 mempool_t *pool; 1125 }; 1126 1127 struct mlx5_devx_event_table { 1128 struct mlx5_nb devx_nb; 1129 /* serialize updating the event_xa */ 1130 struct mutex event_xa_lock; 1131 struct xarray event_xa; 1132 }; 1133 1134 struct mlx5_var_table { 1135 /* serialize updating the bitmap */ 1136 struct mutex bitmap_lock; 1137 unsigned long *bitmap; 1138 u64 hw_start_addr; 1139 u32 stride_size; 1140 u64 num_var_hw_entries; 1141 }; 1142 1143 struct mlx5_port_caps { 1144 bool has_smi; 1145 u8 ext_port_cap; 1146 }; 1147 1148 1149 struct mlx5_special_mkeys { 1150 u32 dump_fill_mkey; 1151 __be32 null_mkey; 1152 __be32 terminate_scatter_list_mkey; 1153 }; 1154 1155 struct mlx5_macsec { 1156 struct mutex lock; /* Protects mlx5_macsec internal contexts */ 1157 struct list_head macsec_devices_list; 1158 struct notifier_block blocking_events_nb; 1159 }; 1160 1161 struct mlx5_ib_dev { 1162 struct ib_device ib_dev; 1163 struct mlx5_core_dev *mdev; 1164 struct mlx5_data_direct_dev *data_direct_dev; 1165 /* protect accessing data_direct_dev */ 1166 struct mutex data_direct_lock; 1167 struct notifier_block mdev_events; 1168 struct notifier_block sys_error_events; 1169 struct notifier_block lag_events; 1170 int num_ports; 1171 /* serialize update of capability mask 1172 */ 1173 struct mutex cap_mask_mutex; 1174 u8 ib_active:1; 1175 u8 is_rep:1; 1176 u8 lag_active:1; 1177 u8 fill_delay; 1178 struct umr_common umrc; 1179 /* sync used page count stats 1180 */ 1181 struct mlx5_ib_resources devr; 1182 1183 atomic_t mkey_var; 1184 struct mlx5_mkey_cache cache; 1185 struct timer_list delay_timer; 1186 /* Prevents soft lock on massive reg MRs */ 1187 struct mutex slow_path_mutex; 1188 struct ib_odp_caps odp_caps; 1189 u64 odp_max_size; 1190 struct mutex odp_eq_mutex; 1191 struct mlx5_ib_pf_eq odp_pf_eq; 1192 1193 struct xarray odp_mkeys; 1194 1195 struct mlx5_ib_flow_db *flow_db; 1196 /* protect resources needed as part of reset flow */ 1197 spinlock_t reset_flow_resource_lock; 1198 struct list_head qp_list; 1199 struct list_head data_direct_mr_list; 1200 /* Array with num_ports elements */ 1201 struct mlx5_ib_port *port; 1202 struct mlx5_sq_bfreg bfreg; 1203 struct mlx5_sq_bfreg fp_bfreg; 1204 struct mlx5_ib_delay_drop delay_drop; 1205 const struct mlx5_ib_profile *profile; 1206 1207 struct mlx5_ib_lb_state lb; 1208 u8 umr_fence; 1209 struct list_head ib_dev_list; 1210 u64 sys_image_guid; 1211 struct mlx5_dm dm; 1212 u16 devx_whitelist_uid; 1213 struct mlx5_srq_table srq_table; 1214 struct mlx5_qp_table qp_table; 1215 struct mlx5_async_ctx async_ctx; 1216 struct mlx5_devx_event_table devx_event_table; 1217 struct mlx5_var_table var_table; 1218 1219 struct xarray sig_mrs; 1220 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1221 u16 pkey_table_len; 1222 u8 lag_ports; 1223 struct mlx5_special_mkeys mkeys; 1224 struct mlx5_data_direct_resources ddr; 1225 1226 #ifdef CONFIG_MLX5_MACSEC 1227 struct mlx5_macsec macsec; 1228 #endif 1229 1230 u8 num_plane; 1231 struct mlx5_ib_dev *smi_dev; 1232 const char *sub_dev_name; 1233 }; 1234 1235 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1236 { 1237 return container_of(mcq, struct mlx5_ib_cq, mcq); 1238 } 1239 1240 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1241 { 1242 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1243 } 1244 1245 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1246 { 1247 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1248 } 1249 1250 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1251 { 1252 return to_mdev(mr->ibmr.device); 1253 } 1254 1255 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1256 { 1257 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1258 udata, struct mlx5_ib_ucontext, ibucontext); 1259 1260 return to_mdev(context->ibucontext.device); 1261 } 1262 1263 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1264 { 1265 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1266 } 1267 1268 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1269 { 1270 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1271 } 1272 1273 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1274 { 1275 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1276 } 1277 1278 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1279 { 1280 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1281 } 1282 1283 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1284 { 1285 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1286 } 1287 1288 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1289 { 1290 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1291 } 1292 1293 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1294 { 1295 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1296 } 1297 1298 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1299 { 1300 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1301 } 1302 1303 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1304 { 1305 return container_of(msrq, struct mlx5_ib_srq, msrq); 1306 } 1307 1308 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1309 { 1310 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1311 } 1312 1313 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1314 { 1315 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1316 } 1317 1318 static inline struct mlx5_ib_flow_action * 1319 to_mflow_act(struct ib_flow_action *ibact) 1320 { 1321 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1322 } 1323 1324 static inline struct mlx5_user_mmap_entry * 1325 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1326 { 1327 return container_of(rdma_entry, 1328 struct mlx5_user_mmap_entry, rdma_entry); 1329 } 1330 1331 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev); 1332 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev); 1333 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1334 struct mlx5_db *db); 1335 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1336 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1337 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1338 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1339 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1340 struct ib_udata *udata); 1341 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1342 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1343 { 1344 return 0; 1345 } 1346 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1347 struct ib_udata *udata); 1348 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1349 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1350 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1351 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1352 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1353 const struct ib_recv_wr **bad_wr); 1354 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1355 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1356 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1357 struct ib_udata *udata); 1358 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1359 int attr_mask, struct ib_udata *udata); 1360 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1361 struct ib_qp_init_attr *qp_init_attr); 1362 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1363 void mlx5_ib_drain_sq(struct ib_qp *qp); 1364 void mlx5_ib_drain_rq(struct ib_qp *qp); 1365 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1366 size_t buflen, size_t *bc); 1367 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1368 size_t buflen, size_t *bc); 1369 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1370 size_t buflen, size_t *bc); 1371 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1372 struct uverbs_attr_bundle *attrs); 1373 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1374 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1375 int mlx5_ib_pre_destroy_cq(struct ib_cq *cq); 1376 void mlx5_ib_post_destroy_cq(struct ib_cq *cq); 1377 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1378 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1379 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1380 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1381 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1382 u64 virt_addr, int access_flags, 1383 struct ib_dmah *dmah, 1384 struct ib_udata *udata); 1385 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1386 u64 length, u64 virt_addr, 1387 int fd, int access_flags, 1388 struct ib_dmah *dmah, 1389 struct uverbs_attr_bundle *attrs); 1390 int mlx5_ib_advise_mr(struct ib_pd *pd, 1391 enum ib_uverbs_advise_mr_advice advice, 1392 u32 flags, 1393 struct ib_sge *sg_list, 1394 u32 num_sge, 1395 struct uverbs_attr_bundle *attrs); 1396 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1397 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1398 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1399 int access_flags); 1400 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1401 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1402 u64 length, u64 virt_addr, int access_flags, 1403 struct ib_pd *pd, struct ib_udata *udata); 1404 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1405 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1406 u32 max_num_sg); 1407 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1408 u32 max_num_sg, 1409 u32 max_num_meta_sg); 1410 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1411 unsigned int *sg_offset); 1412 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1413 int data_sg_nents, unsigned int *data_sg_offset, 1414 struct scatterlist *meta_sg, int meta_sg_nents, 1415 unsigned int *meta_sg_offset); 1416 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1417 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1418 const struct ib_mad *in, struct ib_mad *out, 1419 size_t *out_mad_size, u16 *out_mad_pkey_index); 1420 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1421 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1422 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1423 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1424 __be64 *sys_image_guid); 1425 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1426 u16 *max_pkeys); 1427 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1428 u32 *vendor_id); 1429 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1430 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1431 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1432 u16 *pkey); 1433 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1434 union ib_gid *gid); 1435 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1436 struct ib_port_attr *props); 1437 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1438 struct ib_port_attr *props); 1439 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, 1440 u64 *speed); 1441 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1442 u64 access_flags); 1443 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1444 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1445 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1446 struct mlx5_cache_ent * 1447 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 1448 struct mlx5r_cache_rb_key rb_key, 1449 bool persistent_entry); 1450 1451 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1452 int access_flags, int access_mode, 1453 int ndescs); 1454 1455 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1456 struct ib_mr_status *mr_status); 1457 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1458 struct ib_wq_init_attr *init_attr, 1459 struct ib_udata *udata); 1460 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1461 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1462 u32 wq_attr_mask, struct ib_udata *udata); 1463 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1464 struct ib_rwq_ind_table_init_attr *init_attr, 1465 struct ib_udata *udata); 1466 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1467 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1468 struct ib_dm_mr_attr *attr, 1469 struct uverbs_attr_bundle *attrs); 1470 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 1471 struct mlx5_data_direct_dev *dev); 1472 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev); 1473 void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev); 1474 1475 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1476 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1477 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1478 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1479 int __init mlx5_ib_odp_init(void); 1480 void mlx5_ib_odp_cleanup(void); 1481 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1482 int mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1483 struct mlx5_ib_mr *mr, int flags); 1484 1485 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1486 enum ib_uverbs_advise_mr_advice advice, 1487 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1488 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1489 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1490 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1491 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1492 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1493 struct mlx5_ib_pf_eq *eq) 1494 { 1495 return 0; 1496 } 1497 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1498 static inline int mlx5_ib_odp_init(void) { return 0; } 1499 static inline void mlx5_ib_odp_cleanup(void) {} 1500 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1501 { 1502 return 0; 1503 } 1504 static inline int mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1505 struct mlx5_ib_mr *mr, int flags) 1506 { 1507 return -EOPNOTSUPP; 1508 } 1509 1510 static inline int 1511 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1512 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1513 struct ib_sge *sg_list, u32 num_sge) 1514 { 1515 return -EOPNOTSUPP; 1516 } 1517 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1518 { 1519 return -EOPNOTSUPP; 1520 } 1521 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1522 { 1523 return -EOPNOTSUPP; 1524 } 1525 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1526 1527 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1528 1529 /* Needed for rep profile */ 1530 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1531 const struct mlx5_ib_profile *profile, 1532 int stage); 1533 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1534 const struct mlx5_ib_profile *profile); 1535 1536 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1537 u32 port, struct ifla_vf_info *info); 1538 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1539 u32 port, int state); 1540 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1541 u32 port, struct ifla_vf_stats *stats); 1542 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1543 struct ifla_vf_guid *node_guid, 1544 struct ifla_vf_guid *port_guid); 1545 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1546 u64 guid, int type); 1547 1548 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1549 const struct ib_gid_attr *attr); 1550 1551 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1552 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1553 1554 /* GSI QP helper functions */ 1555 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1556 struct ib_qp_init_attr *attr); 1557 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1558 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1559 int attr_mask); 1560 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1561 int qp_attr_mask, 1562 struct ib_qp_init_attr *qp_init_attr); 1563 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1564 const struct ib_send_wr **bad_wr); 1565 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1566 const struct ib_recv_wr **bad_wr); 1567 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1568 1569 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1570 1571 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1572 int bfregn); 1573 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1574 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1575 u32 ib_port_num, 1576 u32 *native_port_num); 1577 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1578 u32 port_num); 1579 1580 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1581 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1582 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1583 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1584 extern const struct uapi_definition mlx5_ib_create_cq_defs[]; 1585 1586 static inline int is_qp1(enum ib_qp_type qp_type) 1587 { 1588 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1589 } 1590 1591 static inline u32 check_cq_create_flags(u32 flags) 1592 { 1593 /* 1594 * It returns non-zero value for unsupported CQ 1595 * create flags, otherwise it returns zero. 1596 */ 1597 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1598 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1599 } 1600 1601 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1602 u32 *user_index) 1603 { 1604 if (cqe_version) { 1605 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1606 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1607 return -EINVAL; 1608 *user_index = cmd_uidx; 1609 } else { 1610 *user_index = MLX5_IB_DEFAULT_UIDX; 1611 } 1612 1613 return 0; 1614 } 1615 1616 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1617 struct mlx5_ib_create_qp *ucmd, 1618 int inlen, 1619 u32 *user_index) 1620 { 1621 u8 cqe_version = ucontext->cqe_version; 1622 1623 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1624 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1625 return 0; 1626 1627 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1628 return -EINVAL; 1629 1630 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1631 } 1632 1633 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1634 struct mlx5_ib_create_srq *ucmd, 1635 int inlen, 1636 u32 *user_index) 1637 { 1638 u8 cqe_version = ucontext->cqe_version; 1639 1640 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1641 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1642 return 0; 1643 1644 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1645 return -EINVAL; 1646 1647 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1648 } 1649 1650 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1651 { 1652 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1653 MLX5_UARS_IN_PAGE : 1; 1654 } 1655 1656 extern void *xlt_emergency_page; 1657 1658 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1659 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1660 bool dyn_bfreg); 1661 1662 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1663 struct mlx5_ib_mkey *mmkey) 1664 { 1665 refcount_set(&mmkey->usecount, 1); 1666 1667 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1668 mmkey, GFP_KERNEL)); 1669 } 1670 1671 /* deref an mkey that can participate in ODP flow */ 1672 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1673 { 1674 if (refcount_dec_and_test(&mmkey->usecount)) 1675 wake_up(&mmkey->wait); 1676 } 1677 1678 /* deref an mkey that can participate in ODP flow and wait for relese */ 1679 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1680 { 1681 mlx5r_deref_odp_mkey(mmkey); 1682 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1683 } 1684 1685 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1686 { 1687 /* 1688 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1689 * is supported, it means that the driver no longer needs to assign the port 1690 * affinity by default. If a user wants to set the port affinity explicitly, 1691 * the user has a dedicated API to do that, so there is no need to assign 1692 * the port affinity by default. 1693 */ 1694 if (dev->lag_active && 1695 mlx5_lag_mode_is_hash(dev->mdev) && 1696 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1697 return 0; 1698 1699 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1700 return 0; 1701 1702 return dev->lag_active || 1703 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1704 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1705 } 1706 1707 static inline bool rt_supported(int ts_cap) 1708 { 1709 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1710 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1711 } 1712 1713 /* 1714 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1715 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1716 * root complexes. However if a switch is present in the path, then things get 1717 * really ugly depending on how the switch is setup. This table assumes that the 1718 * root complex is strict and is validating that all req/reps are matches 1719 * perfectly - so any scenario where it sees only half the transaction is a 1720 * failure. 1721 * 1722 * CR/RR/DT ATS RO P2P 1723 * 00X X X OK 1724 * 010 X X fails (request is routed to root but root never sees comp) 1725 * 011 0 X fails (request is routed to root but root never sees comp) 1726 * 011 1 X OK 1727 * 10X X 1 OK 1728 * 101 X 0 fails (completion is routed to root but root didn't see req) 1729 * 110 X 0 SLOW 1730 * 111 0 0 SLOW 1731 * 111 1 0 fails (completion is routed to root but root didn't see req) 1732 * 111 1 1 OK 1733 * 1734 * Unfortunately we cannot reliably know if a switch is present or what the 1735 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1736 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1737 * 1738 * For now assume if the umem is a dma_buf then it is P2P. 1739 */ 1740 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1741 struct ib_umem *umem, int access_flags) 1742 { 1743 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1744 return false; 1745 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1746 } 1747 1748 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 1749 unsigned int index, const union ib_gid *gid, 1750 const struct ib_gid_attr *attr); 1751 1752 static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) 1753 { 1754 return (port - 1) / dev->num_ports + 1; 1755 } 1756 1757 static inline unsigned int get_max_log_entity_size_cap(struct mlx5_ib_dev *dev, 1758 int access_mode) 1759 { 1760 int max_log_size = 0; 1761 1762 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT) 1763 max_log_size = 1764 MLX5_CAP_GEN_2(dev->mdev, max_mkey_log_entity_size_mtt); 1765 else if (access_mode == MLX5_MKC_ACCESS_MODE_KSM) 1766 max_log_size = MLX5_CAP_GEN_2( 1767 dev->mdev, max_mkey_log_entity_size_fixed_buffer); 1768 1769 if (!max_log_size || 1770 (max_log_size > 31 && 1771 !MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5))) 1772 max_log_size = 31; 1773 1774 return max_log_size; 1775 } 1776 1777 static inline unsigned int get_min_log_entity_size_cap(struct mlx5_ib_dev *dev, 1778 int access_mode) 1779 { 1780 int min_log_size = 0; 1781 1782 if (access_mode == MLX5_MKC_ACCESS_MODE_KSM && 1783 MLX5_CAP_GEN_2(dev->mdev, 1784 min_mkey_log_entity_size_fixed_buffer_valid)) 1785 min_log_size = MLX5_CAP_GEN_2( 1786 dev->mdev, min_mkey_log_entity_size_fixed_buffer); 1787 else 1788 min_log_size = 1789 MLX5_CAP_GEN_2(dev->mdev, log_min_mkey_entity_size); 1790 1791 min_log_size = max(min_log_size, MLX5_ADAPTER_PAGE_SHIFT); 1792 return min_log_size; 1793 } 1794 1795 /* 1796 * For mkc users, instead of a page_offset the command has a start_iova which 1797 * specifies both the page_offset and the on-the-wire IOVA 1798 */ 1799 static __always_inline unsigned long 1800 mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1801 u64 iova, int access_mode) 1802 { 1803 unsigned int max_log_entity_size_cap, min_log_entity_size_cap; 1804 unsigned long bitmap; 1805 1806 max_log_entity_size_cap = get_max_log_entity_size_cap(dev, access_mode); 1807 min_log_entity_size_cap = get_min_log_entity_size_cap(dev, access_mode); 1808 1809 bitmap = GENMASK_ULL(max_log_entity_size_cap, min_log_entity_size_cap); 1810 1811 /* In KSM mode HW requires IOVA and mkey's page size to be aligned */ 1812 if (access_mode == MLX5_MKC_ACCESS_MODE_KSM && iova) 1813 bitmap &= GENMASK_ULL(__ffs64(iova), 0); 1814 1815 return ib_umem_find_best_pgsz(umem, bitmap, iova); 1816 } 1817 1818 static inline unsigned long 1819 mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf, 1820 int access_mode) 1821 { 1822 return mlx5_umem_mkc_find_best_pgsz(to_mdev(umem_dmabuf->umem.ibdev), 1823 &umem_dmabuf->umem, 1824 umem_dmabuf->umem.iova, 1825 access_mode); 1826 } 1827 1828 #endif /* MLX5_IB_H */ 1829