Searched refs:min_clk_table (Results 1 – 6 of 6) sorted by relevance
15 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()251 l->mode_support_params.min_clk_table = ¶ms->dml->min_clk_table; in dml2_top_optimization_perform_optimization_phase()303 l->mode_support_params.min_clk_table = ¶ms->dml->min_clk_table; in dml2_top_optimization_perform_optimization_phase_1()789 l->mode_support_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_check_mode_supported()810 l->dppm_map_mode_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_check_mode_supported()844 l->mode_support_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_build_mode_programming()855 l->mode_support_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_build_mode_programming()982 l->dppm_map_mode_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_build_mode_programming()1138 mcg_build_min_clk_params.min_clk_table = &dml->min_clk_table; in dml2_top_soc15_initialize_instance()1145 core_init_params.minimum_clock_table = &dml->min_clk_table; in dml2_top_soc15_initialize_instance()[all …]
44 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; in get_minimum_clocks_for_latency()45 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()46 …*uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_… in get_minimum_clocks_for_latency()47 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in get_minimum_clocks_for_latency()68 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()73 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()77 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()116 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()120 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()149 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_svp_prefetch_minimums()[all …]
70 struct dml2_mcg_min_clock_table *min_clk_table; member86 struct dml2_mcg_min_clock_table *min_clk_table; member389 struct dml2_mcg_min_clock_table *min_clk_table; member993 struct dml2_mcg_min_clock_table min_clk_table; member
423 l->mode_support_ex_params.min_clk_table = in_out->min_clk_table; in core_dcn4_mode_support()559 l->mode_programming_ex_params.min_clk_table = in_out->instance->minimum_clock_table; in core_dcn4_mode_programming()
7952 const struct dml2_mcg_min_clock_table *min_clk_table = in_out_params->min_clk_table; in dml_core_mode_support() local7971 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml_core_mode_support()7972 …mode_lib->ms.FabricClock = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_in… in dml_core_mode_support()7973 mode_lib->ms.MaxDCFCLK = (double)min_clk_table->max_clocks_khz.dcfclk / 1000; in dml_core_mode_support()7974 mode_lib->ms.MaxFabricClock = (double)min_clk_table->max_clocks_khz.fclk / 1000; in dml_core_mode_support()7975 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; in dml_core_mode_support()7976 mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; in dml_core_mode_support()7977 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dppclk / 1000; in dml_core_mode_support()7978 …mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()7980 …mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_… in dml_core_mode_support()[all …]
12 return build_min_clock_table(in_out->soc_bb, in_out->min_clk_table); in mcg_dcn4_build_min_clock_table()