| /linux/Documentation/arch/powerpc/ |
| H A D | qe_firmware.rst | 44 In this document, the term 'microcode' refers to the sequence of 32-bit
45 integers that compose the actual QE microcode.
47 The term 'firmware' refers to a binary blob that contains the microcode as
50 1) describes the microcode's purpose
51 2) describes how and where to upload the microcode
60 The QE architecture allows for only one microcode present in I-RAM for each
61 RISC processor. To replace any current microcode, a full QE reset (which
62 disables the microcode) must be performed first.
64 QE microcode is uploaded using the following procedure:
66 1) The microcode is placed into I-RAM at a specific location, using the
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| /linux/Documentation/arch/x86/ |
| H A D | microcode.rst | 11 The kernel has a x86 microcode loading facility which is supposed to
12 provide microcode loading methods in the OS. Potential use cases are
13 updating the microcode on platforms beyond the OEM End-Of-Life support,
14 and updating the microcode on long-running systems without rebooting.
18 Early load microcode
21 The kernel can update microcode very early during boot. Loading
22 microcode early can fix CPU issues before they are observed during
25 The microcode is stored in an initrd file. During boot, it is read from
28 The format of the combined initrd image is microcode in (uncompressed)
32 The microcode files in cpio name space are:
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| H A D | mds.rst | 77 instruction in combination with a microcode update. The microcode clears
87 executed on a CPU without the microcode update there is no side effect
105 the microcode updated, but the hypervisor does not (yet) expose the
127 scenarios where the host has the updated microcode but the
207 functionality in microcode. Aside of that the IO-Port mechanism is a
209 not affected or do not receive microcode updates anymore.
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| H A D | index.rst | 35 microcode
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| /linux/arch/x86/kernel/cpu/microcode/ |
| H A D | Makefile | 2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o
5 microcode-$(CONFIG_CPU_SUP_AMD) += amd.o
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| H A D | core.c | 592 int old_rev = boot_cpu_data.microcode; in load_late_stop_cpus()
667 pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); in load_late_stop_cpus()
855 cpu_data(cpu).microcode = uci->cpu_sig.rev; in mc_cpu_online()
857 boot_cpu_data.microcode = uci->cpu_sig.rev; in mc_cpu_online()
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| H A D | intel.c | 798 cpu_data(cpu).microcode = uci->cpu_sig.rev; in apply_microcode_late()
800 boot_cpu_data.microcode = uci->cpu_sig.rev; in apply_microcode_late()
807 int cur_rev = boot_cpu_data.microcode; in ucode_validate_minrev()
921 c->microcode < 0x0b000021) { in is_blacklisted()
922 …rr_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); in is_blacklisted()
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| /linux/Documentation/power/ |
| H A D | suspend-and-cpuhotplug.rst | 176 There are some interesting situations involving CPU hotplug and microcode
179 [Please bear in mind that the kernel requests the microcode images from
187 to apply the same microcode revision to each of the CPUs.
190 and thereby in applying the correct microcode revision to it.
191 But note that the kernel does not maintain a common microcode image for the
197 In this case since we probably need to apply different microcode revisions
198 to different CPUs, the kernel maintains a copy of the correct microcode
208 (which is sent by the CPU hotplug code), the microcode update driver's
210 microcode image for that CPU.
213 doesn't have the microcode image, it does the CPU type/model discovery
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | gather_data_sampling.rst | 48 This issue is mitigated in microcode. The microcode defines the following new
62 GDS can also be mitigated on systems that don't have updated microcode by
76 use the microcode mitigation when available or disable AVX on affected systems
77 where the microcode hasn't been updated to include the mitigation.
91 Vulnerable: No microcode Processor vulnerable and microcode is missing
94 no microcode Processor is vulnerable and microcode is missing
108 The updated microcode will enable the mitigation by default. The kernel's
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| H A D | old_microcode.rst | 7 The kernel keeps a table of released microcode. Systems that had
8 microcode older than this at boot will say "Vulnerable". This means
12 You should update the CPU microcode to mitigate any exposure. This is
20 determined at boot. Runtime microcode updates do not change the status
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| H A D | reg-file-data-sampling.rst | 34 Intel released a microcode update that enables software to clear sensitive
38 unused and obsolete VERW instruction in combination with a microcode update.
39 The microcode clears the affected CPU buffers when the VERW instruction is
50 Newer processors and microcode update on existing affected processors added new
56 microcode that clears the affected buffers on VERW execution.
87 * - 'Vulnerable: No microcode'
88 - The processor is vulnerable but microcode is not updated.
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| H A D | tsx_async_abort.rst | 99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101 - The processor is vulnerable but microcode is not updated. The
104 If the processor is vulnerable but the availability of the microcode
110 microcode update applied, but the hypervisor is not yet updated to
111 expose the CPUID to the guest. If the host has updated microcode the
115 - The microcode has been updated to clear the buffers. TSX is still enabled.
124 The kernel detects the affected CPUs and the presence of the microcode which is
125 required. If a CPU is affected and the microcode is available, then the kernel
135 Affected systems where the host has TAA microcode and TAA is mitigated by
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| H A D | srso.rst | 36 First of all, it is required that the latest microcode be loaded for
53 * 'Vulnerable: No microcode':
55 The processor is vulnerable, no microcode extending IBPB
58 * 'Vulnerable: Safe RET, no microcode':
61 kernel, but the IBPB-extending microcode has not been applied. User
66 Extended IBPB functionality microcode patch has been applied. It does
83 (spec_rstack_overflow=microcode)
87 Combined microcode/software mitigation. It complements the
88 extended IBPB microcode patch functionality by addressing
152 microcode patch for one's system. This mitigation comes also at
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| H A D | special-register-buffer-data-sampling.rst | 64 Intel will release microcode updates that modify the RDRAND, RDSEED, and
86 The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
100 9]==1. This MSR is introduced through the microcode update.
132 Vulnerable: No microcode Processor vulnerable and microcode is missing
147 This new microcode serializes processor access during execution of RDRAND,
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| H A D | processor_mmio_stale_data.rst | 14 vulnerabilities includes a combination of microcode update and software
115 Newer processors and microcode update on existing affected processors added new
157 combination with a microcode update. The microcode clears the affected CPU
225 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
226 - The processor is vulnerable but microcode is not updated. The
229 If the processor is vulnerable but the availability of the microcode
235 microcode update applied, but the hypervisor is not yet updated to
236 expose the CPUID to the guest. If the host has updated microcode the
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| H A D | mds.rst | 104 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
105 - The processor is vulnerable but microcode is not updated. The
108 If the processor is vulnerable but the availability of the microcode
114 microcode update applied, but the hypervisor is not yet updated to
115 expose the CPUID to the guest. If the host has updated microcode the
135 The kernel detects the affected CPUs and the presence of the microcode
138 If a CPU is affected and the microcode is available, then the kernel
168 If the L1D flush mitigation is enabled and up to date microcode is
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| H A D | indirect-target-selection.rst | 22 executed prior to the IBPB. This is fixed by the IPU 2025.1 microcode, which
23 should be available via distro updates. Alternatively microcode can be
48 - IBPB isolation is affected on all ITS affected CPUs, and need a microcode
143 Note, microcode mitigation status is not reported in this file.
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| /linux/include/trace/events/ |
| H A D | mce.h | 45 __field( u32, microcode )
68 __entry->microcode = err->m.microcode;
88 __entry->microcode,
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| /linux/drivers/net/wireless/intel/iwlegacy/ |
| H A D | Kconfig | 22 In order to use this driver, you will need a microcode (uCode)
23 image for it. You can obtain the microcode from:
27 The microcode is typically installed in /lib/firmware. You can
49 In order to use this driver, you will need a microcode (uCode)
50 image for it. You can obtain the microcode from:
54 The microcode is typically installed in /lib/firmware. You can
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| /linux/drivers/crypto/cavium/cpt/ |
| H A D | cptpf.h | 22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS]; argument
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| H A D | cptpf_main.c | 122 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) in cpt_load_microcode()
160 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) in do_cpt_init()
257 struct microcode *mcode; in cpt_ucode_load_fw()
419 struct microcode *mcode = &cpt->mcode[grp]; in cpt_unload_microcode()
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| /linux/arch/x86/kernel/cpu/ |
| H A D | intel.c | 104 u32 microcode; member
144 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
207 c->microcode = intel_get_microcode_revision(); in early_init_intel()
234 c->microcode < 0x20e) { in early_init_intel()
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| H A D | proc.c | 85 if (c->microcode) in show_cpuinfo()
86 seq_printf(m, "microcode\t: 0x%x\n", c->microcode); in show_cpuinfo()
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| /linux/drivers/soc/fsl/qe/ |
| H A D | qe.c | 484 calc_size = struct_size(firmware, microcode, firmware->count); in qe_upload_firmware()
493 be32_to_cpu(firmware->microcode[i].count); in qe_upload_firmware()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware()
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| /linux/arch/x86/include/uapi/asm/ |
| H A D | mce.h | 38 __u32 microcode; /* Microcode revision */ member
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