Searched refs:me_hdr (Results 1 – 5 of 5) sorted by relevance
2758 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_me_cache_rs64() local2760 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_me_cache_rs64()2815 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_me_cache_rs64()2816 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_me_cache_rs64()2818 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_me_cache_rs64()2962 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v11_0_config_gfx_rs64() local2968 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v11_0_config_gfx_rs64()2999 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_gfx_rs64()3000 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_gfx_rs64()3002 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_gfx_rs64()[all …]
2112 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_config_gfx_rs64() local2118 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2149 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v12_0_config_gfx_rs64()2150 (me_hdr->ucode_start_addr_lo >> 2)); in gfx_v12_0_config_gfx_rs64()2152 me_hdr->ucode_start_addr_hi>>2); in gfx_v12_0_config_gfx_rs64()2500 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_cp_gfx_load_me_microcode_rs64() local2506 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2509 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2513 le32_to_cpu(me_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2514 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()[all …]
6260 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v10_0_cp_gfx_load_me_microcode() local6266 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v10_0_cp_gfx_load_me_microcode()6269 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v10_0_cp_gfx_load_me_microcode()6272 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_gfx_load_me_microcode()6273 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); in gfx_v10_0_cp_gfx_load_me_microcode()6275 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, in gfx_v10_0_cp_gfx_load_me_microcode()6325 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v10_0_cp_gfx_load_me_microcode()6327 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_me_microcode()
3898 const struct gfx_firmware_header_v1_0 *me_hdr = in cik_cp_gfx_load_microcode() local3905 radeon_ucode_print_gfx_hdr(&me_hdr->header); in cik_cp_gfx_load_microcode()3927 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in cik_cp_gfx_load_microcode()3928 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in cik_cp_gfx_load_microcode()3932 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()3933 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3470 const struct gfx_firmware_header_v1_0 *me_hdr = in si_cp_load_microcode() local3477 radeon_ucode_print_gfx_hdr(&me_hdr->header); in si_cp_load_microcode()3499 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()3500 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()