| /linux/sound/hda/core/ |
| H A D | intel-nhlt.c | 176 int mclk_mask = 0; in intel_nhlt_ssp_mclk_mask() local
223 mclk_mask |= blob[mdivc_offset] & GENMASK(1, 0); in intel_nhlt_ssp_mclk_mask()
232 if (hweight_long(mclk_mask) != 1) in intel_nhlt_ssp_mclk_mask()
235 return mclk_mask; in intel_nhlt_ssp_mclk_mask()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 809 uint32_t *mclk_mask, in vangogh_get_profiling_clk_mask() argument
816 if (mclk_mask) in vangogh_get_profiling_clk_mask()
817 *mclk_mask = clk_table->NumDfPstatesEnabled - 1; in vangogh_get_profiling_clk_mask()
825 if (mclk_mask) in vangogh_get_profiling_clk_mask()
826 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
840 if (mclk_mask) in vangogh_get_profiling_clk_mask()
841 *mclk_mask = 0; in vangogh_get_profiling_clk_mask()
900 uint32_t mclk_mask; in vangogh_get_dpm_ultimate_freq() local
944 &mclk_mask, in vangogh_get_dpm_ultimate_freq()
953 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in vangogh_get_dpm_ultimate_freq()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 246 uint32_t *mclk_mask, in renoir_get_profiling_clk_mask() argument
254 if (mclk_mask) in renoir_get_profiling_clk_mask()
256 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
262 if (mclk_mask) in renoir_get_profiling_clk_mask()
264 *mclk_mask = 0; in renoir_get_profiling_clk_mask()
279 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
313 &mclk_mask, in renoir_get_dpm_ultimate_freq()
330 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
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| /linux/sound/soc/sof/intel/ |
| H A D | hda.c | 1654 int mclk_mask = check_nhlt_ssp_mclk_mask(sdev, in hda_machine_select() local
1657 if (mclk_mask < 0) { in hda_machine_select()
1664 if (mclk_mask) { in hda_machine_select()
1666 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; in hda_machine_select()
1669 ssp_num, sdev->mclk_id_quirk, mclk_mask); in hda_machine_select()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 1728 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1736 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1743 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1750 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1753 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1783 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1800 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1804 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
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| H A D | vega20_hwmgr.c | 2534 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2542 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2549 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2556 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2559 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2734 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2753 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2757 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
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| H A D | smu7_hwmgr.c | 3168 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
3186 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3189 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
3225 *mclk_mask = 0; in smu7_get_profiling_clk()
3227 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
3239 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
3256 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
3260 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
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| H A D | vega10_hwmgr.c | 4219 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4229 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4235 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4245 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4337 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4354 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4358 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()
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