Searched refs:mbox1 (Results 1 – 8 of 8) sorted by relevance
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ |
| H A D | tu102.c | 46 tu102_gsp_booter_unload(struct nvkm_gsp *gsp, u32 mbox0, u32 mbox1) in tu102_gsp_booter_unload() argument
59 ret = nvkm_falcon_fw_boot(&gsp->booter.unload, &gsp->subdev, true, &mbox0, &mbox1, 0, 0); in tu102_gsp_booter_unload()
71 tu102_gsp_booter_load(struct nvkm_gsp *gsp, u32 mbox0, u32 mbox1) in tu102_gsp_booter_load() argument
73 return nvkm_falcon_fw_boot(&gsp->booter.load, &gsp->subdev, true, &mbox0, &mbox1, 0, 0); in tu102_gsp_booter_load()
166 u32 mbox0 = 0xff, mbox1 = 0xff; in tu102_gsp_fini() local
180 mbox1 = upper_32_bits(gsp->sr.meta.addr); in tu102_gsp_fini()
183 ret = tu102_gsp_booter_unload(gsp, mbox0, mbox1); in tu102_gsp_fini()
191 u32 mbox0, mbox1; in tu102_gsp_init() local
196 mbox1 = upper_32_bits(gsp->wpr_meta.addr); in tu102_gsp_init()
201 mbox1 = upper_32_bits(gsp->sr.meta.addr); in tu102_gsp_init()
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| H A D | gh100.c | 56 u32 mbox1 = nvkm_falcon_rd32(&gsp->falcon, NV_PFALCON_FALCON_MAILBOX1); in gh100_gsp_lockdown_released() local
59 if ((((u64)mbox1 << 32) | *mbox0) != gsp->fmc.args.addr) in gh100_gsp_lockdown_released()
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| /linux/drivers/gpu/nova-core/gsp/ |
| H A D | boot.rs | 168 let (mbox0, mbox1) = gsp_falcon.boot( in boot()
177 mbox1 in boot()
188 let (mbox0, mbox1) = sec2_falcon.boot( in boot()
197 mbox1 in boot()
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| /linux/drivers/gpu/drm/nouveau/nvkm/falcon/ |
| H A D | ga102.c | 113 ga102_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr) in ga102_flcn_fw_boot() argument
122 return gm200_flcn_fw_boot(fw, mbox0, mbox1, mbox0_ok, irqsclr); in ga102_flcn_fw_boot()
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| H A D | gm200.c | 221 u32 mbox0, mbox1; in gm200_flcn_fw_boot() local
238 mbox1 = nvkm_falcon_rd32(falcon, 0x044); in gm200_flcn_fw_boot()
239 if (FLCN_ERRON(falcon, ret || mbox0 != mbox0_ok, "mbox %08x %08x", mbox0, mbox1)) in gm200_flcn_fw_boot()
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| /linux/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| H A D | falcon.h | 101 u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr);
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-sriox-defs.h | 443 uint64_t mbox1:2; member
473 uint64_t mbox1:2;
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| /linux/Documentation/scsi/ |
| H A D | ChangeLog.sym53c8xx | 459 - Define some new IO registers for the 896 (istat1, mbox0, mbox1)
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