| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager.c | 128 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()
131 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()
150 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()
196 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
|
| H A D | kfd_mqd_manager_v12_1.c | 66 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask_v12_1()
91 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask_v12_1()
|
| H A D | kfd_topology.c | 1701 for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) { in fill_in_l2_l3_pcache()
1758 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()
1826 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()
2091 gfx_info->max_sh_per_se; in kfd_topology_add_device()
|
| H A D | kfd_crat.c | 2288 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
|
| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_kms.c | 457 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
459 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
|
| H A D | si.c | 3083 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3100 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3135 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3152 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3269 rdev->config.si.max_sh_per_se, in si_gpu_init()
3273 rdev->config.si.max_sh_per_se, in si_gpu_init()
3278 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
|
| H A D | cik.c | 3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
|
| H A D | radeon.h | 2124 unsigned max_sh_per_se; member
2155 unsigned max_sh_per_se; member
|
| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atomfirmware.h | 1797 uint8_t max_sh_per_se; member
1817 uint8_t max_sh_per_se; member
1842 uint8_t max_sh_per_se; member
1877 uint8_t max_sh_per_se; member
1918 uint8_t max_sh_per_se; member
|
| H A D | atombios.h | 5655 UCHAR max_sh_per_se; member
5668 UCHAR max_sh_per_se; member
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_debugfs.c | 130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
254 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
887 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
|
| H A D | gfx_v10_0.c | 5095 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
5107 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
5111 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
5112 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
5123 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5150 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
5284 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
10032 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
10121 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
10122 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
[all …]
|
| H A D | amdgpu_atombios.c | 747 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
|
| H A D | gfx_v9_4_2.c | 1876 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1909 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
|
| H A D | gfx_v12_0.c | 1706 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()
1748 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
1750 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
5726 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()
5727 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
|
| H A D | gfx_v11_0.c | 1998 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
2040 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
2042 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
7408 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
7492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7493 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
|
| H A D | amdgpu_discovery.c | 1665 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1709 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
|
| H A D | amdgpu_kms.c | 955 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
|
| H A D | amdgpu_device.c | 2547 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
4754 adev->gfx.config.max_sh_per_se, in amdgpu_device_init()
|
| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 2235 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
2264 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
|