Home
last modified time | relevance | path

Searched refs:mask_base (Results 1 – 25 of 78) sorted by relevance

1234

/linux/drivers/mfd/
H A Dsec-irq.c252 .mask_base = S2MPG10_COMMON_INT_MASK,
262 .mask_base = S2MPG10_PMIC_INT1M,
271 .mask_base = S2MPG11_COMMON_INT_MASK,
281 .mask_base = S2MPG11_PMIC_INT1M,
293 .mask_base = S2MPS11_REG_INT1M,
302 .mask_base = S2MPS14_REG_INT1M, \
326 .mask_base = S2MPU02_REG_INT1M,
336 .mask_base = S2MPU05_REG_INT1M,
346 .mask_base = S5M8767_REG_INT1M,
H A Dmax77541.c27 .mask_base = MAX77541_REG_INT_SRC_M,
45 .mask_base = MAX77541_REG_TOPSYS_INT_M,
61 .mask_base = MAX77541_REG_BUCK_INT_M,
77 .mask_base = MAX77541_REG_ADC_INT_M,
H A Dintel_soc_pmic_bxtwc.c154 .mask_base = BXTWC_MIRQLVL1,
164 .mask_base = BXTWC_MPWRBTNIRQ,
174 .mask_base = BXTWC_MTMUIRQ,
184 .mask_base = BXTWC_MBCUIRQ,
194 .mask_base = BXTWC_MADCIRQ,
204 .mask_base = BXTWC_MCHGR0IRQ,
214 .mask_base = BXTWC_MCRITIRQ,
H A Drk8xx-core.c594 .mask_base = RK801_INT_MASK0_REG,
605 .mask_base = RK805_INT_STS_MSK_REG,
616 .mask_base = RK806_INT_MSK0,
629 .mask_base = RK808_INT_STS_MSK_REG1,
641 .mask_base = RK816_INT_STS_MSK_REG1,
653 .mask_base = RK817_INT_STS_MSK_REG0,
665 .mask_base = RK818_INT_STS_MSK_REG1,
H A Dretu-mfd.c80 .mask_base = RETU_REG_IMR,
116 .mask_base = TAHVO_REG_IMR,
265 ret = retu_write(rdev, rdat->irq_chip->mask_base, 0xffff); in retu_probe()
H A Dmax8907.c131 .mask_base = MAX8907_REG_CHG_IRQ1_MASK,
155 .mask_base = MAX8907_REG_ON_OFF_IRQ1_MASK,
170 .mask_base = MAX8907_REG_RTC_IRQ_MASK,
H A Dmotorola-cpcap.c98 .mask_base = CPCAP_REG_MIM1,
107 .mask_base = CPCAP_REG_MIM2,
116 .mask_base = CPCAP_REG_INTM1,
H A Dmax77759.c267 .mask_base = MAX77759_PMIC_REG_INTSRCMASK,
283 .mask_base = MAX77759_MAXQ_REG_UIC_INT1_M,
293 .mask_base = MAX77759_PMIC_REG_TOPSYS_INT_MASK,
304 .mask_base = MAX77759_CHGR_REG_CHG_INT_MASK,
H A Dpf1550.c60 .mask_base = PF1550_PMIC_REG_SW_INT_MASK0,
95 .mask_base = PF1550_PMIC_REG_ONKEY_INT_MASK0,
124 .mask_base = PF1550_CHARG_REG_CHG_INT_MASK,
H A Dmax77693.c68 .mask_base = MAX77693_LED_REG_FLASH_INT_MASK,
83 .mask_base = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
100 .mask_base = MAX77693_CHG_REG_CHG_INT_MASK,
H A Dda9063-irq.c94 .mask_base = DA9063_REG_IRQ_MASK_A,
166 .mask_base = DA9063_REG_IRQ_MASK_A,
H A Dmax77686.c132 .mask_base = MAX77686_REG_INT1MSK,
141 .mask_base = MAX77802_REG_INT1MSK,
H A Dbd9571mwv.c99 .mask_base = BD9571MWV_INT_INTMASK,
165 .mask_base = BD9571MWV_INT_INTMASK,
H A Drohm-bd96801.c515 .mask_base = BD96801_REG_MASK_SYS_ERRB,
531 .mask_base = BD96801_REG_MASK_SYS_ERRB,
547 .mask_base = BD96801_REG_MASK_SYS_INTB,
562 .mask_base = BD96801_REG_MASK_SYS_INTB,
H A Dtps65910.c207 .mask_base = TPS65910_INT_MSK,
218 .mask_base = TPS65910_INT_MSK,
H A Dtps65912-core.c66 .mask_base = TPS65912_INT_MSK,
H A Dmax77714.c65 .mask_base = MAX77714_INT_TOPM,
H A Dtps65086.c51 .mask_base = TPS65086_IRQ_MASK,
H A Dintel_soc_pmic_chtdc_ti.c104 .mask_base = CHTDC_TI_MASK_IRQLVL1,
H A Drohm-bd9576.c84 .mask_base = BD957X_REG_INT_MAIN_MASK,
H A Dhi655x-pmic.c41 .mask_base = HI655X_IRQ_MASK_BASE,
/linux/drivers/pci/msi/
H A Dmsi.h26 return desc->pci.mask_base + desc->msi_index * PCI_MSIX_ENTRY_SIZE; in pci_msix_desc_addr()
48 readl(desc->pci.mask_base); in pci_msix_mask()
/linux/drivers/base/regmap/
H A Dregmap-irq.c122 if (d->chip->mask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
123 reg = d->get_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
689 if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted) in regmap_add_irq_chip_fwnode()
829 if (chip->mask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
830 reg = d->get_irq_reg(d, chip->mask_base, i); in regmap_add_irq_chip_fwnode()
/linux/drivers/gpio/
H A Dgpio-idio-16.c133 chip->mask_base = IDIO_16_ENABLE_IRQ; in devm_idio_16_regmap_register()
/linux/drivers/rtc/
H A Drtc-max77686.c180 .mask_base = MAX77686_RTC_INTM,
206 .mask_base = MAX77686_RTC_INTM,
275 .mask_base = MAX77802_RTC_INTM,

1234