Home
last modified time | relevance | path

Searched refs:mask2 (Results 1 – 25 of 70) sorted by relevance

123

/linux/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c100 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
106 mask2 = create_cpumask(); in create_cpumask_set()
107 if (!mask2) { in create_cpumask_set()
116 bpf_cpumask_release(mask2); in create_cpumask_set()
124 bpf_cpumask_release(mask2); in create_cpumask_set()
131 *out2 = mask2; in create_cpumask_set()
254 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
264 mask2 = create_cpumask(); in BPF_PROG()
265 if (!mask2) in BPF_PROG()
269 bpf_cpumask_set_cpu(1, mask2); in BPF_PROG()
[all …]
/linux/drivers/ras/amd/atl/
H A Dsystem.c67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df3p5_get_masks_shifts() argument
75 df_cfg.socket_id_mask = FIELD_GET(DF4_SOCKET_ID_MASK, mask2); in df3p5_get_masks_shifts()
76 df_cfg.die_id_mask = FIELD_GET(DF4_DIE_ID_MASK, mask2); in df3p5_get_masks_shifts()
79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df4_get_masks_shifts() argument
81 df3p5_get_masks_shifts(mask0, mask1, mask2); in df4_get_masks_shifts()
96 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
107 if (df_indirect_read_broadcast(0, 4, 0x1B8, &mask2)) in df4_get_fabric_id_mask_registers()
110 df4_get_masks_shifts(mask0, mask1, mask2); in df4_get_fabric_id_mask_registers()
/linux/drivers/soc/fsl/qe/
H A Dgpio.c241 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
248 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
249 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
250 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
251 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
253 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
254 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
255 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
256 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/linux/fs/orangefs/
H A Dorangefs-debugfs.c107 __u64 mask2; member
497 c_mask.mask2); in orangefs_debug_write()
584 (unsigned long long *)&(cdm_array[i].mask2)); in orangefs_prepare_cdm_array()
796 (mask->mask2 & cdm_array[index].mask2)) { in do_c_string()
840 (c_mask->mask2 == cdm_array[client_all_index].mask2)) { in check_amalgam_keyword()
847 (c_mask->mask2 == cdm_array[client_verbose_index].mask2)) { in check_amalgam_keyword()
916 (**sane_mask).mask2 = (**sane_mask).mask2 | cdm_array[i].mask2; in do_c_mask()
941 client_debug_mask.mask2 = mask2_info.mask2_value; in orangefs_debugfs_new_client_mask()
947 (unsigned long long)client_debug_mask.mask2); in orangefs_debugfs_new_client_mask()
/linux/sound/pci/ice1712/
H A Dwm8776.c136 .mask2 = WM8776_DACVOL_MASK,
146 .mask2 = WM8776_DAC_PL_RR,
162 .mask2 = WM8776_HPVOL_MASK,
180 .mask2 = WM8776_VOL_HPZCEN,
207 .mask2 = WM8776_PHASE_INVERTR,
223 .mask2 = WM8776_ADC_GAIN_MASK,
233 .mask2 = WM8776_ADC_MUTER,
488 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8776_ctl_get()
489 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8776_ctl_get()
528 val &= ~wm->ctl[n].mask2; in snd_wm8776_ctl_put()
[all …]
H A Dwm8766.c37 .mask2 = WM8766_VOL_MASK,
48 .mask2 = WM8766_VOL_MASK,
59 .mask2 = WM8766_VOL_MASK,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
219 val2 >>= __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_get()
258 val &= ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
259 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
266 val |= regval2 << __ffs(wm->ctl[n].mask2); in snd_wm8766_ctl_put()
/linux/include/linux/
H A Dcpumask.h406 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
407 for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
424 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
425 for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
441 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
442 for_each_or_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
489 const struct cpumask *mask2, in cpumask_any_and_but() argument
498 i = cpumask_first_and(mask1, mask2); in cpumask_any_and_but()
502 return cpumask_next_and(cpu, mask1, mask2); in cpumask_any_and_but()
516 const struct cpumask *mask2, in cpumask_any_andnot_but() argument
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
118 mask2 = sgint->vmeistat & sgint->cmeimask0; in indy_local0_irqdispatch()
119 irq = lc2msk_to_irqnr[mask2]; in indy_local0_irqdispatch()
136 u8 mask2; in indy_local1_irqdispatch() local
140 mask2 = sgint->vmeistat & sgint->cmeimask1; in indy_local1_irqdispatch()
141 irq = lc3msk_to_irqnr[mask2]; in indy_local1_irqdispatch()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c287 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2() argument
291 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
297 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3() argument
302 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
309 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4() argument
315 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
323 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5() argument
330 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
339 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6() argument
347 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get6()
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
H A Dar9003_mac.c187 u32 mask2 = 0; in ar9003_hw_get_isr() local
217 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
219 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
221 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
223 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
225 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
227 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
229 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
231 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
303 *masked |= mask2; in ar9003_hw_get_isr()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
217 reg2 ## __ ## mask2 ## _MASK,\
219 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
207 reg2 ## __ ## mask2 ## _MASK,\
209 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
205 reg2 ## __ ## mask2 ## _MASK,\
207 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
210 reg2 ## __ ## mask2 ## _MASK,\
212 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
206 reg2 ## __ ## mask2 ## _MASK,\
208 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
212 reg2 ## __ ## mask2 ## _MASK,\
214 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
H A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
182 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
196 reg2 ## __ ## mask2 ## _MASK,\
198 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
202 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
216 reg2 ## __ ## mask2 ## _MASK,\
218 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
169 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
171 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
183 reg2 ## __ ## mask2 ## _MASK,\
185 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/
H A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
168 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
170 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
182 reg2 ## __ ## mask2 ## _MASK,\
184 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
190 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
192 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
204 reg2 ## __ ## mask2 ## _MASK,\
206 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/net/hamradio/
H A Dbaycom_par.c206 unsigned int data, mask, mask2, descx; in par96_rx() local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; in par96_rx()
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2) in par96_rx()
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; in par96_rx()
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) && in par96_rx()
/linux/arch/alpha/kernel/
H A Dsys_titan.c69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
75 mask2 = mask & titan_cpu_irq_affinity[2]; in titan_update_irq_hw()
80 else if (bcpu == 2) mask2 |= isa_enable; in titan_update_irq_hw()
94 *dim2 = mask2; in titan_update_irq_hw()
/linux/drivers/media/test-drivers/vidtv/
H A Dvidtv_pes.c90 u64 mask2; in vidtv_pes_write_pts_dts() local
97 mask2 = GENMASK_ULL(29, 15); in vidtv_pes_write_pts_dts()
103 pts_dts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
107 pts_dts.dts2 = cpu_to_be16(((args->dts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
115 pts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()

123