| /linux/drivers/firmware/xilinx/ |
| H A D | zynqmp-crypto.c | 29 lower_32_bits(address)); in zynqmp_pm_aes_engine()
54 u32 lower_addr = lower_32_bits(address); in zynqmp_pm_sha_hash()
109 lower_32_bits(keyaddr), in versal_pm_aes_key_write()
140 lower_32_bits(hw_req), in versal_pm_aes_op_init()
157 lower_32_bits(aad_addr), in versal_pm_aes_update_aad()
174 lower_32_bits(in_params), in versal_pm_aes_enc_update()
176 lower_32_bits(in_addr), in versal_pm_aes_enc_update()
190 lower_32_bits(gcm_addr), in versal_pm_aes_enc_final()
206 lower_32_bits(in_params), in versal_pm_aes_dec_update()
208 lower_32_bits(in_addr), in versal_pm_aes_dec_update()
[all …]
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| /linux/drivers/firmware/smccc/ |
| H A D | kvm_guest.c | 30 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
31 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
32 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
33 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
71 ver = lower_32_bits(res.a1); in kvm_arm_target_impl_cpu_init()
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| /linux/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil.c | 151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
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| /linux/drivers/tee/tstee/ |
| H A D | core.c | 37 args[0] = lower_32_bits(data->data0); in arg_list_from_ffa_data()
38 args[1] = lower_32_bits(data->data1); in arg_list_from_ffa_data()
39 args[2] = lower_32_bits(data->data2); in arg_list_from_ffa_data()
40 args[3] = lower_32_bits(data->data3); in arg_list_from_ffa_data()
41 args[4] = lower_32_bits(data->data4); in arg_list_from_ffa_data()
190 shm_id = lower_32_bits(param[0].u.value.a); in tstee_invoke_func()
191 req_len = lower_32_bits(param[0].u.value.b); in tstee_invoke_func()
212 ffa_args[TS_RPC_SERVICE_MEM_HANDLE_LSW] = lower_32_bits(handle); in tstee_invoke_func()
281 lower_32_bits(shm->sec_world_id); in tstee_shm_register()
319 lower_32_bits(shm->sec_world_id); in tstee_shm_unregister()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v6_0.c | 151 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
217 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
235 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
281 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
289 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
365 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
367 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
376 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
[all …]
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| H A D | sdma_v5_2.c | 149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
222 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
236 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
245 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
249 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
294 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
299 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
302 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
382 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
384 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
[all …]
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| H A D | sdma_v5_0.c | 309 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
382 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
395 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
400 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
446 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
451 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
454 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
532 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
534 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
543 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
[all …]
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| H A D | sdma_v2_4.c | 255 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
313 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
315 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
321 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
447 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
554 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
609 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
663 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v2_4_vm_copy_pte()
665 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v2_4_vm_copy_pte()
[all …]
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| H A D | vcn_v2_5.c | 609 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
620 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
628 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
636 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v2_5_mc_resume()
675 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
696 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
716 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
728 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1130 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1141 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
[all …]
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| H A D | sdma_v3_0.c | 431 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v3_0_ring_emit_ib()
436 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
489 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
491 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
497 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
688 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
710 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
828 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
883 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib()
936 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v3_0_vm_copy_pte()
[all …]
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| H A D | cik_sdma.c | 231 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); in cik_sdma_ring_emit_ib()
284 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
286 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
292 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
622 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
677 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
727 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pte()
729 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pte()
752 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_write_pte()
756 ib->ptr[ib->length_dw++] = lower_32_bits(value); in cik_sdma_vm_write_pte()
[all …]
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager_vi.c | 117 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
131 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
133 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
143 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
185 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
188 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
190 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
216 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
371 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
373 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| H A D | kfd_mqd_manager_v12.c | 127 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
151 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
196 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
198 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
219 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
335 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
337 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
339 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
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| H A D | kfd_mqd_manager_v12_1.c | 183 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
207 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
250 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
262 lower_32_bits((q->queue_address + q->queue_size) >> 8); in update_mqd()
274 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
276 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
297 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
410 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
412 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
414 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
[all …]
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| H A D | kfd_mqd_manager_v11.c | 148 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
176 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
218 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
221 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
223 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
244 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
422 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
424 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
426 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
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| H A D | kfd_mqd_manager_v10.c | 115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
136 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
179 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
182 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
184 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
205 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
377 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
379 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| H A D | kfd_mqd_manager_cik.c | 117 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
193 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
195 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
237 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
239 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
353 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
355 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
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| /linux/drivers/iio/test/ |
| H A D | iio-test-format.c | 211 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
217 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
223 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
229 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
235 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
241 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
247 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | gm20b.c | 73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
95 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
99 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
101 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | gv100.c | 47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); in gv100_chan_ramfc_write()
51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in gv100_chan_ramfc_write()
101 nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr)); in gv100_ectx_bind()
121 nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2)); in gv100_ectx_ce_bind()
187 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); in gv100_runl_insert_chan()
189 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); in gv100_runl_insert_chan()
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| /linux/drivers/pci/controller/ |
| H A D | pci-xgene.c | 288 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
292 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
385 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
387 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
389 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
397 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
446 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
449 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
512 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
518 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
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| /linux/drivers/media/pci/pt3/ |
| H A D | pt3_dma.c | 52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gm20b.c | 41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
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| /linux/drivers/accel/habanalabs/common/ |
| H A D | memory_mgr.c | 25 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_get()
67 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_release()
86 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_remove_idr_locked()
118 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_put_handle()
185 idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_alloc()
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| /linux/arch/x86/include/asm/ |
| H A D | mshyperv.h | 79 u32 input_address_lo = lower_32_bits(input_address); in hv_do_hypercall()
81 u32 output_address_lo = lower_32_bits(output_address); in hv_do_hypercall()
106 u32 input1_lo = lower_32_bits(input1); in _hv_do_fast_hypercall8()
135 u32 input1_lo = lower_32_bits(input1); in _hv_do_fast_hypercall16()
137 u32 input2_lo = lower_32_bits(input2); in _hv_do_fast_hypercall16()
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