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Searched refs:lcdc (Results 1 – 25 of 56) sorted by relevance

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/linux/drivers/video/fbdev/omap/
H A Dlcdc.c71 } lcdc; variable
75 lcdc.irq_mask |= mask; in enable_irqs()
80 lcdc.irq_mask &= ~mask; in disable_irqs()
111 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */ in enable_controller()
133 init_completion(&lcdc.last_frame_complete); in disable_controller()
135 if (!wait_for_completion_timeout(&lcdc.last_frame_complete, in disable_controller()
137 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n"); in disable_controller()
148 dev_err(lcdc.fbdev->dev, in reset_controller()
157 dev_err(lcdc.fbdev->dev, in reset_controller()
175 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par; in setup_lcd_dma()
[all …]
H A DMakefile13 objs-yy := omapfb_main.o lcdc.o
/linux/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c145 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); in imx_lcdc_update_hw_registers() local
152 writel(addr, lcdc->base + IMX21LCDC_LSSAR); in imx_lcdc_update_hw_registers()
159 clk_disable_unprepare(lcdc->clk_per); in imx_lcdc_update_hw_registers()
164 writel(framesize, lcdc->base + IMX21LCDC_LSR); in imx_lcdc_update_hw_registers()
170 writel(lhcr, lcdc->base + IMX21LCDC_LHCR); in imx_lcdc_update_hw_registers()
176 writel(lvcr, lcdc->base + IMX21LCDC_LVCR); in imx_lcdc_update_hw_registers()
178 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
181 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); in imx_lcdc_update_hw_registers()
184 writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR); in imx_lcdc_update_hw_registers()
188 clk_prepare_enable(lcdc->clk_per); in imx_lcdc_update_hw_registers()
[all …]
H A DMakefile1 obj-$(CONFIG_DRM_IMX_LCDC) += imx-lcdc.o
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-msm8660.c752 MSM_PIN_FUNCTION(lcdc),
773 PINGROUP(0, lcdc, dsub, _, _, _, _, _),
774 PINGROUP(1, lcdc, dsub, _, _, _, _, _),
775 PINGROUP(2, lcdc, dsub, _, _, _, _, _),
776 PINGROUP(3, lcdc, dsub, _, _, _, _, _),
777 PINGROUP(4, lcdc, dsub, _, _, _, _, _),
778 PINGROUP(5, lcdc, dsub, _, _, _, _, _),
779 PINGROUP(6, lcdc, dsub, _, _, _, _, _),
780 PINGROUP(7, lcdc, dsub, _, _, _, _, _),
781 PINGROUP(8, lcdc, dsub, _, _, _, _, _),
[all …]
/linux/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.c290 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_write_chan()
292 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan()
299 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + in lcdc_write_chan_mirror()
306 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); in lcdc_read_chan()
312 iowrite32(data, ovl->channel->lcdc->base + reg); in lcdc_write_overlay()
313 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); in lcdc_write_overlay()
400 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); in lcdc_sys_write_index()
401 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
402 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | in lcdc_sys_write_index()
404 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
[all …]
H A Dsh_mobile_lcdcfb.h44 struct sh_mobile_lcdc_chan *lcdc; member
57 struct sh_mobile_lcdc_priv *lcdc; member
/linux/Documentation/devicetree/bindings/display/
H A Dmarvell,pxa2xx-lcdc.txt6 "marvell,pxa2xx-lcdc",
7 "marvell,pxa270-lcdc",
8 "marvell,pxa300-lcdc"
25 compatible = "marvell,pxa2xx-lcdc";
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi154 lcdc: lcd-controller@40500000 { label
155 compatible = "marvell,pxa2xx-lcdc";
H A Dpxa300-raumfeld-controller.dts149 &lcdc {
258 lcdc_pins: lcdc-pins {
/linux/drivers/gpu/drm/imx/
H A DMakefile6 obj-$(CONFIG_DRM_IMX_LCDC) += lcdc/
H A DKconfig6 source "drivers/gpu/drm/imx/lcdc/Kconfig"
/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dtilcdc.txt41 tfp410 DVI encoder or lcd panel to lcdc
58 ti,hwmods = "lcdc";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts34 &lcdc {
H A Dimx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts34 &lcdc {
H A Dimx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts53 &lcdc {
H A Dimx6sx-udoo-neo.dtsi205 remote-endpoint = <&lcdc>;
225 lcdc: endpoint { label
H A Dimx25.dtsi481 lcdc: lcdc@53fbc000 { label
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-myirtech-myd.dts178 &lcdc {
409 lcdc_pins_default: lcdc-default-pins {
434 lcdc_pins_sleep: lcdc-sleep-pins {
H A Dam335x-boneblack-hdmi.dtsi53 &lcdc {
H A Dam335x-sbc-t335.dts174 &lcdc {
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi2152 lcdc {
2153 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2158 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2163 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2168 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2173 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2201 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2223 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2243 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2264 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi1089 lcdc {
1090 lcdc_dclk: lcdc-dclk {
1094 lcdc_den: lcdc-den {
1098 lcdc_hsync: lcdc-hsync {
1102 lcdc_vsync: lcdc-vsync {
1106 lcdc_rgb24: lcdc-rgb24 {
/linux/drivers/clk/davinci/
H A Dpsc-da850.c114 LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
/linux/Documentation/fb/
H A Dsh7760fb.rst126 .name = "sh7760-lcdc",

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