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/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_ui_layer.c29 static void sun8i_ui_layer_disable(struct sun8i_layer *layer) in sun8i_ui_layer_disable() argument
31 u32 ch_base = sun8i_channel_base(layer); in sun8i_ui_layer_disable()
33 regmap_write(layer->regs, in sun8i_ui_layer_disable()
34 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), 0); in sun8i_ui_layer_disable()
37 static void sun8i_ui_layer_update_attributes(struct sun8i_layer *layer, in sun8i_ui_layer_update_attributes() argument
44 ch_base = sun8i_channel_base(layer); in sun8i_ui_layer_update_attributes()
55 regmap_write(layer->regs, in sun8i_ui_layer_update_attributes()
56 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), val); in sun8i_ui_layer_update_attributes()
59 static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer, in sun8i_ui_layer_update_coord() argument
69 layer->channel, layer->overlay); in sun8i_ui_layer_update_coord()
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H A Dsun8i_vi_layer.c23 static void sun8i_vi_layer_disable(struct sun8i_layer *layer) in sun8i_vi_layer_disable() argument
25 u32 ch_base = sun8i_channel_base(layer); in sun8i_vi_layer_disable()
27 regmap_write(layer->regs, in sun8i_vi_layer_disable()
28 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), 0); in sun8i_vi_layer_disable()
31 static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer, in sun8i_vi_layer_update_attributes() argument
38 ch_base = sun8i_channel_base(layer); in sun8i_vi_layer_update_attributes()
46 if (layer->cfg->de_type >= SUN8I_MIXER_DE3) { in sun8i_vi_layer_update_attributes()
53 regmap_write(layer->regs, in sun8i_vi_layer_update_attributes()
54 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val); in sun8i_vi_layer_update_attributes()
56 if (layer->cfg->de2_fcc_alpha) { in sun8i_vi_layer_update_attributes()
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H A Dsun4i_layer.c69 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_disable() local
70 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_disable()
72 sun4i_backend_layer_enable(backend, layer->id, false); in sun4i_backend_layer_atomic_disable()
89 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_update() local
90 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_update()
93 sun4i_backend_cleanup_layer(backend, layer->id); in sun4i_backend_layer_atomic_update()
101 sun4i_backend_update_layer_frontend(backend, layer->id, in sun4i_backend_layer_atomic_update()
105 sun4i_backend_update_layer_formats(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
106 sun4i_backend_update_layer_buffer(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
109 sun4i_backend_update_layer_coord(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
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H A Dsun8i_vi_scaler.c836 static u32 sun8i_vi_scaler_base(struct sun8i_layer *layer) in sun8i_vi_scaler_base() argument
838 if (layer->cfg->de_type == SUN8I_MIXER_DE33) in sun8i_vi_scaler_base()
840 DE33_CH_SIZE * layer->channel; in sun8i_vi_scaler_base()
841 else if (layer->cfg->de_type == SUN8I_MIXER_DE3) in sun8i_vi_scaler_base()
843 DE3_VI_SCALER_UNIT_SIZE * layer->channel; in sun8i_vi_scaler_base()
846 DE2_VI_SCALER_UNIT_SIZE * layer->channel; in sun8i_vi_scaler_base()
913 void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable) in sun8i_vi_scaler_enable() argument
917 base = sun8i_vi_scaler_base(layer); in sun8i_vi_scaler_enable()
925 regmap_write(layer->regs, in sun8i_vi_scaler_enable()
929 void sun8i_vi_scaler_setup(struct sun8i_layer *layer, in sun8i_vi_scaler_setup() argument
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H A Dsun8i_ui_scaler.c92 static u32 sun8i_ui_scaler_base(struct sun8i_layer *layer) in sun8i_ui_scaler_base() argument
94 int offset = layer->cfg->vi_scaler_num; in sun8i_ui_scaler_base()
96 if (layer->cfg->de_type == SUN8I_MIXER_DE3) in sun8i_ui_scaler_base()
99 DE3_UI_SCALER_UNIT_SIZE * (layer->channel - offset); in sun8i_ui_scaler_base()
103 DE2_UI_SCALER_UNIT_SIZE * (layer->channel - offset); in sun8i_ui_scaler_base()
130 void sun8i_ui_scaler_enable(struct sun8i_layer *layer, bool enable) in sun8i_ui_scaler_enable() argument
134 base = sun8i_ui_scaler_base(layer); in sun8i_ui_scaler_enable()
142 regmap_write(layer->regs, SUN8I_SCALER_GSU_CTRL(base), val); in sun8i_ui_scaler_enable()
145 void sun8i_ui_scaler_setup(struct sun8i_layer *layer, in sun8i_ui_scaler_setup() argument
153 base = sun8i_ui_scaler_base(layer); in sun8i_ui_scaler_setup()
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H A Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
18 ((base) + 0x20 * (layer) + 0x0)
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
20 ((base) + 0x20 * (layer) + 0x4)
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
22 ((base) + 0x20 * (layer) + 0x8)
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
24 ((base) + 0x20 * (layer) + 0xc)
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
26 ((base) + 0x20 * (layer) + 0x10)
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H A Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
12 ((base) + 0x30 * (layer) + 0x0)
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
14 ((base) + 0x30 * (layer) + 0x4)
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
16 ((base) + 0x30 * (layer) + 0x8)
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
20 ((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
H A Dsun8i_csc.c160 static void sun8i_de3_ccsc_setup(struct regmap *map, int layer, in sun8i_de3_ccsc_setup() argument
169 mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); in sun8i_de3_ccsc_setup()
178 addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); in sun8i_de3_ccsc_setup()
186 layer, in sun8i_de3_ccsc_setup()
190 layer, in sun8i_de3_ccsc_setup()
194 layer, i); in sun8i_de3_ccsc_setup()
230 void sun8i_csc_config(struct sun8i_layer *layer, in sun8i_csc_config() argument
236 if (layer->cfg->de_type == SUN8I_MIXER_DE3) { in sun8i_csc_config()
237 sun8i_de3_ccsc_setup(layer->regs, layer->channel, in sun8i_csc_config()
243 base = ccsc_base[layer->cfg->ccsc][layer->channel]; in sun8i_csc_config()
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c413 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_is_video() argument
415 return layer->id == ZYNQMP_DPSUB_LAYER_VID; in zynqmp_disp_layer_is_video()
427 struct zynqmp_disp_layer *layer, in zynqmp_disp_avbuf_set_format() argument
433 layer->disp_fmt = fmt; in zynqmp_disp_avbuf_set_format()
434 if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { in zynqmp_disp_avbuf_set_format()
437 val &= zynqmp_disp_layer_is_video(layer) in zynqmp_disp_avbuf_set_format()
443 reg = zynqmp_disp_layer_is_video(layer) in zynqmp_disp_avbuf_set_format()
451 reg = zynqmp_disp_layer_is_video(layer) in zynqmp_disp_avbuf_set_format()
572 struct zynqmp_disp_layer *layer) in zynqmp_disp_avbuf_enable_video() argument
577 if (zynqmp_disp_layer_is_video(layer)) { in zynqmp_disp_avbuf_enable_video()
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H A Dzynqmp_disp.h53 u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
55 u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,
57 void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer);
58 void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
59 void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
61 void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,
63 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_qos.c84 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
88 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
92 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
96 HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_set_leak_time()
99 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
103 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
107 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
117 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_last() argument
121 itr = sparx5_lg_get_first(sparx5, layer, group); in sparx5_lg_get_last()
124 next = sparx5_lg_get_next(sparx5, layer, group, itr); in sparx5_lg_get_last()
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/linux/drivers/media/dvb-frontends/
H A Dmb86a20s.c377 unsigned layer) in mb86a20s_get_modulation() argument
386 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_modulation()
388 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_modulation()
409 unsigned layer) in mb86a20s_get_fec() argument
419 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_fec()
421 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_fec()
444 unsigned layer) in mb86a20s_get_interleaving() argument
457 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_interleaving()
459 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_interleaving()
470 unsigned layer) in mb86a20s_get_segment_count() argument
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/linux/drivers/gpu/drm/logicvc/
H A Dlogicvc_layer.c87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
111 ret = logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_check()
123 layer->index != (logicvc->config.layers_count - 1) && in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_update() local
149 u32 index = layer->index; in logicvc_plane_atomic_update()
167 logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_update()
191 if (layer->config.alpha_mode == LOGICVC_LAYER_ALPHA_LAYER) { in logicvc_plane_atomic_update()
196 switch (layer->config.depth) { in logicvc_plane_atomic_update()
201 if (layer->config.colorspace == in logicvc_plane_atomic_update()
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_disable() local
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/linux/net/caif/
H A Dcaif_dev.c35 struct cflayer layer; member
161 caifd->layer.up-> in caif_flow_cb()
162 ctrlcmd(caifd->layer.up, in caif_flow_cb()
164 caifd->layer.id); in caif_flow_cb()
168 static int transmit(struct cflayer *layer, struct cfpkt *pkt) in transmit() argument
172 container_of(layer, struct caif_device_entry, layer); in transmit()
230 caifd->layer.up->ctrlcmd(caifd->layer.up, in transmit()
232 caifd->layer.id); in transmit()
259 if (!caifd || !caifd->layer.up || !caifd->layer.up->receive || in receive()
270 err = caifd->layer.up->receive(caifd->layer.up, pkt); in receive()
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H A Dcfserl.c22 struct cflayer layer; member
34 void cfserl_release(struct cflayer *layer) in cfserl_release() argument
36 kfree(layer); in cfserl_release()
44 caif_assert(offsetof(struct cfserl, layer) == 0); in cfserl_create()
45 this->layer.receive = cfserl_receive; in cfserl_create()
46 this->layer.transmit = cfserl_transmit; in cfserl_create()
47 this->layer.ctrlcmd = cfserl_ctrlcmd; in cfserl_create()
50 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); in cfserl_create()
51 return &this->layer; in cfserl_create()
157 ret = layr->layer.up->receive(layr->layer.up, pkt); in cfserl_receive()
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H A Dcaif_usb.c33 struct cflayer layer; member
55 struct cfusbl *usbl = container_of(layr, struct cfusbl, layer); in cfusbl_transmit()
93 caif_assert(offsetof(struct cfusbl, layer) == 0); in cfusbl_create()
95 memset(&this->layer, 0, sizeof(this->layer)); in cfusbl_create()
96 this->layer.receive = cfusbl_receive; in cfusbl_create()
97 this->layer.transmit = cfusbl_transmit; in cfusbl_create()
98 this->layer.ctrlcmd = cfusbl_ctrlcmd; in cfusbl_create()
99 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "usb%d", phyid); in cfusbl_create()
100 this->layer.id = phyid; in cfusbl_create()
119 static void cfusbl_release(struct cflayer *layer) in cfusbl_release() argument
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H A Dcfsrvl.c25 #define container_obj(layr) container_of(layr, struct cfsrvl, layer)
121 info->channel_id = service->layer.id; in cfservl_modemcmd()
142 info->channel_id = service->layer.id; in cfservl_modemcmd()
154 static void cfsrvl_release(struct cflayer *layer) in cfsrvl_release() argument
156 struct cfsrvl *service = container_of(layer, struct cfsrvl, layer); in cfsrvl_release()
165 caif_assert(offsetof(struct cfsrvl, layer) == 0); in cfsrvl_init()
169 service->layer.id = channel_id; in cfsrvl_init()
170 service->layer.ctrlcmd = cfservl_ctrlcmd; in cfsrvl_init()
171 service->layer.modemcmd = cfservl_modemcmd; in cfsrvl_init()
186 bool cfsrvl_phyid_match(struct cflayer *layer, int phyid) in cfsrvl_phyid_match() argument
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H A Dcfmuxl.c18 #define container_obj(layr) container_of(layr, struct cfmuxl, layer)
25 struct cflayer layer; member
54 this->layer.receive = cfmuxl_receive; in cfmuxl_create()
55 this->layer.transmit = cfmuxl_transmit; in cfmuxl_create()
56 this->layer.ctrlcmd = cfmuxl_ctrlcmd; in cfmuxl_create()
61 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "mux"); in cfmuxl_create()
62 return &this->layer; in cfmuxl_create()
250 struct cflayer *layer; in cfmuxl_ctrlcmd() local
253 list_for_each_entry_rcu(layer, &muxl->srvl_list, node) { in cfmuxl_ctrlcmd()
255 if (cfsrvl_phyid_match(layer, phyid) && layer->ctrlcmd) { in cfmuxl_ctrlcmd()
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H A Dcfctrl.c17 #define container_obj(layr) container_of(layr, struct cfctrl, serv.layer)
42 caif_assert(offsetof(struct cfctrl, serv.layer) == 0); in cfctrl_create()
48 this->serv.layer.receive = cfctrl_recv; in cfctrl_create()
49 sprintf(this->serv.layer.name, "ctrl"); in cfctrl_create()
50 this->serv.layer.ctrlcmd = cfctrl_ctrlcmd; in cfctrl_create()
57 return &this->serv.layer; in cfctrl_create()
60 void cfctrl_remove(struct cflayer *layer) in cfctrl_remove() argument
63 struct cfctrl *ctrl = container_obj(layer); in cfctrl_remove()
71 kfree(layer); in cfctrl_remove()
163 struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer) in cfctrl_get_respfuncs() argument
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H A Dcfrfml.c17 #define container_obj(layr) container_of(layr, struct cfrfml, serv.layer)
34 static void cfrfml_release(struct cflayer *layer) in cfrfml_release() argument
36 struct cfsrvl *srvl = container_of(layer, struct cfsrvl, layer); in cfrfml_release()
37 struct cfrfml *rfml = container_obj(&srvl->layer); in cfrfml_release()
56 this->serv.layer.receive = cfrfml_receive; in cfrfml_create()
57 this->serv.layer.transmit = cfrfml_transmit; in cfrfml_create()
65 snprintf(this->serv.layer.name, CAIF_LAYER_NAME_SZ, in cfrfml_create()
68 return &this->serv.layer; in cfrfml_create()
167 err = rfml->serv.layer.up->receive(rfml->serv.layer.up, pkt); in cfrfml_receive()
201 cfpkt_info(pkt)->channel_id = rfml->serv.layer.id; in cfrfml_transmit_segment()
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/linux/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c280 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
288 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_setup_scaler()
295 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_setup_scaler()
327 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, in atmel_hlcdc_plane_setup_scaler()
337 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_xlcdc_plane_setup_scaler()
344 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_xlcdc_plane_setup_scaler()
355 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, in atmel_xlcdc_plane_setup_scaler()
361 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, in atmel_xlcdc_plane_setup_scaler()
363 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, in atmel_xlcdc_plane_setup_scaler()
397 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, in atmel_xlcdc_plane_setup_scaler()
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/linux/Documentation/networking/caif/
H A Dlinux_caif.rst66 CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
68 each layer described in the specification is implemented as a separate layer.
78 - Layered architecture (a la Streams), each layer in the CAIF
80 - Clients must call configuration function to add PHY layer.
81 - Clients must implement CAIF layer to consume/produce
84 Client layer.
100 - CFCNFG CAIF Configuration layer. Configures the CAIF Protocol
104 - CFCTRL CAIF Control layer. Encodes and Decodes control messages
111 - CFVEI CAIF VEI layer. Handles CAIF AT Channels on VEI (Virtual
112 External Interface). This layer encodes/decodes VEI frames.
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/linux/Documentation/hid/
H A Damd-sfh-hid.rst49 sensor data. The layer, which binds each device (AMD SFH HID driver) identifies the device type and
50 registers with the HID core. Transport layer attaches a constant "struct hid_ll_driver" object with
52 used by HID core to communicate with the device. AMD HID Transport layer implements the synchronous…
56 This layer is responsible to implement HID requests and descriptors. As firmware is OS agnostic, HID
57 client layer fills the HID request structure and descriptors. HID client layer is complex as it is
58 interface between MP2 PCIe layer and HID. HID client layer initializes the MP2 PCIe layer and holds
59 the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Based
61 enumeration of each sensor, client layer fills the HID Descriptor structure and HID input report
65 AMD MP2 PCIe layer
76 interrupt to MP2. The client layer allocates the physical memory and the same is sent to MP2 via
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/linux/fs/overlayfs/
H A Dexport.c89 return ovl_lowerstack(oe)->layer->idx; in ovl_connectable_layer()
111 origin_layer = ovl_lowerstack(oe)->layer->idx; in ovl_connect_layer()
318 ovl_lowerstack(oe)->layer = lowerpath->layer; in ovl_obtain_alias()
345 if (lowerstack[i].layer->idx == idx) in ovl_dentry_real_at()
360 const struct ovl_layer *layer) in ovl_lookup_real_one() argument
377 if (ovl_dentry_real_at(connected, layer->idx) != parent) in ovl_lookup_real_one()
399 } else if (ovl_dentry_real_at(this, layer->idx) != real) { in ovl_lookup_real_one()
412 real, layer->idx, connected, err); in ovl_lookup_real_one()
419 const struct ovl_layer *layer);
426 const struct ovl_layer *layer) in ovl_lookup_real_inode() argument
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/linux/drivers/gpu/drm/arm/
H A Dmalidp_planes.c291 mc->scaled_planes_mask &= ~(mp->layer->id); in malidp_se_check_scaling()
295 if (mp->layer->id & (DE_SMART | DE_GRAPHICS2)) in malidp_se_check_scaling()
298 mc->scaled_planes_mask |= mp->layer->id; in malidp_se_check_scaling()
483 if (!mp->layer->mmu_ctrl_offset) in malidp_de_prefetch_settings()
511 mp->layer->id, fb->format->format, in malidp_de_plane_check()
561 if (mp->layer->rot == ROTATE_NONE) in malidp_de_plane_check()
563 if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier)) in malidp_de_plane_check()
575 if (mp->layer->id == DE_SMART && fb->modifier) { in malidp_de_plane_check()
611 if (!mp->layer->stride_offset) in malidp_de_set_plane_pitches()
627 mp->layer->base + in malidp_de_set_plane_pitches()
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