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Searched refs:lane_width (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h97 uint8_t lane_width; member
H A Dvega20_hwmgr.c3381 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_emit_clock_levels() local
3495 lane_width = pptable->PcieLaneCount[i]; in vega20_emit_clock_levels()
3504 (lane_width == 1) ? "x1" : in vega20_emit_clock_levels()
3505 (lane_width == 2) ? "x2" : in vega20_emit_clock_levels()
3506 (lane_width == 3) ? "x4" : in vega20_emit_clock_levels()
3507 (lane_width == 4) ? "x8" : in vega20_emit_clock_levels()
3508 (lane_width == 5) ? "x12" : in vega20_emit_clock_levels()
3509 (lane_width == 6) ? "x16" : in vega20_emit_clock_levels()
3514 lane_width) ? in vega20_emit_clock_levels()
H A Dvega10_hwmgr.c1284 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
4690 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_emit_clock_levels() local
4764 lane_width = pptable->PcieLaneCount[i]; in vega10_emit_clock_levels()
4771 (lane_width == 1) ? "x1" : in vega10_emit_clock_levels()
4772 (lane_width == 2) ? "x2" : in vega10_emit_clock_levels()
4773 (lane_width == 3) ? "x4" : in vega10_emit_clock_levels()
4774 (lane_width == 4) ? "x8" : in vega10_emit_clock_levels()
4775 (lane_width == 5) ? "x12" : in vega10_emit_clock_levels()
4776 (lane_width == 6) ? "x16" : "", in vega10_emit_clock_levels()
4778 (current_lane_width == lane_width) ? in vega10_emit_clock_levels()
H A Dprocess_pptables_v1_0.c517 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
554 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
H A Dvega10_processpptables.c814 pcie_table->entries[i].lane_width = in get_pcie_table()
H A Dsmu7_hwmgr.c677 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c770 uint32_t gen_speed, lane_width; in arcturus_emit_clk_levels() local
861 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in arcturus_emit_clk_levels()
866 pcie_table->pcie_lane[0] = lane_width; in arcturus_emit_clk_levels()
870 lane_width, buf, offset); in arcturus_emit_clk_levels()
H A Dnavi10_ppt.c1253 uint32_t gen_speed, lane_width; in navi10_emit_clk_levels() local
1288 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_emit_clk_levels()
1291 lane_width, buf, offset); in navi10_emit_clk_levels()
H A Dsienna_cichlid_ppt.c1285 uint32_t gen_speed, lane_width; in sienna_cichlid_emit_clk_levels() local
1316 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in sienna_cichlid_emit_clk_levels()
1319 lane_width, buf, offset); in sienna_cichlid_emit_clk_levels()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c1221 uint32_t gen_speed, lane_width; in smu_v13_0_7_emit_clk_levels() local
1263 &lane_width); in smu_v13_0_7_emit_clk_levels()
1270 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v13_0_7_emit_clk_levels()
H A Dsmu_v13_0_0_ppt.c1211 uint32_t gen_speed, lane_width; in smu_v13_0_0_emit_clk_levels() local
1253 &lane_width); in smu_v13_0_0_emit_clk_levels()
1260 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v13_0_0_emit_clk_levels()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c1039 uint32_t gen_speed, lane_width; in smu_v14_0_2_emit_clk_levels() local
1082 &lane_width); in smu_v14_0_2_emit_clk_levels()
1089 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v14_0_2_emit_clk_levels()
/linux/drivers/gpu/drm/radeon/
H A Dsi_dpm.c4644 u32 lane_width; in si_init_smc_table() local
4715 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4716 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5861 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5869 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5870 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5239 u32 lane_width; in si_init_smc_table() local
5310 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5311 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6440 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6448 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6449 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()