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Searched refs:irq_enable_mask (Results 1 – 7 of 7) sorted by relevance

/linux/arch/mips/sgi-ip30/
H A Dip30-irq.c27 static DEFINE_PER_CPU(unsigned long, irq_enable_mask);
147 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_mask_heart_irq()
156 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_mask_and_ack_heart_irq()
166 unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu); in ip30_unmask_heart_irq()
250 unsigned long *mask = &per_cpu(irq_enable_mask, cpu); in ip30_install_ipi()
281 mask = &per_cpu(irq_enable_mask, 0); in arch_init_irq()
284 mask = &per_cpu(irq_enable_mask, 1); in arch_init_irq()
/linux/arch/mips/sgi-ip27/
H A Dip27-irq.c35 static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
55 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); in enable_hub_irq()
65 unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); in disable_hub_irq()
192 unsigned long *mask = per_cpu(irq_enable_mask, cpu); in ip27_do_irq_mask0()
232 unsigned long *mask = per_cpu(irq_enable_mask, cpu); in ip27_do_irq_mask1()
255 unsigned long *mask = per_cpu(irq_enable_mask, cpu); in install_ipi()
/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c428 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen6_irq_enable()
433 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_enable()
439 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_disable()
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
449 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); in hsw_irq_enable_vecs()
455 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); in hsw_irq_disable_vecs()
H A Dgen2_engine_cs.c295 engine->i915->gen2_imr_mask &= ~engine->irq_enable_mask; in gen2_irq_enable()
302 engine->i915->gen2_imr_mask |= engine->irq_enable_mask; in gen2_irq_disable()
308 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_enable()
313 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_disable()
H A Dintel_engine_types.h505 u32 irq_enable_mask; /* bitmask to enable ring interrupt */ member
/linux/drivers/pinctrl/
H A Dpinctrl-single.c136 unsigned irq_enable_mask; member
704 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
708 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
711 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
1416 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1587 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1942 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1947 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1953 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1959 .irq_enable_mask = (1 << 29), /* WKUP_EN */
/linux/drivers/dma/ti/
H A Domap-dma.c59 uint32_t irq_enable_mask; member
639 status &= od->irq_enable_mask; in omap_dma_irq()
732 od->irq_enable_mask |= val; in omap_dma_alloc_chan_resources()
733 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); in omap_dma_alloc_chan_resources()
767 od->irq_enable_mask &= ~BIT(c->dma_ch); in omap_dma_free_chan_resources()
768 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); in omap_dma_free_chan_resources()
1777 od->irq_enable_mask = 0; in omap_dma_probe()