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Searched refs:iq (Results 1 – 25 of 53) sorted by relevance

123

/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_tx.c16 static void octep_iq_reset_indices(struct octep_iq *iq) in octep_iq_reset_indices() argument
18 iq->fill_cnt = 0; in octep_iq_reset_indices()
19 iq->host_write_index = 0; in octep_iq_reset_indices()
20 iq->octep_read_index = 0; in octep_iq_reset_indices()
21 iq->flush_index = 0; in octep_iq_reset_indices()
22 iq->pkts_processed = 0; in octep_iq_reset_indices()
23 iq->pkt_in_done = 0; in octep_iq_reset_indices()
32 int octep_iq_process_completions(struct octep_iq *iq, u16 budget) in octep_iq_process_completions() argument
35 struct octep_device *oct = iq->octep_dev; in octep_iq_process_completions()
38 u32 fi = iq->flush_index; in octep_iq_process_completions()
[all …]
H A Doctep_main.c65 ioq_vector->iq = oct->iq[i]; in octep_alloc_ioq_vectors()
562 static void octep_update_pkt(struct octep_iq *iq, struct octep_oq *oq) in octep_update_pkt() argument
566 u32 pkts_processed = READ_ONCE(iq->pkts_processed); in octep_update_pkt()
567 u32 pkt_in_done = READ_ONCE(iq->pkt_in_done); in octep_update_pkt()
569 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); in octep_update_pkt()
571 writel(pkts_processed, iq->inst_cnt_reg); in octep_update_pkt()
572 readl(iq->inst_cnt_reg); in octep_update_pkt()
573 WRITE_ONCE(iq->pkt_in_done, (pkt_in_done - pkts_processed)); in octep_update_pkt()
574 WRITE_ONCE(iq->pkts_processed, 0); in octep_update_pkt()
592 static void octep_enable_ioq_irq(struct octep_iq *iq, struct octep_oq *oq) in octep_enable_ioq_irq() argument
[all …]
H A Doctep_main.h50 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ argument
54 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ argument
97 u32 (*update_iq_read_idx)(struct octep_iq *iq);
150 struct octep_iq *iq; member
259 struct octep_iq *iq[OCTEP_MAX_IQ]; member
410 int octep_iq_process_completions(struct octep_iq *iq, u16 budget);
H A Doctep_config.h60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
232 struct octep_iq_config iq; member
H A Doctep_cn9k_pf.c232 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; in octep_init_config_cn93_pf()
233 conf->iq.instr_type = OCTEP_64BYTE_INSTR; in octep_init_config_cn93_pf()
234 conf->iq.db_min = OCTEP_DB_MIN; in octep_init_config_cn93_pf()
235 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; in octep_init_config_cn93_pf()
265 struct octep_iq *iq = oct->iq[iq_no]; in octep_setup_iq_regs_cn93_pf() local
286 iq->desc_ring_dma); in octep_setup_iq_regs_cn93_pf()
288 iq->max_count); in octep_setup_iq_regs_cn93_pf()
293 iq->doorbell_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cn93_pf()
295 iq->inst_cnt_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cn93_pf()
297 iq->intr_lvl_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cn93_pf()
[all …]
H A Doctep_cnxk_pf.c252 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS; in octep_init_config_cnxk_pf()
253 conf->iq.instr_type = OCTEP_64BYTE_INSTR; in octep_init_config_cnxk_pf()
254 conf->iq.db_min = OCTEP_DB_MIN; in octep_init_config_cnxk_pf()
255 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD; in octep_init_config_cnxk_pf()
286 struct octep_iq *iq = oct->iq[iq_no]; in octep_setup_iq_regs_cnxk_pf() local
307 iq->desc_ring_dma); in octep_setup_iq_regs_cnxk_pf()
309 iq->max_count); in octep_setup_iq_regs_cnxk_pf()
314 iq->doorbell_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cnxk_pf()
316 iq->inst_cnt_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cnxk_pf()
318 iq->intr_lvl_reg = oct->mmio[0].hw_addr + in octep_setup_iq_regs_cnxk_pf()
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_tx.c17 static void octep_vf_iq_reset_indices(struct octep_vf_iq *iq) in octep_vf_iq_reset_indices() argument
19 iq->fill_cnt = 0; in octep_vf_iq_reset_indices()
20 iq->host_write_index = 0; in octep_vf_iq_reset_indices()
21 iq->octep_vf_read_index = 0; in octep_vf_iq_reset_indices()
22 iq->flush_index = 0; in octep_vf_iq_reset_indices()
23 iq->pkts_processed = 0; in octep_vf_iq_reset_indices()
24 iq->pkt_in_done = 0; in octep_vf_iq_reset_indices()
33 int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget) in octep_vf_iq_process_completions() argument
36 struct octep_vf_device *oct = iq->octep_vf_dev; in octep_vf_iq_process_completions()
39 u32 fi = iq->flush_index; in octep_vf_iq_process_completions()
[all …]
H A Doctep_vf_main.c62 ioq_vector->iq = oct->iq[i]; in octep_vf_alloc_ioq_vectors()
295 static void octep_vf_update_pkt(struct octep_vf_iq *iq, struct octep_vf_oq *oq) in octep_vf_update_pkt() argument
299 u32 pkts_processed = READ_ONCE(iq->pkts_processed); in octep_vf_update_pkt()
300 u32 pkt_in_done = READ_ONCE(iq->pkt_in_done); in octep_vf_update_pkt()
302 netdev_dbg(iq->netdev, "enabling intr for Q-%u\n", iq->q_no); in octep_vf_update_pkt()
304 writel(pkts_processed, iq->inst_cnt_reg); in octep_vf_update_pkt()
305 readl(iq->inst_cnt_reg); in octep_vf_update_pkt()
306 WRITE_ONCE(iq->pkt_in_done, (pkt_in_done - pkts_processed)); in octep_vf_update_pkt()
307 WRITE_ONCE(iq->pkts_processed, 0); in octep_vf_update_pkt()
325 static void octep_vf_enable_ioq_irq(struct octep_vf_iq *iq, in octep_vf_enable_ioq_irq() argument
[all …]
H A Doctep_vf_main.h35 #define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ argument
39 #define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ argument
64 u32 (*update_iq_read_idx)(struct octep_vf_iq *iq);
126 struct octep_vf_iq *iq; member
247 struct octep_vf_iq *iq[OCTEP_VF_MAX_IQ]; member
332 int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget);
H A Doctep_vf_cn9k.c146 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; in octep_vf_init_config_cn93_vf()
147 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; in octep_vf_init_config_cn93_vf()
148 conf->iq.db_min = OCTEP_VF_DB_MIN; in octep_vf_init_config_cn93_vf()
149 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; in octep_vf_init_config_cn93_vf()
163 struct octep_vf_iq *iq = oct->iq[iq_no]; in octep_vf_setup_iq_regs_cn93() local
181 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); in octep_vf_setup_iq_regs_cn93()
182 octep_vf_write_csr64(oct, CN93_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); in octep_vf_setup_iq_regs_cn93()
185 iq->doorbell_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_INSTR_DBELL(iq_no); in octep_vf_setup_iq_regs_cn93()
186 iq->inst_cnt_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_CNTS(iq_no); in octep_vf_setup_iq_regs_cn93()
187 iq->intr_lvl_reg = oct->mmio.hw_addr + CN93_VF_SDP_R_IN_INT_LEVELS(iq_no); in octep_vf_setup_iq_regs_cn93()
[all …]
H A Doctep_vf_cnxk.c148 conf->iq.num_descs = OCTEP_VF_IQ_MAX_DESCRIPTORS; in octep_vf_init_config_cnxk_vf()
149 conf->iq.instr_type = OCTEP_VF_64BYTE_INSTR; in octep_vf_init_config_cnxk_vf()
150 conf->iq.db_min = OCTEP_VF_DB_MIN; in octep_vf_init_config_cnxk_vf()
151 conf->iq.intr_threshold = OCTEP_VF_IQ_INTR_THRESHOLD; in octep_vf_init_config_cnxk_vf()
166 struct octep_vf_iq *iq = oct->iq[iq_no]; in octep_vf_setup_iq_regs_cnxk() local
184 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_BADDR(iq_no), iq->desc_ring_dma); in octep_vf_setup_iq_regs_cnxk()
185 octep_vf_write_csr64(oct, CNXK_VF_SDP_R_IN_INSTR_RSIZE(iq_no), iq->max_count); in octep_vf_setup_iq_regs_cnxk()
188 iq->doorbell_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INSTR_DBELL(iq_no); in octep_vf_setup_iq_regs_cnxk()
189 iq->inst_cnt_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_CNTS(iq_no); in octep_vf_setup_iq_regs_cnxk()
190 iq->intr_lvl_reg = oct->mmio.hw_addr + CNXK_VF_SDP_R_IN_INT_LEVELS(iq_no); in octep_vf_setup_iq_regs_cnxk()
[all …]
H A Doctep_vf_config.h56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
149 struct octep_vf_iq_config iq; member
/linux/drivers/net/ethernet/cavium/liquidio/
H A Drequest_manager.c51 struct octeon_instr_queue *iq; in octeon_init_instr_queue() local
73 iq = oct->instr_queue[iq_no]; in octeon_init_instr_queue()
75 iq->oct_dev = oct; in octeon_init_instr_queue()
77 iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma); in octeon_init_instr_queue()
78 if (!iq->base_addr) { in octeon_init_instr_queue()
84 iq->max_count = num_descs; in octeon_init_instr_queue()
89 iq->request_list = vzalloc_node(array_size(num_descs, sizeof(*iq->request_list)), in octeon_init_instr_queue()
91 if (!iq->request_list) in octeon_init_instr_queue()
92 iq->request_list = vzalloc(array_size(num_descs, sizeof(*iq->request_list))); in octeon_init_instr_queue()
93 if (!iq->request_list) { in octeon_init_instr_queue()
[all …]
H A Dcn23xx_vf_regs.h70 #define CN23XX_VF_SLI_IQ_PKT_CONTROL64(iq) \ argument
71 (CN23XX_VF_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
73 #define CN23XX_VF_SLI_IQ_BASE_ADDR64(iq) \ argument
74 (CN23XX_VF_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
76 #define CN23XX_VF_SLI_IQ_SIZE(iq) \ argument
77 (CN23XX_VF_SLI_IQ_SIZE_START + ((iq) * CN23XX_VF_IQ_OFFSET))
79 #define CN23XX_VF_SLI_IQ_DOORBELL(iq) \ argument
80 (CN23XX_VF_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_VF_IQ_OFFSET))
82 #define CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq) \ argument
83 (CN23XX_VF_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_VF_IQ_OFFSET))
H A Dcn66xx_regs.h143 #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \ argument
144 (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))
146 #define CN6XXX_SLI_IQ_SIZE(iq) \ argument
147 (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET))
149 #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \ argument
150 (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET))
152 #define CN6XXX_SLI_IQ_DOORBELL(iq) \ argument
153 (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET))
155 #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \ argument
156 (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSET))
[all …]
H A Dcn23xx_vf_device.c104 struct octeon_instr_queue *iq; in cn23xx_vf_setup_global_input_regs() local
116 iq = oct->instr_queue[q_no]; in cn23xx_vf_setup_global_input_regs()
118 if (iq) in cn23xx_vf_setup_global_input_regs()
119 inst_cnt_reg = iq->inst_cnt_reg; in cn23xx_vf_setup_global_input_regs()
214 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in cn23xx_setup_vf_iq_regs() local
219 iq->base_addr_dma); in cn23xx_setup_vf_iq_regs()
220 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count); in cn23xx_setup_vf_iq_regs()
225 iq->doorbell_reg = in cn23xx_setup_vf_iq_regs()
227 iq->inst_cnt_reg = in cn23xx_setup_vf_iq_regs()
230 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); in cn23xx_setup_vf_iq_regs()
[all …]
H A Dcn23xx_pf_regs.h170 #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ argument
171 (CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET))
173 #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \ argument
174 (CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET))
176 #define CN23XX_SLI_IQ_SIZE(iq) \ argument
177 (CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET))
179 #define CN23XX_SLI_IQ_DOORBELL(iq) \ argument
180 (CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET))
182 #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ argument
183 (CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSET))
H A Dcn66xx_device.c266 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn6xxx_setup_iq_regs() local
272 iq->base_addr_dma); in lio_cn6xxx_setup_iq_regs()
273 octeon_write_csr(oct, CN6XXX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn6xxx_setup_iq_regs()
278 iq->doorbell_reg = oct->mmio[0].hw_addr + CN6XXX_SLI_IQ_DOORBELL(iq_no); in lio_cn6xxx_setup_iq_regs()
279 iq->inst_cnt_reg = oct->mmio[0].hw_addr in lio_cn6xxx_setup_iq_regs()
282 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
287 iq->reset_instr_cnt = readl(iq->inst_cnt_reg); in lio_cn6xxx_setup_iq_regs()
339 mask |= oct->io_qmask.iq; in lio_cn6xxx_enable_io_queues()
357 mask ^= oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
361 mask = (u32)oct->io_qmask.iq; in lio_cn6xxx_disable_io_queues()
[all …]
H A Docteon_config.h121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
410 struct octeon_iq_config iq; member
H A Dcn23xx_pf_device.c234 struct octeon_instr_queue *iq; in cn23xx_pf_setup_global_input_regs() local
277 iq = oct->instr_queue[q_no]; in cn23xx_pf_setup_global_input_regs()
278 if (iq) in cn23xx_pf_setup_global_input_regs()
279 inst_cnt_reg = iq->inst_cnt_reg; in cn23xx_pf_setup_global_input_regs()
420 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in cn23xx_setup_iq_regs() local
427 iq->base_addr_dma); in cn23xx_setup_iq_regs()
428 octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count); in cn23xx_setup_iq_regs()
433 iq->doorbell_reg = in cn23xx_setup_iq_regs()
435 iq->inst_cnt_reg = in cn23xx_setup_iq_regs()
438 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); in cn23xx_setup_iq_regs()
[all …]
H A Docteon_device.c41 .iq = {
150 .iq = {
316 .iq = {
419 .iq = {
656 if (oct->io_qmask.iq & BIT_ULL(i)) in octeon_free_device_mem()
1286 (oct->io_qmask.iq & BIT_ULL(q_no))) in octeon_get_tx_qsize()
1436 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq) in lio_enable_irq() argument
1449 if (iq) { in lio_enable_irq()
1450 spin_lock_bh(&iq->lock); in lio_enable_irq()
1451 writel(iq->pkts_processed, iq->inst_cnt_reg); in lio_enable_irq()
[all …]
H A Dlio_vf_main.c121 struct octeon_instr_queue *iq; in pcierror_quiesce_device() local
123 if (!(oct->io_qmask.iq & BIT_ULL(i))) in pcierror_quiesce_device()
125 iq = oct->instr_queue[i]; in pcierror_quiesce_device()
127 if (atomic_read(&iq->instr_pending)) { in pcierror_quiesce_device()
128 spin_lock_bh(&iq->lock); in pcierror_quiesce_device()
129 iq->fill_cnt = 0; in pcierror_quiesce_device()
130 iq->octeon_read_index = iq->host_write_index; in pcierror_quiesce_device()
131 iq->stats.instr_processed += in pcierror_quiesce_device()
132 atomic_read(&iq->instr_pending); in pcierror_quiesce_device()
133 lio_process_iq_request_list(oct, iq, 0); in pcierror_quiesce_device()
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptlf.h140 struct otx2_cpt_inst_queue *iq; in otx2_cpt_free_instruction_queues() local
144 iq = &lfs->lf[i].iqueue; in otx2_cpt_free_instruction_queues()
145 if (iq->real_vaddr) in otx2_cpt_free_instruction_queues()
147 iq->size, in otx2_cpt_free_instruction_queues()
148 iq->real_vaddr, in otx2_cpt_free_instruction_queues()
149 iq->real_dma_addr); in otx2_cpt_free_instruction_queues()
150 iq->real_vaddr = NULL; in otx2_cpt_free_instruction_queues()
151 iq->vaddr = NULL; in otx2_cpt_free_instruction_queues()
158 struct otx2_cpt_inst_queue *iq; in otx2_cpt_alloc_instruction_queues() local
165 iq = &lfs->lf[i].iqueue; in otx2_cpt_alloc_instruction_queues()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dcn10k_ipsec.c235 struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq; in cn10k_outb_cptlf_iq_alloc() local
237 iq->size = CN10K_CPT_INST_QLEN_BYTES + CN10K_CPT_Q_FC_LEN + in cn10k_outb_cptlf_iq_alloc()
240 iq->real_vaddr = dma_alloc_coherent(pf->dev, iq->size, in cn10k_outb_cptlf_iq_alloc()
241 &iq->real_dma_addr, GFP_KERNEL); in cn10k_outb_cptlf_iq_alloc()
242 if (!iq->real_vaddr) in cn10k_outb_cptlf_iq_alloc()
246 iq->vaddr = iq->real_vaddr + CN10K_CPT_INST_GRP_QLEN_BYTES; in cn10k_outb_cptlf_iq_alloc()
247 iq->dma_addr = iq->real_dma_addr + CN10K_CPT_INST_GRP_QLEN_BYTES; in cn10k_outb_cptlf_iq_alloc()
250 iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_ALIGN); in cn10k_outb_cptlf_iq_alloc()
251 iq->dma_addr = PTR_ALIGN(iq->dma_addr, OTX2_ALIGN); in cn10k_outb_cptlf_iq_alloc()
257 struct cn10k_cpt_inst_queue *iq = &pf->ipsec.iq; in cn10k_outb_cptlf_iq_free() local
[all …]
/linux/drivers/scsi/csiostor/
H A Dcsio_isr.c212 csio_scsi_isr_handler(struct csio_q *iq) in csio_scsi_isr_handler() argument
214 struct csio_hw *hw = (struct csio_hw *)iq->owner; in csio_scsi_isr_handler()
223 if (unlikely(csio_wr_process_iq(hw, iq, csio_process_scsi_cmpl, in csio_scsi_isr_handler()
258 struct csio_q *iq = (struct csio_q *) dev_id; in csio_scsi_isr() local
261 if (unlikely(!iq)) in csio_scsi_isr()
264 hw = (struct csio_hw *)iq->owner; in csio_scsi_isr()
271 csio_scsi_isr_handler(iq); in csio_scsi_isr()
288 struct csio_q *iq = priv; in csio_scsi_intx_handler() local
290 csio_scsi_isr_handler(iq); in csio_scsi_intx_handler()

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