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Searched refs:intel_de_rmw (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c474 intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); in intel_fdi_normal_train()
545 intel_de_rmw(display, FDI_TX_CTL(pipe), in ilk_fdi_link_train()
547 intel_de_rmw(display, FDI_RX_CTL(pipe), in ilk_fdi_link_train()
635 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
686 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
807 intel_de_rmw(display, FDI_TX_CTL(pipe), in ivb_manual_fdi_link_train()
810 intel_de_rmw(display, FDI_RX_CTL(pipe), in ivb_manual_fdi_link_train()
923 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
950 intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_link_train()
954 intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); in hsw_fdi_link_train()
[all …]
H A Dicl_dsi.c246 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, in icl_dsi_frame_update()
270 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
280 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
286 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
290 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), in dsi_program_swing_and_deemphasis()
334 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, in configure_dual_link_mode()
423 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), in gen11_dsi_enable_io_power()
450 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), in gen11_dsi_config_phy_lanes_sequence()
453 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), in gen11_dsi_config_phy_lanes_sequence()
459 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), in gen11_dsi_config_phy_lanes_sequence()
[all …]
H A Dintel_combo_phy.c87 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
305 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
366 intel_de_rmw(display, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
369 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
370 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
401 intel_de_rmw(display, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
405 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()
H A Dvlv_dsi.c340 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
343 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
349 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
383 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
388 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
393 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
402 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
406 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
410 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); in glk_dsi_device_ready()
442 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
[all …]
H A Dintel_dpt_common.c24 intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
30 intel_de_rmw(display, CHICKEN_MISC_2, in intel_dpt_configure()
H A Dintel_dpio_phy.c321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
331 intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
345 intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
420 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); in _bxt_dpio_phy_init()
436 intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy), in _bxt_dpio_phy_init()
439 intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy), in _bxt_dpio_phy_init()
443 intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0, in _bxt_dpio_phy_init()
447 intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0, in _bxt_dpio_phy_init()
467 intel_de_rmw(display, BXT_PORT_REF_DW8(phy), in _bxt_dpio_phy_init()
474 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); in _bxt_dpio_phy_init()
[all …]
H A Dintel_display_power_well.c395 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); in hsw_power_well_enable()
408 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in hsw_power_well_enable()
434 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in hsw_power_well_disable()
454 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in icl_combo_phy_aux_power_well_enable()
460 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_enable()
468 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_enable()
485 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), in icl_combo_phy_aux_power_well_disable()
488 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in icl_combo_phy_aux_power_well_disable()
554 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), in icl_tc_phy_aux_power_well_enable()
557 intel_de_rmw(display, regs->driver, in icl_tc_phy_aux_power_well_enable()
[all …]
H A Dintel_pch_display.c327 intel_de_rmw(display, reg, TRANS_ENABLE, 0); in ilk_disable_pch_transcoder()
335 intel_de_rmw(display, TRANS_CHICKEN2(pipe), in ilk_disable_pch_transcoder()
465 intel_de_rmw(display, TRANS_DP_CTL(pipe), in ilk_pch_post_disable()
470 intel_de_rmw(display, PCH_DPLL_SEL, in ilk_pch_post_disable()
582 intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0); in lpt_disable_pch_transcoder()
589 intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
H A Dvlv_dsi_pll.c316 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0); in bxt_dsi_pll_disable()
568 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE); in bxt_dsi_pll_enable()
595 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); in bxt_dsi_reset_clocks()
597 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); in bxt_dsi_reset_clocks()
H A Dintel_pmdemand.c134 intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
504 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0), in intel_pmdemand_program_dbuf()
507 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_dbuf()
616 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_params()
H A Dintel_psr.c390 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in psr_irq_control()
454 val = intel_de_rmw(display, in intel_psr_irq_handler()
476 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), in intel_psr_irq_handler()
964 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), in hsw_activate_psr1()
1043 intel_de_rmw(display, in dg2_activate_panel_replay()
1047 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, in dg2_activate_panel_replay()
1176 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), in psr2_program_idle_frames()
2005 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
2008 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
2081 intel_de_rmw(display, in intel_psr_enable_source()
[all …]
H A Dintel_dmc.c436 intel_de_rmw(display, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
483 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
487 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
498 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
809 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
811 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
825 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
827 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
882 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), in intel_dmc_block_pkgc()
H A Dintel_dsi_vbt.c354 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in icl_native_gpio_set_value()
364 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, in icl_native_gpio_set_value()
371 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
378 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
387 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
H A Dintel_dvo.c196 intel_de_rmw(display, DVO(port), DVO_ENABLE, 0); in intel_disable_dvo()
213 intel_de_rmw(display, DVO(port), 0, DVO_ENABLE); in intel_enable_dvo()
461 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, in intel_dvo_init_dev()
H A Dintel_backlight.c365 intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in lpt_disable_backlight()
375 intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0); in pch_disable_backlight()
377 intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in pch_disable_backlight()
392 intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); in i965_disable_backlight()
403 intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0); in vlv_disable_backlight()
414 intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), in bxt_disable_backlight()
418 intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0); in bxt_disable_backlight()
429 intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), in cnp_disable_backlight()
493 intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, in lpt_enable_backlight()
497 intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY, in lpt_enable_backlight()
H A Dintel_lvds.c327 intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN); in intel_enable_lvds()
329 intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON); in intel_enable_lvds()
347 intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0); in intel_disable_lvds()
352 intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0); in intel_disable_lvds()
H A Dintel_dkl_phy.c96 intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set); in intel_dkl_phy_rmw()
H A Dintel_fbc.c542 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS, in fbc_compressor_clkgate_disable_wa()
545 intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id), in fbc_compressor_clkgate_disable_wa()
654 intel_de_rmw(display, CHICKEN_MISC_4, in skl_fbc_program_cfb_stride()
716 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), in ivb_fbc_set_false_color()
938 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
948 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
954 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
962 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), in intel_fbc_program_workarounds()
H A Dintel_display_irq.c963 psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0); in _ivb_display_irq_handler()
1298 psr_iir = intel_de_rmw(display, iir_reg, 0, 0); in gen8_de_misc_irq_handler()
1368 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); in gen11_dsi_te_interrupt_handler()
1396 pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); in gen8_read_and_ack_pch_irqs()
1764 intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT); in gen11_dsi_configure_te()
1766 intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); in gen11_dsi_configure_te()
1942 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); in _vlv_display_irq_reset()
1962 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); in i9xx_display_irq_reset()
H A Dintel_gmbus.c222 intel_de_rmw(display, DSPCLK_GATE_D, in pnv_gmbus_clock_gating()
230 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in pch_gmbus_clock_gating()
238 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, in bxt_gmbus_clock_gating()
H A Dintel_pch_refclk.c22 intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL); in lpt_fdi_reset_mphy()
29 intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0); in lpt_fdi_reset_mphy()
H A Dintel_de.h87 intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) in intel_de_rmw() function
H A Dintel_cdclk.c898 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
910 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
913 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
1104 intel_de_rmw(display, DPLL_CTRL1, in skl_dpll0_enable()
1112 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_enable()
1126 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_disable()
1847 intel_de_rmw(display, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1874 intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK); in icl_cdclk_pll_disable()
1876 intel_de_rmw(display, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
H A Dintel_casf.c85 intel_de_rmw(display, SHARPNESS_CTL(crtc->pipe), FILTER_STRENGTH_MASK, in intel_casf_update_strength()
H A Dintel_dp_test.c236 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_dp_phy_pattern_update()
297 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), in intel_dp_phy_pattern_update()

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