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Searched refs:intel_ctrl (Results 1 – 4 of 4) sorted by relevance

/linux/arch/x86/events/zhaoxin/
H A Dcore.c263 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
607 x86_pmu.intel_ctrl = x86_pmu.cntr_mask64; in zhaoxin_pmu_init()
608 x86_pmu.intel_ctrl |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED; in zhaoxin_pmu_init()
/linux/arch/x86/events/intel/
H A Dcore.c2528 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); in __intel_pmu_enable_all() local
2538 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); in __intel_pmu_enable_all()
3600 status &= hybrid(cpuc->pmu, intel_ctrl); in handle_pmi_common()
4679 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & in intel_pmu_hw_config()
5000 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); in intel_guest_get_msrs() local
5013 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, in intel_guest_get_msrs()
5014 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask, in intel_guest_get_msrs()
5671 u64 *intel_ctrl) in intel_pmu_check_counters_mask() argument
5681 *intel_ctrl = *cntr_mask; in intel_pmu_check_counters_mask()
5690 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED; in intel_pmu_check_counters_mask()
[all …]
/linux/arch/x86/events/
H A Dperf_event.h737 u64 intel_ctrl; member
927 u64 intel_ctrl; member
1452 u64 intel_ctrl = hybrid(pmu, intel_ctrl); in fixed_counter_disabled() local
1454 return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); in fixed_counter_disabled()
H A Dcore.c2127 pr_info("... global_ctrl mask: %016llx\n", hybrid(pmu, intel_ctrl)); in x86_pmu_show_pmu_cap()
2175 if (!x86_pmu.intel_ctrl) in init_hw_perf_events()
2176 x86_pmu.intel_ctrl = x86_pmu.cntr_mask64; in init_hw_perf_events()