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Searched refs:input_rate (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll() argument
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
H A Dclk.h231 unsigned long input_rate; member
/linux/drivers/clk/tegra/
H A Dclk-pll.c526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
959 unsigned long input_rate; in clk_plle_enable() local
966 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable()
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
1122 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1132 input_rate in clk_pllu_enable()
1254 tegra_pll_get_fixed_mdiv(struct clk_hw * hw,unsigned long input_rate) tegra_pll_get_fixed_mdiv() argument
1453 _pllcx_update_dynamic_coef(struct tegra_clk_pll * pll,unsigned long input_rate,u32 n) _pllcx_update_dynamic_coef() argument
1616 unsigned long input_rate; clk_plle_tegra114_enable() local
1745 unsigned long flags = 0, input_rate; clk_pllu_tegra114_enable() local
2455 unsigned long input_rate; clk_plle_tegra210_enable() local
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H A Dclk-tegra210.c1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1115 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1117 input_rate = 38400000; in pllx_get_dyn_steps()
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1121 switch (input_rate) { in pllx_get_dyn_steps()
1138 __func__, input_rate); in pllx_get_dyn_steps()
1464 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1480 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg() argument
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
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H A Dclk.h156 * @input_rate: input rate from source
165 unsigned long input_rate; member
906 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
/linux/sound/pci/ctxfi/
H A Dctatc.c192 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch() argument
198 pitch = (input_rate / output_rate) << 24; in atc_get_pitch()
199 input_rate %= output_rate; in atc_get_pitch()
200 input_rate /= 100; in atc_get_pitch()
202 for (b = 31; ((b >= 0) && !(input_rate >> b)); ) in atc_get_pitch()
206 input_rate <<= (31 - b); in atc_get_pitch()
207 input_rate /= output_rate; in atc_get_pitch()
210 input_rate <<= b; in atc_get_pitch()
212 input_rate >>= -b; in atc_get_pitch()
214 pitch |= input_rate; in atc_get_pitch()
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/linux/sound/soc/stm/
H A Dstm32_i2s.c286 unsigned long input_rate, in stm32_i2s_calc_clk_div() argument
292 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_i2s_calc_clk_div()
313 if (input_rate % divider) in stm32_i2s_calc_clk_div()
316 output_rate, input_rate / divider); in stm32_i2s_calc_clk_div()
H A Dstm32_sai_sub.c322 unsigned long input_rate, in stm32_sai_get_clk_div() argument
328 div = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_sai_get_clk_div()
335 if (input_rate % div) in stm32_sai_get_clk_div()
338 output_rate, input_rate / div); in stm32_sai_get_clk_div()