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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_lrc.c305 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
310 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
315 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
320 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
325 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
330 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
335 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
340 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
345 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
350 i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)), in live_lrc_fixed()
[all …]
H A Dselftest_workarounds.c157 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
184 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
465 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
520 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
870 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
906 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
961 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
965 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
989 i915_mmio_reg_offset(reg), a, b); in result_eq()
1011 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
H A Dselftest_mocs.c152 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in read_l3cc_table()
197 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in check_l3cc_table()
H A Dgen8_engine_cs.c210 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
218 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
503 *cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)); in __xehp_emit_bb_start()
H A Dgen7_renderclear.c400 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); in emit_batch()
406 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
H A Dselftest_rc6.c178 *cs++ = i915_mmio_reg_offset(GEN8_RC6_CTX_INFO); in __live_rc6_ctx()
H A Dselftest_engine_cs.c70 *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine)); in write_timestamp()
H A Dselftest_engine_pm.c60 *cs++ = i915_mmio_reg_offset(reg); in emit_srm()
H A Dintel_gt_mcr.c566 u32 offset = i915_mmio_reg_offset(reg); in reg_needs_read_steering()
H A Dintel_mocs.c653 return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); in global_mocs_offset()
H A Dselftest_timeline.c778 const u32 gpr = i915_mmio_reg_offset(GEN8_RING_CS_GPR(rq->engine->mmio_base, 0)); in emit_read_hwsp()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c340 i915_mmio_reg_offset(reg), \
366 return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags); in guc_mcr_reg_add()
421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()
H A Dintel_guc_capture.c266 ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg)); in __fill_ext_reg()
/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.h324 u32 offset = i915_mmio_reg_offset(reg); \
334 u32 offset = i915_mmio_reg_offset(reg); \
514 readl(base + i915_mmio_reg_offset(reg))
516 writel(value, base + i915_mmio_reg_offset(reg))
H A Dintel_uncore_trace.h31 __entry->reg = i915_mmio_reg_offset(reg);
H A Di915_ioctl.c55 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
H A Dintel_device_info.c348 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), in intel_ipver_early_init()
356 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), in intel_ipver_early_init()
H A Di915_cmd_parser.c848 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); in check_sorted()
1132 int ret = addr - i915_mmio_reg_offset(table[mid].addr); in __find_reg()
H A Di915_query.c216 unsafe_put_user(i915_mmio_reg_offset(kernel_regs[r].addr), in copy_perf_config_registers_or_number()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c166 *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); in prepare_blit()
206 *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); in prepare_blit()
H A Di915_gem_context.c926 *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base)); in rpcs_query_batch()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dmc_wl.c230 u32 offset = i915_mmio_reg_offset(reg); in intel_dmc_wl_reg_in_range()
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c307 gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0)); in live_noa_gpr()
H A Di915_request.c1962 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP((ce->engine->mmio_base))); in emit_timestamp_store()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2224 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()

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