1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
7
8 #include <hyperv/hvhdk.h>
9
10 /*
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
13 */
14
15 enum intercept_words {
16 INTERCEPT_CR = 0,
17 INTERCEPT_DR,
18 INTERCEPT_EXCEPTION,
19 INTERCEPT_WORD3,
20 INTERCEPT_WORD4,
21 INTERCEPT_WORD5,
22 MAX_INTERCEPT,
23 };
24
25 enum {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
37 INTERCEPT_DR1_READ,
38 INTERCEPT_DR2_READ,
39 INTERCEPT_DR3_READ,
40 INTERCEPT_DR4_READ,
41 INTERCEPT_DR5_READ,
42 INTERCEPT_DR6_READ,
43 INTERCEPT_DR7_READ,
44 INTERCEPT_DR0_WRITE = 48,
45 INTERCEPT_DR1_WRITE,
46 INTERCEPT_DR2_WRITE,
47 INTERCEPT_DR3_WRITE,
48 INTERCEPT_DR4_WRITE,
49 INTERCEPT_DR5_WRITE,
50 INTERCEPT_DR6_WRITE,
51 INTERCEPT_DR7_WRITE,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
55 INTERCEPT_INTR = 96,
56 INTERCEPT_NMI,
57 INTERCEPT_SMI,
58 INTERCEPT_INIT,
59 INTERCEPT_VINTR,
60 INTERCEPT_SELECTIVE_CR0,
61 INTERCEPT_STORE_IDTR,
62 INTERCEPT_STORE_GDTR,
63 INTERCEPT_STORE_LDTR,
64 INTERCEPT_STORE_TR,
65 INTERCEPT_LOAD_IDTR,
66 INTERCEPT_LOAD_GDTR,
67 INTERCEPT_LOAD_LDTR,
68 INTERCEPT_LOAD_TR,
69 INTERCEPT_RDTSC,
70 INTERCEPT_RDPMC,
71 INTERCEPT_PUSHF,
72 INTERCEPT_POPF,
73 INTERCEPT_CPUID,
74 INTERCEPT_RSM,
75 INTERCEPT_IRET,
76 INTERCEPT_INTn,
77 INTERCEPT_INVD,
78 INTERCEPT_PAUSE,
79 INTERCEPT_HLT,
80 INTERCEPT_INVLPG,
81 INTERCEPT_INVLPGA,
82 INTERCEPT_IOIO_PROT,
83 INTERCEPT_MSR_PROT,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
86 INTERCEPT_SHUTDOWN,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
89 INTERCEPT_VMMCALL,
90 INTERCEPT_VMLOAD,
91 INTERCEPT_VMSAVE,
92 INTERCEPT_STGI,
93 INTERCEPT_CLGI,
94 INTERCEPT_SKINIT,
95 INTERCEPT_RDTSCP,
96 INTERCEPT_ICEBP,
97 INTERCEPT_WBINVD,
98 INTERCEPT_MONITOR,
99 INTERCEPT_MWAIT,
100 INTERCEPT_MWAIT_COND,
101 INTERCEPT_XSETBV,
102 INTERCEPT_RDPRU,
103 TRAP_EFER_WRITE,
104 TRAP_CR0_WRITE,
105 TRAP_CR1_WRITE,
106 TRAP_CR2_WRITE,
107 TRAP_CR3_WRITE,
108 TRAP_CR4_WRITE,
109 TRAP_CR5_WRITE,
110 TRAP_CR6_WRITE,
111 TRAP_CR7_WRITE,
112 TRAP_CR8_WRITE,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
116 INTERCEPT_INVPCID,
117 INTERCEPT_MCOMMIT,
118 INTERCEPT_TLBSYNC,
119 INTERCEPT_BUSLOCK,
120 INTERCEPT_IDLE_HLT = 166,
121 };
122
123
124 struct __attribute__ ((__packed__)) vmcb_control_area {
125 u32 intercepts[MAX_INTERCEPT];
126 u32 reserved_1[15 - MAX_INTERCEPT];
127 u16 pause_filter_thresh;
128 u16 pause_filter_count;
129 u64 iopm_base_pa;
130 u64 msrpm_base_pa;
131 u64 tsc_offset;
132 u32 asid;
133 u8 tlb_ctl;
134 u8 erap_ctl;
135 u8 reserved_2[2];
136 u32 int_ctl;
137 u32 int_vector;
138 u32 int_state;
139 u8 reserved_3[4];
140 u64 exit_code;
141 u64 exit_info_1;
142 u64 exit_info_2;
143 u32 exit_int_info;
144 u32 exit_int_info_err;
145 u64 nested_ctl;
146 u64 avic_vapic_bar;
147 u64 ghcb_gpa;
148 u32 event_inj;
149 u32 event_inj_err;
150 u64 nested_cr3;
151 u64 virt_ext;
152 u32 clean;
153 u32 reserved_5;
154 u64 next_rip;
155 u8 insn_len;
156 u8 insn_bytes[15];
157 u64 avic_backing_page; /* Offset 0xe0 */
158 u8 reserved_6[8]; /* Offset 0xe8 */
159 u64 avic_logical_id; /* Offset 0xf0 */
160 u64 avic_physical_id; /* Offset 0xf8 */
161 u8 reserved_7[8];
162 u64 vmsa_pa; /* Used for an SEV-ES guest */
163 u8 reserved_8[16];
164 u16 bus_lock_counter; /* Offset 0x120 */
165 u8 reserved_9[22];
166 u64 allowed_sev_features; /* Offset 0x138 */
167 u64 guest_sev_features; /* Offset 0x140 */
168 u8 reserved_10[664];
169 /*
170 * Offset 0x3e0, 32 bytes reserved
171 * for use by hypervisor/software.
172 */
173 union {
174 struct hv_vmcb_enlightenments hv_enlightenments;
175 u8 reserved_sw[32];
176 };
177 };
178
179
180 #define TLB_CONTROL_DO_NOTHING 0
181 #define TLB_CONTROL_FLUSH_ALL_ASID 1
182 #define TLB_CONTROL_FLUSH_ASID 3
183 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
184
185 #define ERAP_CONTROL_ALLOW_LARGER_RAP BIT(0)
186 #define ERAP_CONTROL_CLEAR_RAP BIT(1)
187
188 #define V_TPR_MASK 0x0f
189
190 #define V_IRQ_SHIFT 8
191 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
192
193 #define V_GIF_SHIFT 9
194 #define V_GIF_MASK (1 << V_GIF_SHIFT)
195
196 #define V_NMI_PENDING_SHIFT 11
197 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
198
199 #define V_NMI_BLOCKING_SHIFT 12
200 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
201
202 #define V_INTR_PRIO_SHIFT 16
203 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
204
205 #define V_IGN_TPR_SHIFT 20
206 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
207
208 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
209
210 #define V_INTR_MASKING_SHIFT 24
211 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
212
213 #define V_GIF_ENABLE_SHIFT 25
214 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
215
216 #define V_NMI_ENABLE_SHIFT 26
217 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
218
219 #define AVIC_ENABLE_SHIFT 31
220 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
221
222 #define X2APIC_MODE_SHIFT 30
223 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
224
225 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
226 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
227
228 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
229 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
230
231 #define SVM_IOIO_STR_SHIFT 2
232 #define SVM_IOIO_REP_SHIFT 3
233 #define SVM_IOIO_SIZE_SHIFT 4
234 #define SVM_IOIO_ASIZE_SHIFT 7
235
236 #define SVM_IOIO_TYPE_MASK 1
237 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
238 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
239 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
240 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
241
242 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
243 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
244 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
245
246
247 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
248 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
249 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
250 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
251
252
253 /* AVIC */
254 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
255 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
256 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
257
258 /*
259 * GA_LOG_INTR is a synthetic flag that's never propagated to hardware-visible
260 * tables. GA_LOG_INTR is set if the vCPU needs device posted IRQs to generate
261 * GA log interrupts to wake the vCPU (because it's blocking or about to block).
262 */
263 #define AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR BIT_ULL(61)
264
265 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
266 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12)
267 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
268 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
269 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
270
271 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
272
273 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
274 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
275 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
276
277 enum avic_ipi_failure_cause {
278 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
279 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
280 AVIC_IPI_FAILURE_INVALID_TARGET,
281 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
282 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR,
283 };
284
285 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(11, 0)
286
287 /*
288 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
289 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
290 */
291 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
292
293 /*
294 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
295 * With X86_FEATURE_X2AVIC_EXT, the max index is increased to 0xfff (4095).
296 */
297 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
298 #define X2AVIC_4K_MAX_PHYSICAL_ID 0xFFFUL
299
300 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
301 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
302 static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_4K_MAX_PHYSICAL_ID);
303
304 #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0)
305 #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3)
306 #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4)
307 #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5)
308 #define SVM_SEV_FEAT_SECURE_TSC BIT(9)
309
310 #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63)
311
312 struct vmcb_seg {
313 u16 selector;
314 u16 attrib;
315 u32 limit;
316 u64 base;
317 } __packed;
318
319 /* Save area definition for legacy and SEV-MEM guests */
320 struct vmcb_save_area {
321 struct vmcb_seg es;
322 struct vmcb_seg cs;
323 struct vmcb_seg ss;
324 struct vmcb_seg ds;
325 struct vmcb_seg fs;
326 struct vmcb_seg gs;
327 struct vmcb_seg gdtr;
328 struct vmcb_seg ldtr;
329 struct vmcb_seg idtr;
330 struct vmcb_seg tr;
331 /* Reserved fields are named following their struct offset */
332 u8 reserved_0xa0[42];
333 u8 vmpl;
334 u8 cpl;
335 u8 reserved_0xcc[4];
336 u64 efer;
337 u8 reserved_0xd8[112];
338 u64 cr4;
339 u64 cr3;
340 u64 cr0;
341 u64 dr7;
342 u64 dr6;
343 u64 rflags;
344 u64 rip;
345 u8 reserved_0x180[88];
346 u64 rsp;
347 u64 s_cet;
348 u64 ssp;
349 u64 isst_addr;
350 u64 rax;
351 u64 star;
352 u64 lstar;
353 u64 cstar;
354 u64 sfmask;
355 u64 kernel_gs_base;
356 u64 sysenter_cs;
357 u64 sysenter_esp;
358 u64 sysenter_eip;
359 u64 cr2;
360 u8 reserved_0x248[32];
361 u64 g_pat;
362 u64 dbgctl;
363 u64 br_from;
364 u64 br_to;
365 u64 last_excp_from;
366 u64 last_excp_to;
367 u8 reserved_0x298[72];
368 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
369 } __packed;
370
371 /* Save area definition for SEV-ES and SEV-SNP guests */
372 struct sev_es_save_area {
373 struct vmcb_seg es;
374 struct vmcb_seg cs;
375 struct vmcb_seg ss;
376 struct vmcb_seg ds;
377 struct vmcb_seg fs;
378 struct vmcb_seg gs;
379 struct vmcb_seg gdtr;
380 struct vmcb_seg ldtr;
381 struct vmcb_seg idtr;
382 struct vmcb_seg tr;
383 u64 pl0_ssp;
384 u64 pl1_ssp;
385 u64 pl2_ssp;
386 u64 pl3_ssp;
387 u64 u_cet;
388 u8 reserved_0xc8[2];
389 u8 vmpl;
390 u8 cpl;
391 u8 reserved_0xcc[4];
392 u64 efer;
393 u8 reserved_0xd8[104];
394 u64 xss;
395 u64 cr4;
396 u64 cr3;
397 u64 cr0;
398 u64 dr7;
399 u64 dr6;
400 u64 rflags;
401 u64 rip;
402 u64 dr0;
403 u64 dr1;
404 u64 dr2;
405 u64 dr3;
406 u64 dr0_addr_mask;
407 u64 dr1_addr_mask;
408 u64 dr2_addr_mask;
409 u64 dr3_addr_mask;
410 u8 reserved_0x1c0[24];
411 u64 rsp;
412 u64 s_cet;
413 u64 ssp;
414 u64 isst_addr;
415 u64 rax;
416 u64 star;
417 u64 lstar;
418 u64 cstar;
419 u64 sfmask;
420 u64 kernel_gs_base;
421 u64 sysenter_cs;
422 u64 sysenter_esp;
423 u64 sysenter_eip;
424 u64 cr2;
425 u8 reserved_0x248[32];
426 u64 g_pat;
427 u64 dbgctl;
428 u64 br_from;
429 u64 br_to;
430 u64 last_excp_from;
431 u64 last_excp_to;
432 u8 reserved_0x298[80];
433 u32 pkru;
434 u32 tsc_aux;
435 u64 tsc_scale;
436 u64 tsc_offset;
437 u8 reserved_0x300[8];
438 u64 rcx;
439 u64 rdx;
440 u64 rbx;
441 u64 reserved_0x320; /* rsp already available at 0x01d8 */
442 u64 rbp;
443 u64 rsi;
444 u64 rdi;
445 u64 r8;
446 u64 r9;
447 u64 r10;
448 u64 r11;
449 u64 r12;
450 u64 r13;
451 u64 r14;
452 u64 r15;
453 u8 reserved_0x380[16];
454 u64 guest_exit_info_1;
455 u64 guest_exit_info_2;
456 u64 guest_exit_int_info;
457 u64 guest_nrip;
458 u64 sev_features;
459 u64 vintr_ctrl;
460 u64 guest_exit_code;
461 u64 virtual_tom;
462 u64 tlb_id;
463 u64 pcpu_id;
464 u64 event_inj;
465 u64 xcr0;
466 u8 reserved_0x3f0[16];
467
468 /* Floating point area */
469 u64 x87_dp;
470 u32 mxcsr;
471 u16 x87_ftw;
472 u16 x87_fsw;
473 u16 x87_fcw;
474 u16 x87_fop;
475 u16 x87_ds;
476 u16 x87_cs;
477 u64 x87_rip;
478 u8 fpreg_x87[80];
479 u8 fpreg_xmm[256];
480 u8 fpreg_ymm[256];
481 } __packed;
482
483 struct ghcb_save_area {
484 u8 reserved_0x0[203];
485 u8 cpl;
486 u8 reserved_0xcc[116];
487 u64 xss;
488 u8 reserved_0x148[24];
489 u64 dr7;
490 u8 reserved_0x168[16];
491 u64 rip;
492 u8 reserved_0x180[88];
493 u64 rsp;
494 u8 reserved_0x1e0[24];
495 u64 rax;
496 u8 reserved_0x200[264];
497 u64 rcx;
498 u64 rdx;
499 u64 rbx;
500 u8 reserved_0x320[8];
501 u64 rbp;
502 u64 rsi;
503 u64 rdi;
504 u64 r8;
505 u64 r9;
506 u64 r10;
507 u64 r11;
508 u64 r12;
509 u64 r13;
510 u64 r14;
511 u64 r15;
512 u8 reserved_0x380[16];
513 u64 sw_exit_code;
514 u64 sw_exit_info_1;
515 u64 sw_exit_info_2;
516 u64 sw_scratch;
517 u8 reserved_0x3b0[56];
518 u64 xcr0;
519 u8 valid_bitmap[16];
520 u64 x87_state_gpa;
521 } __packed;
522
523 #define GHCB_SHARED_BUF_SIZE 2032
524
525 struct ghcb {
526 struct ghcb_save_area save;
527 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
528
529 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
530
531 u8 reserved_0xff0[10];
532 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
533 u32 ghcb_usage;
534 } __packed;
535
536 struct vmcb {
537 struct vmcb_control_area control;
538 union {
539 struct vmcb_save_area save;
540
541 /*
542 * For SEV-ES VMs, the save area in the VMCB is used only to
543 * save/load host state. Guest state resides in a separate
544 * page, the aptly named VM Save Area (VMSA), that is encrypted
545 * with the guest's private key.
546 */
547 struct sev_es_save_area host_sev_es_save;
548 };
549 } __packed;
550
551 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744
552 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
553 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
554 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
555 #define EXPECTED_GHCB_SIZE PAGE_SIZE
556
557 #define BUILD_BUG_RESERVED_OFFSET(x, y) \
558 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
559
__unused_size_checks(void)560 static inline void __unused_size_checks(void)
561 {
562 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
563 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
564 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
565 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
566 BUILD_BUG_ON(offsetof(struct vmcb, save) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
567 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
568
569 /* Check offsets of reserved fields */
570
571 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
572 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
573 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
574 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
575 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
576 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
577
578 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
579 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
580 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
581 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
582 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
583 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
584 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x300);
585 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
586 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
587 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
588
589 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
590 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
591 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
592 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
593 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
594 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
595 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
596 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
597 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
598 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
599
600 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
601 }
602
603 #define SVM_CPUID_FUNC 0x8000000a
604
605 #define SVM_SELECTOR_S_SHIFT 4
606 #define SVM_SELECTOR_DPL_SHIFT 5
607 #define SVM_SELECTOR_P_SHIFT 7
608 #define SVM_SELECTOR_AVL_SHIFT 8
609 #define SVM_SELECTOR_L_SHIFT 9
610 #define SVM_SELECTOR_DB_SHIFT 10
611 #define SVM_SELECTOR_G_SHIFT 11
612
613 #define SVM_SELECTOR_TYPE_MASK (0xf)
614 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
615 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
616 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
617 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
618 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
619 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
620 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
621
622 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
623 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
624 #define SVM_SELECTOR_CODE_MASK (1 << 3)
625
626 #define SVM_EVTINJ_VEC_MASK 0xff
627
628 #define SVM_EVTINJ_TYPE_SHIFT 8
629 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
630
631 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
632 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
633 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
634 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
635
636 #define SVM_EVTINJ_VALID (1 << 31)
637 #define SVM_EVTINJ_VALID_ERR (1 << 11)
638
639 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
640 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
641
642 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
643 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
644 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
645 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
646
647 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
648 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
649
650 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
651 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
652 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
653
654 #define SVM_EXITINFO_REG_MASK 0x0F
655
656 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
657
658 /* GHCB Accessor functions */
659
660 #define GHCB_BITMAP_IDX(field) \
661 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
662
663 #define DEFINE_GHCB_ACCESSORS(field) \
664 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
665 { \
666 return test_bit(GHCB_BITMAP_IDX(field), \
667 (unsigned long *)&ghcb->save.valid_bitmap); \
668 } \
669 \
670 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
671 { \
672 return ghcb->save.field; \
673 } \
674 \
675 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
676 { \
677 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
678 } \
679 \
680 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
681 { \
682 __set_bit(GHCB_BITMAP_IDX(field), \
683 (unsigned long *)&ghcb->save.valid_bitmap); \
684 ghcb->save.field = value; \
685 }
686
687 DEFINE_GHCB_ACCESSORS(cpl)
688 DEFINE_GHCB_ACCESSORS(rip)
689 DEFINE_GHCB_ACCESSORS(rsp)
690 DEFINE_GHCB_ACCESSORS(rax)
691 DEFINE_GHCB_ACCESSORS(rcx)
692 DEFINE_GHCB_ACCESSORS(rdx)
693 DEFINE_GHCB_ACCESSORS(rbx)
694 DEFINE_GHCB_ACCESSORS(rbp)
695 DEFINE_GHCB_ACCESSORS(rsi)
696 DEFINE_GHCB_ACCESSORS(rdi)
697 DEFINE_GHCB_ACCESSORS(r8)
698 DEFINE_GHCB_ACCESSORS(r9)
699 DEFINE_GHCB_ACCESSORS(r10)
700 DEFINE_GHCB_ACCESSORS(r11)
701 DEFINE_GHCB_ACCESSORS(r12)
702 DEFINE_GHCB_ACCESSORS(r13)
703 DEFINE_GHCB_ACCESSORS(r14)
704 DEFINE_GHCB_ACCESSORS(r15)
705 DEFINE_GHCB_ACCESSORS(sw_exit_code)
706 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
707 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
708 DEFINE_GHCB_ACCESSORS(sw_scratch)
709 DEFINE_GHCB_ACCESSORS(xcr0)
710 DEFINE_GHCB_ACCESSORS(xss)
711
712 #endif
713