| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt6795.dtsi | 12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
447 gce: mailbox@10212000 { label
448 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
452 clock-names = "gce";
727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
728 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
739 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
749 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
[all …]
|
| H A D | mt8173.dtsi | 14 #include <dt-bindings/gce/mt8173-gce.h>
634 gce: mailbox@10212000 { label
635 compatible = "mediatek,mt8173-gce";
639 clock-names = "gce";
1013 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1014 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1110 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
[all …]
|
| H A D | mt8195.dtsi | 9 #include <dt-bindings/gce/mt8195-gce.h>
919 compatible = "mediatek,mt8195-gce";
927 compatible = "mediatek,mt8195-gce";
2073 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
2079 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2080 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2097 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2104 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2111 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2119 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
|
| H A D | mt8188.dtsi | 11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
1371 compatible = "mediatek,mt8188-gce";
1379 compatible = "mediatek,mt8188-gce";
2271 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2272 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2281 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2288 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2297 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2304 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2305 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
[all …]
|
| H A D | mt8183.dtsi | 9 #include <dt-bindings/gce/mt8183-gce.h>
1065 gce: mailbox@10238000 { label
1066 compatible = "mediatek,mt8183-gce";
1071 clock-names = "gce";
1667 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1668 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1669 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1691 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
1697 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
[all …]
|
| H A D | mt8192.dtsi | 9 #include <dt-bindings/gce/mt8192-gce.h>
744 gce: mailbox@10228000 { label
745 compatible = "mediatek,mt8192-gce";
750 clock-names = "gce";
1457 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1458 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1459 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1467 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1468 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1512 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
|
| H A D | mt8186.dtsi | 8 #include <dt-bindings/gce/mt8186-gce.h>
1145 gce: mailbox@1022c000 { label
1146 compatible = "mediatek,mt8186-gce";
1149 clock-names = "gce";
1775 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1776 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1777 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1785 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1786 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1828 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
[all …]
|
| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_psfp.c | 139 const struct sparx5_psfp_gce *gce; in sparx5_psfp_sg_set() local
171 gce = &sg->gce[i]; in sparx5_psfp_sg_set()
172 ips = sparx5_psfp_ipv_to_ips(gce->ipv); in sparx5_psfp_sg_set()
174 accum_time_interval += gce->interval; in sparx5_psfp_sg_set()
177 ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(gce->gate_state), in sparx5_psfp_sg_set()
185 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); in sparx5_psfp_sg_set()
|
| H A D | sparx5_tc_flower.c | 736 sg->gce[i].gate_state = !!act->gate.entries[i].gate_state; in sparx5_tc_flower_parse_act_gate()
737 sg->gce[i].interval = act->gate.entries[i].interval; in sparx5_tc_flower_parse_act_gate()
738 sg->gce[i].ipv = act->gate.entries[i].ipv; in sparx5_tc_flower_parse_act_gate()
739 sg->gce[i].maxoctets = act->gate.entries[i].maxoctets; in sparx5_tc_flower_parse_act_gate()
796 sg->gce[0].gate_state = 1; in sparx5_tc_flower_psfp_setup()
797 sg->gce[0].interval = SPX5_PSFP_SG_CYCLE_TIME_DEFAULT; in sparx5_tc_flower_psfp_setup()
798 sg->gce[0].ipv = 0; in sparx5_tc_flower_psfp_setup()
799 sg->gce[0].maxoctets = 0; /* Disabled */ in sparx5_tc_flower_psfp_setup()
|
| H A D | sparx5_main.h | 675 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; member
|
| /linux/drivers/net/ethernet/freescale/enetc/ |
| H A D | enetc_qos.c | 54 struct gce *gce; in enetc_setup_taprio() local
86 gce = (struct gce *)(gcl_data + 1); in enetc_setup_taprio()
99 struct gce *temp_gce = gce + i; in enetc_setup_taprio()
|
| H A D | enetc_hw.h | 821 struct gce { struct
833 struct gce entry[]; argument
|
| /linux/Documentation/filesystems/ |
| H A D | fscrypt.rst | 1587 much longer to run; so also consider using `gce-xfstests
1588 <https://github.com/tytso/xfstests-bld/blob/master/Documentation/gce-xfstests.md>`_
1591 gce-xfstests -c ext4/encrypt,f2fs/encrypt -g auto
1592 gce-xfstests -c ext4/encrypt,f2fs/encrypt -g auto -m inlinecrypt
|