1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2025 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45 #define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL 46 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL 47 #define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL 48 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL 49 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 50 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 51 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 52 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 53 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 54 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 55 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 56 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 57 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 58 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 59 60 61 /* tlv (size:64b/8B) */ 62 struct tlv { 63 __le16 cmd_discr; 64 u8 reserved_8b; 65 u8 flags; 66 #define TLV_FLAGS_MORE 0x1UL 67 #define TLV_FLAGS_MORE_LAST 0x0UL 68 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 69 #define TLV_FLAGS_REQUIRED 0x2UL 70 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 71 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 72 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 73 __le16 tlv_type; 74 __le16 length; 75 }; 76 77 /* input (size:128b/16B) */ 78 struct input { 79 __le16 req_type; 80 __le16 cmpl_ring; 81 __le16 seq_id; 82 __le16 target_id; 83 __le64 resp_addr; 84 }; 85 86 /* output (size:64b/8B) */ 87 struct output { 88 __le16 error_code; 89 __le16 req_type; 90 __le16 seq_id; 91 __le16 resp_len; 92 }; 93 94 /* hwrm_short_input (size:128b/16B) */ 95 struct hwrm_short_input { 96 __le16 req_type; 97 __le16 signature; 98 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 99 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 100 __le16 target_id; 101 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 102 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 103 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 104 __le16 size; 105 __le64 req_addr; 106 }; 107 108 /* cmd_nums (size:64b/8B) */ 109 struct cmd_nums { 110 __le16 req_type; 111 #define HWRM_VER_GET 0x0UL 112 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 113 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 114 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 115 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 116 #define HWRM_FUNC_VF_CFG 0xfUL 117 #define HWRM_RESERVED1 0x10UL 118 #define HWRM_FUNC_RESET 0x11UL 119 #define HWRM_FUNC_GETFID 0x12UL 120 #define HWRM_FUNC_VF_ALLOC 0x13UL 121 #define HWRM_FUNC_VF_FREE 0x14UL 122 #define HWRM_FUNC_QCAPS 0x15UL 123 #define HWRM_FUNC_QCFG 0x16UL 124 #define HWRM_FUNC_CFG 0x17UL 125 #define HWRM_FUNC_QSTATS 0x18UL 126 #define HWRM_FUNC_CLR_STATS 0x19UL 127 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 128 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 129 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 130 #define HWRM_FUNC_DRV_RGTR 0x1dUL 131 #define HWRM_FUNC_DRV_QVER 0x1eUL 132 #define HWRM_FUNC_BUF_RGTR 0x1fUL 133 #define HWRM_PORT_PHY_CFG 0x20UL 134 #define HWRM_PORT_MAC_CFG 0x21UL 135 #define HWRM_PORT_TS_QUERY 0x22UL 136 #define HWRM_PORT_QSTATS 0x23UL 137 #define HWRM_PORT_LPBK_QSTATS 0x24UL 138 #define HWRM_PORT_CLR_STATS 0x25UL 139 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 140 #define HWRM_PORT_PHY_QCFG 0x27UL 141 #define HWRM_PORT_MAC_QCFG 0x28UL 142 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 143 #define HWRM_PORT_PHY_QCAPS 0x2aUL 144 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 145 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 146 #define HWRM_PORT_LED_CFG 0x2dUL 147 #define HWRM_PORT_LED_QCFG 0x2eUL 148 #define HWRM_PORT_LED_QCAPS 0x2fUL 149 #define HWRM_QUEUE_QPORTCFG 0x30UL 150 #define HWRM_QUEUE_QCFG 0x31UL 151 #define HWRM_QUEUE_CFG 0x32UL 152 #define HWRM_FUNC_VLAN_CFG 0x33UL 153 #define HWRM_FUNC_VLAN_QCFG 0x34UL 154 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 155 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 156 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 157 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 158 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 159 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 160 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 161 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 162 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 163 #define HWRM_VNIC_ALLOC 0x40UL 164 #define HWRM_VNIC_FREE 0x41UL 165 #define HWRM_VNIC_CFG 0x42UL 166 #define HWRM_VNIC_QCFG 0x43UL 167 #define HWRM_VNIC_TPA_CFG 0x44UL 168 #define HWRM_VNIC_TPA_QCFG 0x45UL 169 #define HWRM_VNIC_RSS_CFG 0x46UL 170 #define HWRM_VNIC_RSS_QCFG 0x47UL 171 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 172 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 173 #define HWRM_VNIC_QCAPS 0x4aUL 174 #define HWRM_VNIC_UPDATE 0x4bUL 175 #define HWRM_RING_ALLOC 0x50UL 176 #define HWRM_RING_FREE 0x51UL 177 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 178 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 179 #define HWRM_RING_AGGINT_QCAPS 0x54UL 180 #define HWRM_RING_SCHQ_ALLOC 0x55UL 181 #define HWRM_RING_SCHQ_CFG 0x56UL 182 #define HWRM_RING_SCHQ_FREE 0x57UL 183 #define HWRM_RING_RESET 0x5eUL 184 #define HWRM_RING_GRP_ALLOC 0x60UL 185 #define HWRM_RING_GRP_FREE 0x61UL 186 #define HWRM_RING_CFG 0x62UL 187 #define HWRM_RING_QCFG 0x63UL 188 #define HWRM_RESERVED5 0x64UL 189 #define HWRM_RESERVED6 0x65UL 190 #define HWRM_PORT_ADSM_QSTATES 0x66UL 191 #define HWRM_PORT_EVENTS_LOG 0x67UL 192 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 193 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 194 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 195 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 196 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 197 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 198 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 199 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 200 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 201 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 202 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 203 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 204 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 205 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 206 #define HWRM_QUEUE_QCAPS 0x8cUL 207 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 208 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 209 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 210 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 211 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 212 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 213 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 214 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 215 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 216 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 217 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 218 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 219 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 220 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 221 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 222 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 223 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 224 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 225 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 226 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 227 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 228 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 229 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 230 #define HWRM_STAT_CTX_ALLOC 0xb0UL 231 #define HWRM_STAT_CTX_FREE 0xb1UL 232 #define HWRM_STAT_CTX_QUERY 0xb2UL 233 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 234 #define HWRM_PORT_QSTATS_EXT 0xb4UL 235 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 236 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 237 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 238 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 239 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 240 #define HWRM_PORT_QSTATS_EXT_PFC_ADV 0xbaUL 241 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 242 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 243 #define HWRM_PORT_ECN_QSTATS 0xbdUL 244 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 245 #define HWRM_FW_LIVEPATCH 0xbfUL 246 #define HWRM_FW_RESET 0xc0UL 247 #define HWRM_FW_QSTATUS 0xc1UL 248 #define HWRM_FW_HEALTH_CHECK 0xc2UL 249 #define HWRM_FW_SYNC 0xc3UL 250 #define HWRM_FW_STATE_QCAPS 0xc4UL 251 #define HWRM_FW_STATE_QUIESCE 0xc5UL 252 #define HWRM_FW_STATE_BACKUP 0xc6UL 253 #define HWRM_FW_STATE_RESTORE 0xc7UL 254 #define HWRM_FW_SET_TIME 0xc8UL 255 #define HWRM_FW_GET_TIME 0xc9UL 256 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 257 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 258 #define HWRM_FW_IPC_MAILBOX 0xccUL 259 #define HWRM_FW_ECN_CFG 0xcdUL 260 #define HWRM_FW_ECN_QCFG 0xceUL 261 #define HWRM_FW_SECURE_CFG 0xcfUL 262 #define HWRM_EXEC_FWD_RESP 0xd0UL 263 #define HWRM_REJECT_FWD_RESP 0xd1UL 264 #define HWRM_FWD_RESP 0xd2UL 265 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 266 #define HWRM_OEM_CMD 0xd4UL 267 #define HWRM_PORT_PRBS_TEST 0xd5UL 268 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 269 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 270 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 271 #define HWRM_PORT_DSC_DUMP 0xd9UL 272 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 273 #define HWRM_PORT_EP_TX_CFG 0xdbUL 274 #define HWRM_PORT_CFG 0xdcUL 275 #define HWRM_PORT_QCFG 0xddUL 276 #define HWRM_PORT_DSC_COLLECTION 0xdeUL 277 #define HWRM_PORT_MAC_QCAPS 0xdfUL 278 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 279 #define HWRM_REG_POWER_QUERY 0xe1UL 280 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 281 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 282 #define HWRM_MONITOR_PAX_HISTOGRAM_START 0xe4UL 283 #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL 284 #define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL 285 #define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL 286 #define HWRM_MONITOR_DEVICE_HEALTH 0xe8UL 287 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 288 #define HWRM_WOL_FILTER_FREE 0xf1UL 289 #define HWRM_WOL_FILTER_QCFG 0xf2UL 290 #define HWRM_WOL_REASON_QCFG 0xf3UL 291 #define HWRM_CFA_METER_QCAPS 0xf4UL 292 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 293 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 294 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 295 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 296 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 297 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 298 #define HWRM_CFA_VFR_ALLOC 0xfdUL 299 #define HWRM_CFA_VFR_FREE 0xfeUL 300 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 301 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 302 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 303 #define HWRM_CFA_FLOW_ALLOC 0x103UL 304 #define HWRM_CFA_FLOW_FREE 0x104UL 305 #define HWRM_CFA_FLOW_FLUSH 0x105UL 306 #define HWRM_CFA_FLOW_STATS 0x106UL 307 #define HWRM_CFA_FLOW_INFO 0x107UL 308 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 309 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 310 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 311 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 312 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 313 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 314 #define HWRM_CFA_PAIR_FREE 0x10eUL 315 #define HWRM_CFA_PAIR_INFO 0x10fUL 316 #define HWRM_FW_IPC_MSG 0x110UL 317 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 318 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 319 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 320 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 321 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 322 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 323 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 324 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 325 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 326 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 327 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 328 #define HWRM_CFA_COUNTER_CFG 0x11cUL 329 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 330 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 331 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 332 #define HWRM_CFA_EEM_QCAPS 0x120UL 333 #define HWRM_CFA_EEM_CFG 0x121UL 334 #define HWRM_CFA_EEM_QCFG 0x122UL 335 #define HWRM_CFA_EEM_OP 0x123UL 336 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 337 #define HWRM_CFA_TFLIB 0x125UL 338 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 339 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 340 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 341 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 342 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 343 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 344 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 345 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 346 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 347 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 348 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 349 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 350 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 351 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 352 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 353 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 354 #define HWRM_ENGINE_QG_QUERY 0x13dUL 355 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 356 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 357 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 358 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 359 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 360 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 361 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 362 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 363 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 364 #define HWRM_ENGINE_SG_QUERY 0x147UL 365 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 366 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 367 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 368 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 369 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 370 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 371 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 372 #define HWRM_ENGINE_STATS_QUERY 0x157UL 373 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 374 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 375 #define HWRM_ENGINE_RQ_FREE 0x15fUL 376 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 377 #define HWRM_ENGINE_CQ_FREE 0x161UL 378 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 379 #define HWRM_ENGINE_NQ_FREE 0x163UL 380 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 381 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 382 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 383 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 384 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 385 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 386 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 387 #define HWRM_FUNC_VF_BW_CFG 0x195UL 388 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 389 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 390 #define HWRM_FUNC_QSTATS_EXT 0x198UL 391 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 392 #define HWRM_FUNC_SPD_CFG 0x19aUL 393 #define HWRM_FUNC_SPD_QCFG 0x19bUL 394 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 395 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 396 #define HWRM_FUNC_PTP_CFG 0x19eUL 397 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 398 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 399 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 400 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 401 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 402 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 403 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 404 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 405 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 406 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 407 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 408 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 409 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 410 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 411 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 412 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 413 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 414 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 415 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 416 #define HWRM_FUNC_LAG_FREE 0x1b2UL 417 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 418 #define HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY 0x1c3UL 419 #define HWRM_FUNC_TTX_PACING_RATE_QUERY 0x1c4UL 420 #define HWRM_SELFTEST_QLIST 0x200UL 421 #define HWRM_SELFTEST_EXEC 0x201UL 422 #define HWRM_SELFTEST_IRQ 0x202UL 423 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 424 #define HWRM_PCIE_QSTATS 0x204UL 425 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 426 #define HWRM_MFG_TIMERS_QUERY 0x206UL 427 #define HWRM_MFG_OTP_CFG 0x207UL 428 #define HWRM_MFG_OTP_QCFG 0x208UL 429 #define HWRM_MFG_HDMA_TEST 0x209UL 430 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 431 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 432 #define HWRM_MFG_SOC_IMAGE 0x20cUL 433 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 434 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 435 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 436 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 437 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 438 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 439 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 440 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 441 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 442 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 443 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 444 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 445 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 446 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 447 #define HWRM_MFG_TESTS 0x21bUL 448 #define HWRM_MFG_WRITE_CERT_NVM 0x21cUL 449 #define HWRM_PORT_POE_CFG 0x230UL 450 #define HWRM_PORT_POE_QCFG 0x231UL 451 #define HWRM_PORT_PHY_FDRSTAT 0x232UL 452 #define HWRM_UDCC_QCAPS 0x258UL 453 #define HWRM_UDCC_CFG 0x259UL 454 #define HWRM_UDCC_QCFG 0x25aUL 455 #define HWRM_UDCC_SESSION_CFG 0x25bUL 456 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 457 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 458 #define HWRM_UDCC_COMP_CFG 0x25eUL 459 #define HWRM_UDCC_COMP_QCFG 0x25fUL 460 #define HWRM_UDCC_COMP_QUERY 0x260UL 461 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL 462 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL 463 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL 464 #define HWRM_QUEUE_ADPTV_QOS_RX_QCFG 0x264UL 465 #define HWRM_QUEUE_ADPTV_QOS_TX_QCFG 0x265UL 466 #define HWRM_TF 0x2bcUL 467 #define HWRM_TF_VERSION_GET 0x2bdUL 468 #define HWRM_TF_SESSION_OPEN 0x2c6UL 469 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 470 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 471 #define HWRM_TF_SESSION_CLOSE 0x2caUL 472 #define HWRM_TF_SESSION_QCFG 0x2cbUL 473 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 474 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 475 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 476 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 477 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 478 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 479 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 480 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 481 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 482 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 483 #define HWRM_TF_EM_INSERT 0x2eaUL 484 #define HWRM_TF_EM_DELETE 0x2ebUL 485 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 486 #define HWRM_TF_EM_MOVE 0x2edUL 487 #define HWRM_TF_TCAM_SET 0x2f8UL 488 #define HWRM_TF_TCAM_GET 0x2f9UL 489 #define HWRM_TF_TCAM_MOVE 0x2faUL 490 #define HWRM_TF_TCAM_FREE 0x2fbUL 491 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 492 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 493 #define HWRM_TF_IF_TBL_SET 0x2feUL 494 #define HWRM_TF_IF_TBL_GET 0x2ffUL 495 #define HWRM_TF_RESC_USAGE_SET 0x300UL 496 #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 497 #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 498 #define HWRM_TF_TBL_TYPE_FREE 0x303UL 499 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 500 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 501 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 502 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 503 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 504 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 505 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 506 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 507 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 508 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 509 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 510 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 511 #define HWRM_TFC_IDENT_FREE 0x38cUL 512 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 513 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 514 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 515 #define HWRM_TFC_IDX_TBL_GET 0x390UL 516 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 517 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 518 #define HWRM_TFC_TCAM_SET 0x393UL 519 #define HWRM_TFC_TCAM_GET 0x394UL 520 #define HWRM_TFC_TCAM_ALLOC 0x395UL 521 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 522 #define HWRM_TFC_TCAM_FREE 0x397UL 523 #define HWRM_TFC_IF_TBL_SET 0x398UL 524 #define HWRM_TFC_IF_TBL_GET 0x399UL 525 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 526 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 527 #define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL 528 #define HWRM_TFC_TCAM_PRI_UPDATE 0x39dUL 529 #define HWRM_TFC_HOT_UPGRADE_PROCESS 0x3a0UL 530 #define HWRM_SV 0x400UL 531 #define HWRM_DBG_SERDES_TEST 0xff0eUL 532 #define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL 533 #define HWRM_DBG_READ_DIRECT 0xff10UL 534 #define HWRM_DBG_READ_INDIRECT 0xff11UL 535 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 536 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 537 #define HWRM_DBG_DUMP 0xff14UL 538 #define HWRM_DBG_ERASE_NVM 0xff15UL 539 #define HWRM_DBG_CFG 0xff16UL 540 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 541 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 542 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 543 #define HWRM_DBG_FW_CLI 0xff1aUL 544 #define HWRM_DBG_I2C_CMD 0xff1bUL 545 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 546 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 547 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 548 #define HWRM_DBG_DRV_TRACE 0xff1fUL 549 #define HWRM_DBG_QCAPS 0xff20UL 550 #define HWRM_DBG_QCFG 0xff21UL 551 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 552 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 553 #define HWRM_DBG_USEQ_FREE 0xff24UL 554 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 555 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 556 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 557 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 558 #define HWRM_DBG_USEQ_RUN 0xff29UL 559 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 560 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 561 #define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL 562 #define HWRM_DBG_PTRACE 0xff2dUL 563 #define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL 564 #define HWRM_DBG_TOKEN_QUERY_AUTH_IDS 0xff2fUL 565 #define HWRM_DBG_TOKEN_CFG 0xff30UL 566 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 567 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 568 #define HWRM_NVM_DEFRAG 0xffecUL 569 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 570 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 571 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 572 #define HWRM_NVM_FLUSH 0xfff0UL 573 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 574 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 575 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 576 #define HWRM_NVM_MODIFY 0xfff4UL 577 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 578 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 579 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 580 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 581 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 582 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 583 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 584 #define HWRM_NVM_RAW_DUMP 0xfffcUL 585 #define HWRM_NVM_READ 0xfffdUL 586 #define HWRM_NVM_WRITE 0xfffeUL 587 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 588 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 589 __le16 unused_0[3]; 590 }; 591 592 /* ret_codes (size:64b/8B) */ 593 struct ret_codes { 594 __le16 error_code; 595 #define HWRM_ERR_CODE_SUCCESS 0x0UL 596 #define HWRM_ERR_CODE_FAIL 0x1UL 597 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 598 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 599 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 600 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 601 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 602 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 603 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 604 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 605 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 606 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 607 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 608 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 609 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 610 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 611 #define HWRM_ERR_CODE_BUSY 0x10UL 612 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 613 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 614 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 615 #define HWRM_ERR_CODE_SECURE_SOC_ERROR 0x14UL 616 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 617 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 618 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 619 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 620 __le16 unused_0[3]; 621 }; 622 623 /* hwrm_err_output (size:128b/16B) */ 624 struct hwrm_err_output { 625 __le16 error_code; 626 __le16 req_type; 627 __le16 seq_id; 628 __le16 resp_len; 629 __le32 opaque_0; 630 __le16 opaque_1; 631 u8 cmd_err; 632 u8 valid; 633 }; 634 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 635 #define HWRM_MAX_REQ_LEN 128 636 #define HWRM_MAX_RESP_LEN 704 637 #define HW_HASH_INDEX_SIZE 0x80 638 #define HW_HASH_KEY_SIZE 40 639 #define HWRM_RESP_VALID_KEY 1 640 #define HWRM_TARGET_ID_BONO 0xFFF8 641 #define HWRM_TARGET_ID_KONG 0xFFF9 642 #define HWRM_TARGET_ID_APE 0xFFFA 643 #define HWRM_TARGET_ID_TOOLS 0xFFFD 644 #define HWRM_VERSION_MAJOR 1 645 #define HWRM_VERSION_MINOR 10 646 #define HWRM_VERSION_UPDATE 3 647 #define HWRM_VERSION_RSVD 151 648 #define HWRM_VERSION_STR "1.10.3.151" 649 650 /* hwrm_ver_get_input (size:192b/24B) */ 651 struct hwrm_ver_get_input { 652 __le16 req_type; 653 __le16 cmpl_ring; 654 __le16 seq_id; 655 __le16 target_id; 656 __le64 resp_addr; 657 u8 hwrm_intf_maj; 658 u8 hwrm_intf_min; 659 u8 hwrm_intf_upd; 660 u8 unused_0[5]; 661 }; 662 663 /* hwrm_ver_get_output (size:1408b/176B) */ 664 struct hwrm_ver_get_output { 665 __le16 error_code; 666 __le16 req_type; 667 __le16 seq_id; 668 __le16 resp_len; 669 u8 hwrm_intf_maj_8b; 670 u8 hwrm_intf_min_8b; 671 u8 hwrm_intf_upd_8b; 672 u8 hwrm_intf_rsvd_8b; 673 u8 hwrm_fw_maj_8b; 674 u8 hwrm_fw_min_8b; 675 u8 hwrm_fw_bld_8b; 676 u8 hwrm_fw_rsvd_8b; 677 u8 mgmt_fw_maj_8b; 678 u8 mgmt_fw_min_8b; 679 u8 mgmt_fw_bld_8b; 680 u8 mgmt_fw_rsvd_8b; 681 u8 netctrl_fw_maj_8b; 682 u8 netctrl_fw_min_8b; 683 u8 netctrl_fw_bld_8b; 684 u8 netctrl_fw_rsvd_8b; 685 __le32 dev_caps_cfg; 686 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 687 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 688 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 689 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 690 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 691 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 692 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 693 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 694 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 695 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 696 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 697 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 698 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 699 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 700 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 701 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 702 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL 703 #define VER_GET_RESP_DEV_CAPS_CFG_DEBUG_TOKEN_SUPPORTED 0x20000UL 704 u8 roce_fw_maj_8b; 705 u8 roce_fw_min_8b; 706 u8 roce_fw_bld_8b; 707 u8 roce_fw_rsvd_8b; 708 char hwrm_fw_name[16]; 709 char mgmt_fw_name[16]; 710 char netctrl_fw_name[16]; 711 char active_pkg_name[16]; 712 char roce_fw_name[16]; 713 __le16 chip_num; 714 u8 chip_rev; 715 u8 chip_metal; 716 u8 chip_bond_id; 717 u8 chip_platform_type; 718 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 719 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 720 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 721 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 722 __le16 max_req_win_len; 723 __le16 max_resp_len; 724 __le16 def_req_timeout; 725 u8 flags; 726 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 727 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 728 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 729 u8 unused_0[2]; 730 u8 always_1; 731 __le16 hwrm_intf_major; 732 __le16 hwrm_intf_minor; 733 __le16 hwrm_intf_build; 734 __le16 hwrm_intf_patch; 735 __le16 hwrm_fw_major; 736 __le16 hwrm_fw_minor; 737 __le16 hwrm_fw_build; 738 __le16 hwrm_fw_patch; 739 __le16 mgmt_fw_major; 740 __le16 mgmt_fw_minor; 741 __le16 mgmt_fw_build; 742 __le16 mgmt_fw_patch; 743 __le16 netctrl_fw_major; 744 __le16 netctrl_fw_minor; 745 __le16 netctrl_fw_build; 746 __le16 netctrl_fw_patch; 747 __le16 roce_fw_major; 748 __le16 roce_fw_minor; 749 __le16 roce_fw_build; 750 __le16 roce_fw_patch; 751 __le16 max_ext_req_len; 752 __le16 max_req_timeout; 753 u8 unused_1[3]; 754 u8 valid; 755 }; 756 757 /* eject_cmpl (size:128b/16B) */ 758 struct eject_cmpl { 759 __le16 type; 760 #define EJECT_CMPL_TYPE_MASK 0x3fUL 761 #define EJECT_CMPL_TYPE_SFT 0 762 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 763 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 764 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 765 #define EJECT_CMPL_FLAGS_SFT 6 766 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 767 __le16 len; 768 __le32 opaque; 769 __le16 v; 770 #define EJECT_CMPL_V 0x1UL 771 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 772 #define EJECT_CMPL_ERRORS_SFT 1 773 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 774 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 775 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 776 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 777 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 778 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 779 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 780 __le16 reserved16; 781 __le32 unused_2; 782 }; 783 784 /* hwrm_cmpl (size:128b/16B) */ 785 struct hwrm_cmpl { 786 __le16 type; 787 #define CMPL_TYPE_MASK 0x3fUL 788 #define CMPL_TYPE_SFT 0 789 #define CMPL_TYPE_HWRM_DONE 0x20UL 790 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 791 __le16 sequence_id; 792 __le32 unused_1; 793 __le32 v; 794 #define CMPL_V 0x1UL 795 __le32 unused_3; 796 }; 797 798 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 799 struct hwrm_fwd_req_cmpl { 800 __le16 req_len_type; 801 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 802 #define FWD_REQ_CMPL_TYPE_SFT 0 803 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 804 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 805 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 806 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 807 __le16 source_id; 808 __le32 unused0; 809 __le32 req_buf_addr_v[2]; 810 #define FWD_REQ_CMPL_V 0x1UL 811 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 812 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 813 }; 814 815 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 816 struct hwrm_fwd_resp_cmpl { 817 __le16 type; 818 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 819 #define FWD_RESP_CMPL_TYPE_SFT 0 820 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 821 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 822 __le16 source_id; 823 __le16 resp_len; 824 __le16 unused_1; 825 __le32 resp_buf_addr_v[2]; 826 #define FWD_RESP_CMPL_V 0x1UL 827 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 828 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 829 }; 830 831 /* hwrm_async_event_cmpl (size:128b/16B) */ 832 struct hwrm_async_event_cmpl { 833 __le16 type; 834 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 835 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 836 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 837 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 838 __le16 event_id; 839 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 845 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 846 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 847 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 848 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 849 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 850 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 851 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 852 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 853 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 854 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 855 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 856 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 857 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 858 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 859 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 860 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 861 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 862 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 863 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 864 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 865 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 866 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 867 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 868 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 869 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 870 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 871 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 872 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 873 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 874 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 875 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 876 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 877 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 878 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 879 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 880 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 881 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 882 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 883 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 884 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL 885 #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL 886 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL 887 #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL 888 #define ASYNC_EVENT_CMPL_EVENT_ID_ADPTV_QOS 0x51UL 889 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x52UL 890 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 891 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 892 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 893 __le32 event_data2; 894 u8 opaque_v; 895 #define ASYNC_EVENT_CMPL_V 0x1UL 896 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 897 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 898 u8 timestamp_lo; 899 __le16 timestamp_hi; 900 __le32 event_data1; 901 }; 902 903 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 904 struct hwrm_async_event_cmpl_link_status_change { 905 __le16 type; 906 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 907 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 908 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 909 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 910 __le16 event_id; 911 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 912 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 913 __le32 event_data2; 914 u8 opaque_v; 915 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 916 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 917 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 918 u8 timestamp_lo; 919 __le16 timestamp_hi; 920 __le32 event_data1; 921 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 922 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 923 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 924 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 925 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 926 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 927 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 928 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 929 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 930 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 931 }; 932 933 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 934 struct hwrm_async_event_cmpl_port_conn_not_allowed { 935 __le16 type; 936 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 937 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 938 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 939 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 940 __le16 event_id; 941 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 942 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 943 __le32 event_data2; 944 u8 opaque_v; 945 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 946 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 947 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 948 u8 timestamp_lo; 949 __le16 timestamp_hi; 950 __le32 event_data1; 951 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 952 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 953 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 954 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 955 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 956 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 957 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 958 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 959 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 960 }; 961 962 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 963 struct hwrm_async_event_cmpl_link_speed_cfg_change { 964 __le16 type; 965 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 966 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 967 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 968 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 969 __le16 event_id; 970 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 971 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 972 __le32 event_data2; 973 u8 opaque_v; 974 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 975 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 976 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 977 u8 timestamp_lo; 978 __le16 timestamp_hi; 979 __le32 event_data1; 980 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 981 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 982 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 983 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 984 }; 985 986 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 987 struct hwrm_async_event_cmpl_reset_notify { 988 __le16 type; 989 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 990 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 991 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 992 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 993 __le16 event_id; 994 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 995 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 996 __le32 event_data2; 997 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 998 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 999 u8 opaque_v; 1000 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 1001 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 1002 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 1003 u8 timestamp_lo; 1004 __le16 timestamp_hi; 1005 __le32 event_data1; 1006 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 1007 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 1008 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 1009 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 1010 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 1011 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 1012 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 1013 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 1014 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 1015 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 1016 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 1017 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 1018 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 1019 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 1020 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 1021 }; 1022 1023 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 1024 struct hwrm_async_event_cmpl_error_recovery { 1025 __le16 type; 1026 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 1027 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 1028 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1029 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 1030 __le16 event_id; 1031 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 1032 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 1033 __le32 event_data2; 1034 u8 opaque_v; 1035 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 1036 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 1037 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 1038 u8 timestamp_lo; 1039 __le16 timestamp_hi; 1040 __le32 event_data1; 1041 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 1042 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 1043 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 1044 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 1045 }; 1046 1047 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1048 struct hwrm_async_event_cmpl_ring_monitor_msg { 1049 __le16 type; 1050 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1051 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1052 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1053 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1054 __le16 event_id; 1055 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1056 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1057 __le32 event_data2; 1058 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1059 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1060 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1061 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1062 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1063 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1064 u8 opaque_v; 1065 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1066 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1067 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1068 u8 timestamp_lo; 1069 __le16 timestamp_hi; 1070 __le32 event_data1; 1071 }; 1072 1073 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1074 struct hwrm_async_event_cmpl_vf_cfg_change { 1075 __le16 type; 1076 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1077 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1078 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1079 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1080 __le16 event_id; 1081 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1082 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1083 __le32 event_data2; 1084 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1085 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1086 u8 opaque_v; 1087 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1088 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1089 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1090 u8 timestamp_lo; 1091 __le16 timestamp_hi; 1092 __le32 event_data1; 1093 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1094 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1095 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1096 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1097 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1098 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1099 }; 1100 1101 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1102 struct hwrm_async_event_cmpl_default_vnic_change { 1103 __le16 type; 1104 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1105 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1106 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1107 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1108 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1109 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1110 __le16 event_id; 1111 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1112 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1113 __le32 event_data2; 1114 u8 opaque_v; 1115 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1116 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1117 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1118 u8 timestamp_lo; 1119 __le16 timestamp_hi; 1120 __le32 event_data1; 1121 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1122 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1123 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1124 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1125 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1126 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1127 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1128 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1129 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1130 }; 1131 1132 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1133 struct hwrm_async_event_cmpl_hw_flow_aged { 1134 __le16 type; 1135 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1136 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1137 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1138 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1139 __le16 event_id; 1140 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1141 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1142 __le32 event_data2; 1143 u8 opaque_v; 1144 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1145 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1146 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1147 u8 timestamp_lo; 1148 __le16 timestamp_hi; 1149 __le32 event_data1; 1150 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1151 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1152 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1153 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1154 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1155 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1156 }; 1157 1158 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1159 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1160 __le16 type; 1161 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1162 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1163 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1164 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1165 __le16 event_id; 1166 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1167 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1168 __le32 event_data2; 1169 u8 opaque_v; 1170 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1171 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1172 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1173 u8 timestamp_lo; 1174 __le16 timestamp_hi; 1175 __le32 event_data1; 1176 }; 1177 1178 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1179 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1180 __le16 type; 1181 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1182 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1183 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1184 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1185 __le16 event_id; 1186 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1187 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1188 __le32 event_data2; 1189 u8 opaque_v; 1190 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1191 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1192 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1193 u8 timestamp_lo; 1194 __le16 timestamp_hi; 1195 __le32 event_data1; 1196 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1197 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1198 }; 1199 1200 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1201 struct hwrm_async_event_cmpl_deferred_response { 1202 __le16 type; 1203 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1204 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1205 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1206 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1207 __le16 event_id; 1208 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1209 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1210 __le32 event_data2; 1211 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1212 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1213 u8 opaque_v; 1214 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1215 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1216 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1217 u8 timestamp_lo; 1218 __le16 timestamp_hi; 1219 __le32 event_data1; 1220 }; 1221 1222 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1223 struct hwrm_async_event_cmpl_echo_request { 1224 __le16 type; 1225 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1226 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1227 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1228 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1229 __le16 event_id; 1230 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1231 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1232 __le32 event_data2; 1233 u8 opaque_v; 1234 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1235 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1236 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1237 u8 timestamp_lo; 1238 __le16 timestamp_hi; 1239 __le32 event_data1; 1240 }; 1241 1242 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1243 struct hwrm_async_event_cmpl_phc_update { 1244 __le16 type; 1245 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1246 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1247 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1248 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1249 __le16 event_id; 1250 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1251 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1252 __le32 event_data2; 1253 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1254 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1255 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1256 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1257 u8 opaque_v; 1258 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1259 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1260 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1261 u8 timestamp_lo; 1262 __le16 timestamp_hi; 1263 __le32 event_data1; 1264 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1265 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1266 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1267 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1268 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1269 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1270 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1271 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1272 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1273 }; 1274 1275 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1276 struct hwrm_async_event_cmpl_pps_timestamp { 1277 __le16 type; 1278 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1279 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1280 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1281 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1282 __le16 event_id; 1283 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1284 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1285 __le32 event_data2; 1286 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1287 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1288 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1289 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1290 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1291 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1292 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1293 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1294 u8 opaque_v; 1295 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1296 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1297 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1298 u8 timestamp_lo; 1299 __le16 timestamp_hi; 1300 __le32 event_data1; 1301 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1302 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1303 }; 1304 1305 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1306 struct hwrm_async_event_cmpl_error_report { 1307 __le16 type; 1308 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1312 __le16 event_id; 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1315 __le32 event_data2; 1316 u8 opaque_v; 1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1320 u8 timestamp_lo; 1321 __le16 timestamp_hi; 1322 __le32 event_data1; 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1325 }; 1326 1327 /* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ 1328 struct hwrm_async_event_cmpl_dbg_buf_producer { 1329 __le16 type; 1330 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL 1331 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 1332 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1333 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 1334 __le16 event_id; 1335 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 1336 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 1337 __le32 event_data2; 1338 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL 1339 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0 1340 u8 opaque_v; 1341 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL 1342 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL 1343 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 1344 u8 timestamp_lo; 1345 __le16 timestamp_hi; 1346 __le32 event_data1; 1347 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL 1348 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 1349 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL 1350 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL 1351 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL 1352 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL 1353 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL 1354 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL 1355 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL 1356 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL 1357 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL 1358 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL 1359 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL 1360 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 1361 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 0xcUL 1362 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 1363 }; 1364 1365 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1366 struct hwrm_async_event_cmpl_hwrm_error { 1367 __le16 type; 1368 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1369 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1370 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1371 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1372 __le16 event_id; 1373 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1374 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1375 __le32 event_data2; 1376 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1377 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1378 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1379 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1380 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1381 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1382 u8 opaque_v; 1383 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1384 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1385 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1386 u8 timestamp_lo; 1387 __le16 timestamp_hi; 1388 __le32 event_data1; 1389 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1390 }; 1391 1392 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1393 struct hwrm_async_event_cmpl_error_report_base { 1394 __le16 type; 1395 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1396 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1398 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1399 __le16 event_id; 1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1402 __le32 event_data2; 1403 u8 opaque_v; 1404 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1405 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1406 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1407 u8 timestamp_lo; 1408 __le16 timestamp_hi; 1409 __le32 event_data1; 1410 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1411 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1414 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1415 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1419 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUP_UDCC_SES 0x7UL 1420 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL 1421 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL 1422 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL 1423 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 0xbUL 1424 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 1425 }; 1426 1427 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1428 struct hwrm_async_event_cmpl_error_report_pause_storm { 1429 __le16 type; 1430 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1431 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1432 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1433 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1434 __le16 event_id; 1435 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1436 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1437 __le32 event_data2; 1438 u8 opaque_v; 1439 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1440 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1441 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1442 u8 timestamp_lo; 1443 __le16 timestamp_hi; 1444 __le32 event_data1; 1445 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1446 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1447 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1448 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1449 }; 1450 1451 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1452 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1453 __le16 type; 1454 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1455 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1456 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1457 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1458 __le16 event_id; 1459 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1461 __le32 event_data2; 1462 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1463 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1464 u8 opaque_v; 1465 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1467 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1468 u8 timestamp_lo; 1469 __le16 timestamp_hi; 1470 __le32 event_data1; 1471 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1472 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1473 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1474 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1475 }; 1476 1477 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1478 struct hwrm_async_event_cmpl_error_report_nvm { 1479 __le16 type; 1480 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1481 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1482 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1483 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1484 __le16 event_id; 1485 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1486 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1487 __le32 event_data2; 1488 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1489 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1490 u8 opaque_v; 1491 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1492 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1493 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1494 u8 timestamp_lo; 1495 __le16 timestamp_hi; 1496 __le32 event_data1; 1497 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1498 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1499 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1500 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1501 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1502 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1503 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1504 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1505 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1506 }; 1507 1508 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1509 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1510 __le16 type; 1511 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1512 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1513 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1514 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1515 __le16 event_id; 1516 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1517 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1518 __le32 event_data2; 1519 u8 opaque_v; 1520 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1521 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1522 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1523 u8 timestamp_lo; 1524 __le16 timestamp_hi; 1525 __le32 event_data1; 1526 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1527 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1528 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1529 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1530 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1531 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1532 }; 1533 1534 /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1535 struct hwrm_async_event_cmpl_error_report_thermal { 1536 __le16 type; 1537 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1538 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1539 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1540 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1541 __le16 event_id; 1542 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1543 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1544 __le32 event_data2; 1545 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1546 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1547 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1548 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1549 u8 opaque_v; 1550 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1551 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1552 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1553 u8 timestamp_lo; 1554 __le16 timestamp_hi; 1555 __le32 event_data1; 1556 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1557 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1558 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1559 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1560 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1561 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1562 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1563 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1564 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1565 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1566 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1567 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1568 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1569 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1570 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1571 }; 1572 1573 /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1574 struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1575 __le16 type; 1576 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1577 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1578 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1579 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1580 __le16 event_id; 1581 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1582 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1583 __le32 event_data2; 1584 u8 opaque_v; 1585 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1586 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1587 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1588 u8 timestamp_lo; 1589 __le16 timestamp_hi; 1590 __le32 event_data1; 1591 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1592 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1593 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1594 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1595 }; 1596 1597 /* hwrm_func_reset_input (size:192b/24B) */ 1598 struct hwrm_func_reset_input { 1599 __le16 req_type; 1600 __le16 cmpl_ring; 1601 __le16 seq_id; 1602 __le16 target_id; 1603 __le64 resp_addr; 1604 __le32 enables; 1605 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1606 __le16 vf_id; 1607 u8 func_reset_level; 1608 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1609 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1610 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1611 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1612 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1613 u8 unused_0; 1614 }; 1615 1616 /* hwrm_func_reset_output (size:128b/16B) */ 1617 struct hwrm_func_reset_output { 1618 __le16 error_code; 1619 __le16 req_type; 1620 __le16 seq_id; 1621 __le16 resp_len; 1622 u8 unused_0[7]; 1623 u8 valid; 1624 }; 1625 1626 /* hwrm_func_getfid_input (size:192b/24B) */ 1627 struct hwrm_func_getfid_input { 1628 __le16 req_type; 1629 __le16 cmpl_ring; 1630 __le16 seq_id; 1631 __le16 target_id; 1632 __le64 resp_addr; 1633 __le32 enables; 1634 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1635 __le16 pci_id; 1636 u8 unused_0[2]; 1637 }; 1638 1639 /* hwrm_func_getfid_output (size:128b/16B) */ 1640 struct hwrm_func_getfid_output { 1641 __le16 error_code; 1642 __le16 req_type; 1643 __le16 seq_id; 1644 __le16 resp_len; 1645 __le16 fid; 1646 u8 unused_0[5]; 1647 u8 valid; 1648 }; 1649 1650 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1651 struct hwrm_func_vf_alloc_input { 1652 __le16 req_type; 1653 __le16 cmpl_ring; 1654 __le16 seq_id; 1655 __le16 target_id; 1656 __le64 resp_addr; 1657 __le32 enables; 1658 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1659 __le16 first_vf_id; 1660 __le16 num_vfs; 1661 }; 1662 1663 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1664 struct hwrm_func_vf_alloc_output { 1665 __le16 error_code; 1666 __le16 req_type; 1667 __le16 seq_id; 1668 __le16 resp_len; 1669 __le16 first_vf_id; 1670 u8 unused_0[5]; 1671 u8 valid; 1672 }; 1673 1674 /* hwrm_func_vf_free_input (size:192b/24B) */ 1675 struct hwrm_func_vf_free_input { 1676 __le16 req_type; 1677 __le16 cmpl_ring; 1678 __le16 seq_id; 1679 __le16 target_id; 1680 __le64 resp_addr; 1681 __le32 enables; 1682 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1683 __le16 first_vf_id; 1684 __le16 num_vfs; 1685 }; 1686 1687 /* hwrm_func_vf_free_output (size:128b/16B) */ 1688 struct hwrm_func_vf_free_output { 1689 __le16 error_code; 1690 __le16 req_type; 1691 __le16 seq_id; 1692 __le16 resp_len; 1693 u8 unused_0[7]; 1694 u8 valid; 1695 }; 1696 1697 /* hwrm_func_vf_cfg_input (size:576b/72B) */ 1698 struct hwrm_func_vf_cfg_input { 1699 __le16 req_type; 1700 __le16 cmpl_ring; 1701 __le16 seq_id; 1702 __le16 target_id; 1703 __le64 resp_addr; 1704 __le32 enables; 1705 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1706 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1707 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1708 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1709 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1710 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1711 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1712 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1713 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1714 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1715 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1716 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1717 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1718 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1719 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1720 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1721 __le16 mtu; 1722 __le16 guest_vlan; 1723 __le16 async_event_cr; 1724 u8 dflt_mac_addr[6]; 1725 __le32 flags; 1726 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1727 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1728 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1729 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1730 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1731 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1732 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1733 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1734 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1735 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1736 __le16 num_rsscos_ctxs; 1737 __le16 num_cmpl_rings; 1738 __le16 num_tx_rings; 1739 __le16 num_rx_rings; 1740 __le16 num_l2_ctxs; 1741 __le16 num_vnics; 1742 __le16 num_stat_ctxs; 1743 __le16 num_hw_ring_grps; 1744 __le32 num_ktls_tx_key_ctxs; 1745 __le32 num_ktls_rx_key_ctxs; 1746 __le16 num_msix; 1747 u8 unused[2]; 1748 __le32 num_quic_tx_key_ctxs; 1749 __le32 num_quic_rx_key_ctxs; 1750 }; 1751 1752 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1753 struct hwrm_func_vf_cfg_output { 1754 __le16 error_code; 1755 __le16 req_type; 1756 __le16 seq_id; 1757 __le16 resp_len; 1758 u8 unused_0[7]; 1759 u8 valid; 1760 }; 1761 1762 /* hwrm_func_qcaps_input (size:192b/24B) */ 1763 struct hwrm_func_qcaps_input { 1764 __le16 req_type; 1765 __le16 cmpl_ring; 1766 __le16 seq_id; 1767 __le16 target_id; 1768 __le64 resp_addr; 1769 __le16 fid; 1770 u8 unused_0[6]; 1771 }; 1772 1773 /* hwrm_func_qcaps_output (size:1152b/144B) */ 1774 struct hwrm_func_qcaps_output { 1775 __le16 error_code; 1776 __le16 req_type; 1777 __le16 seq_id; 1778 __le16 resp_len; 1779 __le16 fid; 1780 __le16 port_id; 1781 __le32 flags; 1782 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1783 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1784 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1785 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1786 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1787 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1788 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1789 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1790 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1791 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1792 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1793 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1794 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1795 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1796 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1797 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1798 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1799 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1800 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1801 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1802 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1803 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1804 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1805 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1806 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1807 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1808 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1809 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1810 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1811 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1812 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1813 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1814 u8 mac_address[6]; 1815 __le16 max_rsscos_ctx; 1816 __le16 max_cmpl_rings; 1817 __le16 max_tx_rings; 1818 __le16 max_rx_rings; 1819 __le16 max_l2_ctxs; 1820 __le16 max_vnics; 1821 __le16 first_vf_id; 1822 __le16 max_vfs; 1823 __le16 max_stat_ctx; 1824 __le32 max_encap_records; 1825 __le32 max_decap_records; 1826 __le32 max_tx_em_flows; 1827 __le32 max_tx_wm_flows; 1828 __le32 max_rx_em_flows; 1829 __le32 max_rx_wm_flows; 1830 __le32 max_mcast_filters; 1831 __le32 max_flow_id; 1832 __le32 max_hw_ring_grps; 1833 __le16 max_sp_tx_rings; 1834 __le16 max_msix_vfs; 1835 __le32 flags_ext; 1836 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1837 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1838 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1839 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1840 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1841 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1842 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1843 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1844 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1845 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1846 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1847 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1848 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1849 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1850 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1851 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1852 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1853 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1854 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1855 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1856 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1857 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1858 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1859 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1860 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1861 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1862 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1863 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1864 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1865 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1866 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1867 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1868 u8 max_schqs; 1869 u8 mpc_chnls_cap; 1870 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1871 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1872 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1873 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1874 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1875 __le16 max_key_ctxs_alloc; 1876 __le32 flags_ext2; 1877 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1878 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1879 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1880 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1881 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1882 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1883 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1884 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1885 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1886 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1887 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1888 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1889 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1890 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1891 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1892 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1893 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1894 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1895 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1896 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1897 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1898 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1899 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1900 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1901 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1902 #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1903 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL 1904 #define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL 1905 #define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL 1906 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED 0x20000000UL 1907 #define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED 0x40000000UL 1908 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED 0x80000000UL 1909 __le16 tunnel_disable_flag; 1910 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1911 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1912 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1913 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1914 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1915 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1916 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1917 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1918 __le16 xid_partition_cap; 1919 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1920 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1921 u8 device_serial_number[8]; 1922 __le16 ctxs_per_partition; 1923 __le16 max_tso_segs; 1924 __le32 roce_vf_max_av; 1925 __le32 roce_vf_max_cq; 1926 __le32 roce_vf_max_mrw; 1927 __le32 roce_vf_max_qp; 1928 __le32 roce_vf_max_srq; 1929 __le32 roce_vf_max_gid; 1930 __le32 flags_ext3; 1931 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL 1932 #define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL 1933 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL 1934 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL 1935 #define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL 1936 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL 1937 #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT 0x40UL 1938 #define FUNC_QCAPS_RESP_FLAGS_EXT3_CHANGE_UDP_SRCPORT_SUPPORT 0x80UL 1939 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL 1940 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL 1941 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL 1942 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_DATA_SUPPORTED 0x800UL 1943 #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_CMPL_TS_SUPPORTED 0x1000UL 1944 #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_ST_SUPPORTED 0x2000UL 1945 __le16 max_roce_vfs; 1946 __le16 max_crypto_rx_flow_filters; 1947 u8 unused_3[3]; 1948 u8 valid; 1949 }; 1950 1951 /* hwrm_func_qcfg_input (size:192b/24B) */ 1952 struct hwrm_func_qcfg_input { 1953 __le16 req_type; 1954 __le16 cmpl_ring; 1955 __le16 seq_id; 1956 __le16 target_id; 1957 __le64 resp_addr; 1958 __le16 fid; 1959 u8 unused_0[6]; 1960 }; 1961 1962 /* hwrm_func_qcfg_output (size:1408b/176B) */ 1963 struct hwrm_func_qcfg_output { 1964 __le16 error_code; 1965 __le16 req_type; 1966 __le16 seq_id; 1967 __le16 resp_len; 1968 __le16 fid; 1969 __le16 port_id; 1970 __le16 vlan; 1971 __le16 flags; 1972 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1973 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1974 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1975 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1976 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1977 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1978 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1979 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1980 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1981 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1982 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1983 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1984 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1985 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1986 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1987 #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1988 u8 mac_address[6]; 1989 __le16 pci_id; 1990 __le16 alloc_rsscos_ctx; 1991 __le16 alloc_cmpl_rings; 1992 __le16 alloc_tx_rings; 1993 __le16 alloc_rx_rings; 1994 __le16 alloc_l2_ctx; 1995 __le16 alloc_vnics; 1996 __le16 admin_mtu; 1997 __le16 mru; 1998 __le16 stat_ctx_id; 1999 u8 port_partition_type; 2000 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 2001 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 2002 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 2003 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 2004 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 2005 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 2006 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 2007 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 2008 u8 port_pf_cnt; 2009 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 2010 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 2011 __le16 dflt_vnic_id; 2012 __le16 max_mtu_configured; 2013 __le32 min_bw; 2014 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2015 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 2016 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 2017 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 2018 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 2019 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 2020 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2021 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 2022 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2023 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2024 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2025 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2026 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2027 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2028 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 2029 __le32 max_bw; 2030 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2031 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 2032 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 2033 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 2034 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 2035 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 2036 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2037 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 2038 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2039 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2040 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2041 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2042 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2043 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2044 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 2045 u8 evb_mode; 2046 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 2047 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 2048 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 2049 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 2050 u8 options; 2051 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2052 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 2053 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2054 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2055 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 2056 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2057 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 2058 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2059 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2060 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2061 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 2062 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 2063 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 2064 __le16 alloc_vfs; 2065 __le32 alloc_mcast_filters; 2066 __le32 alloc_hw_ring_grps; 2067 __le16 alloc_sp_tx_rings; 2068 __le16 alloc_stat_ctx; 2069 __le16 alloc_msix; 2070 __le16 registered_vfs; 2071 __le16 l2_doorbell_bar_size_kb; 2072 u8 active_endpoints; 2073 u8 always_1; 2074 __le32 reset_addr_poll; 2075 __le16 legacy_l2_db_size_kb; 2076 __le16 svif_info; 2077 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 2078 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 2079 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 2080 u8 mpc_chnls; 2081 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 2082 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 2083 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 2084 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 2085 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 2086 u8 db_page_size; 2087 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 2088 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 2089 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 2090 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 2091 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 2092 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 2093 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 2094 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 2095 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 2096 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 2097 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 2098 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 2099 __le16 roce_vnic_id; 2100 __le32 partition_min_bw; 2101 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2102 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 2103 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 2104 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2105 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2106 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 2107 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2108 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2109 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2110 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2111 __le32 partition_max_bw; 2112 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2113 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 2114 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 2115 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2116 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2117 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 2118 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2119 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2120 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2121 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2122 __le16 host_mtu; 2123 __le16 flags2; 2124 #define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL 2125 __le16 stag_vid; 2126 u8 port_kdnet_mode; 2127 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 2128 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 2129 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 2130 u8 kdnet_pcie_function; 2131 __le16 port_kdnet_fid; 2132 u8 unused_5; 2133 u8 roce_bidi_opt_mode; 2134 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DISABLED 0x1UL 2135 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DEDICATED 0x2UL 2136 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_SHARED 0x4UL 2137 __le32 num_ktls_tx_key_ctxs; 2138 __le32 num_ktls_rx_key_ctxs; 2139 u8 lag_id; 2140 u8 parif; 2141 u8 fw_lag_id; 2142 u8 unused_6; 2143 __le32 num_quic_tx_key_ctxs; 2144 __le32 num_quic_rx_key_ctxs; 2145 __le32 roce_max_av_per_vf; 2146 __le32 roce_max_cq_per_vf; 2147 __le32 roce_max_mrw_per_vf; 2148 __le32 roce_max_qp_per_vf; 2149 __le32 roce_max_srq_per_vf; 2150 __le32 roce_max_gid_per_vf; 2151 __le16 xid_partition_cfg; 2152 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2153 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2154 __le16 mirror_vnic_id; 2155 u8 max_link_width; 2156 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_UNKNOWN 0x0UL 2157 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X1 0x1UL 2158 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X2 0x2UL 2159 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X4 0x4UL 2160 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X8 0x8UL 2161 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 0x10UL 2162 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_LAST FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 2163 u8 max_link_speed; 2164 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_UNKNOWN 0x0UL 2165 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G1 0x1UL 2166 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G2 0x2UL 2167 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G3 0x3UL 2168 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G4 0x4UL 2169 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 0x5UL 2170 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_LAST FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 2171 u8 negotiated_link_width; 2172 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_UNKNOWN 0x0UL 2173 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X1 0x1UL 2174 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X2 0x2UL 2175 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X4 0x4UL 2176 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X8 0x8UL 2177 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 0x10UL 2178 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 2179 u8 negotiated_link_speed; 2180 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_UNKNOWN 0x0UL 2181 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G1 0x1UL 2182 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G2 0x2UL 2183 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G3 0x3UL 2184 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G4 0x4UL 2185 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 0x5UL 2186 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 2187 u8 unused_7[2]; 2188 u8 pcie_compliance; 2189 u8 unused_8; 2190 __le16 l2_db_multi_page_size_kb; 2191 u8 unused_9[5]; 2192 u8 valid; 2193 }; 2194 2195 /* hwrm_func_cfg_input (size:1280b/160B) */ 2196 struct hwrm_func_cfg_input { 2197 __le16 req_type; 2198 __le16 cmpl_ring; 2199 __le16 seq_id; 2200 __le16 target_id; 2201 __le64 resp_addr; 2202 __le16 fid; 2203 __le16 num_msix; 2204 __le32 flags; 2205 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2206 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2207 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2208 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2209 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2210 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2211 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2212 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2213 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2214 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2215 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2216 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2217 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2218 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2219 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2220 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2221 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2222 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2223 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2224 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2225 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2226 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2227 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2228 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2229 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2230 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2231 __le32 enables; 2232 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2233 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2234 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2235 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2236 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2237 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2238 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2239 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2240 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2241 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2242 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2243 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2244 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2245 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2246 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2247 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2248 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2249 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2250 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2251 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2252 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2253 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2254 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2255 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2256 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2257 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2258 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2259 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2260 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2261 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2262 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2263 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2264 __le16 admin_mtu; 2265 __le16 mru; 2266 __le16 num_rsscos_ctxs; 2267 __le16 num_cmpl_rings; 2268 __le16 num_tx_rings; 2269 __le16 num_rx_rings; 2270 __le16 num_l2_ctxs; 2271 __le16 num_vnics; 2272 __le16 num_stat_ctxs; 2273 __le16 num_hw_ring_grps; 2274 u8 dflt_mac_addr[6]; 2275 __le16 dflt_vlan; 2276 __be32 dflt_ip_addr[4]; 2277 __le32 min_bw; 2278 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2279 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2280 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2281 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2282 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2283 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2284 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2285 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2286 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2287 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2288 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2289 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2290 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2291 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2292 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2293 __le32 max_bw; 2294 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2295 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2296 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2297 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2298 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2299 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2300 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2301 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2302 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2303 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2304 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2305 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2306 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2307 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2308 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2309 __le16 async_event_cr; 2310 u8 vlan_antispoof_mode; 2311 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2312 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2313 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2314 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2315 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2316 u8 allowed_vlan_pris; 2317 u8 evb_mode; 2318 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2319 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2320 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2321 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2322 u8 options; 2323 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2324 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2325 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2326 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2327 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2328 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2329 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2330 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2331 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2332 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2333 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2334 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2335 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2336 __le16 num_mcast_filters; 2337 __le16 schq_id; 2338 __le16 mpc_chnls; 2339 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2340 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2341 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2342 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2343 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2344 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2345 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2346 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2347 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2348 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2349 __le32 partition_min_bw; 2350 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2351 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2352 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2353 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2354 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2355 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2356 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2357 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2358 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2359 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2360 __le32 partition_max_bw; 2361 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2362 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2363 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2364 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2365 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2366 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2367 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2368 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2369 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2370 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2371 __be16 tpid; 2372 __le16 host_mtu; 2373 __le32 flags2; 2374 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2375 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2376 __le32 enables2; 2377 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2378 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2379 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2380 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2381 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2382 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2383 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2384 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2385 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2386 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2387 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2388 #define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL 2389 #define FUNC_CFG_REQ_ENABLES2_PCIE_COMPLIANCE 0x1000UL 2390 u8 port_kdnet_mode; 2391 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2392 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2393 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2394 u8 db_page_size; 2395 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2396 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2397 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2398 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2399 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2400 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2401 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2402 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2403 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2404 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2405 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2406 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2407 __le16 physical_slot_number; 2408 __le32 num_ktls_tx_key_ctxs; 2409 __le32 num_ktls_rx_key_ctxs; 2410 __le32 num_quic_tx_key_ctxs; 2411 __le32 num_quic_rx_key_ctxs; 2412 __le32 roce_max_av_per_vf; 2413 __le32 roce_max_cq_per_vf; 2414 __le32 roce_max_mrw_per_vf; 2415 __le32 roce_max_qp_per_vf; 2416 __le32 roce_max_srq_per_vf; 2417 __le32 roce_max_gid_per_vf; 2418 __le16 xid_partition_cfg; 2419 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2420 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2421 u8 pcie_compliance; 2422 u8 unused_2; 2423 }; 2424 2425 /* hwrm_func_cfg_output (size:128b/16B) */ 2426 struct hwrm_func_cfg_output { 2427 __le16 error_code; 2428 __le16 req_type; 2429 __le16 seq_id; 2430 __le16 resp_len; 2431 u8 unused_0[7]; 2432 u8 valid; 2433 }; 2434 2435 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2436 struct hwrm_func_cfg_cmd_err { 2437 u8 code; 2438 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2439 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_OUT_OF_RANGE 0x1UL 2440 #define FUNC_CFG_CMD_ERR_CODE_NPAR_PARTITION_DOWN_FAILED 0x2UL 2441 #define FUNC_CFG_CMD_ERR_CODE_TPID_SET_DFLT_VLAN_NOT_SET 0x3UL 2442 #define FUNC_CFG_CMD_ERR_CODE_RES_ARRAY_ALLOC_FAILED 0x4UL 2443 #define FUNC_CFG_CMD_ERR_CODE_TX_RING_ASSET_TEST_FAILED 0x5UL 2444 #define FUNC_CFG_CMD_ERR_CODE_TX_RING_RES_UPDATE_FAILED 0x6UL 2445 #define FUNC_CFG_CMD_ERR_CODE_APPLY_MAX_BW_FAILED 0x7UL 2446 #define FUNC_CFG_CMD_ERR_CODE_ENABLE_EVB_FAILED 0x8UL 2447 #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_ASSET_TEST_FAILED 0x9UL 2448 #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_RES_UPDATE_FAILED 0xaUL 2449 #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_ASSET_TEST_FAILED 0xbUL 2450 #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_RES_UPDATE_FAILED 0xcUL 2451 #define FUNC_CFG_CMD_ERR_CODE_NQ_ASSET_TEST_FAILED 0xdUL 2452 #define FUNC_CFG_CMD_ERR_CODE_NQ_RES_UPDATE_FAILED 0xeUL 2453 #define FUNC_CFG_CMD_ERR_CODE_RX_RING_ASSET_TEST_FAILED 0xfUL 2454 #define FUNC_CFG_CMD_ERR_CODE_RX_RING_RES_UPDATE_FAILED 0x10UL 2455 #define FUNC_CFG_CMD_ERR_CODE_VNIC_ASSET_TEST_FAILED 0x11UL 2456 #define FUNC_CFG_CMD_ERR_CODE_VNIC_RES_UPDATE_FAILED 0x12UL 2457 #define FUNC_CFG_CMD_ERR_CODE_FAILED_TO_START_STATS_THREAD 0x13UL 2458 #define FUNC_CFG_CMD_ERR_CODE_RDMA_SRIOV_DISABLED 0x14UL 2459 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_DISABLED 0x15UL 2460 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_ASSET_TEST_FAILED 0x16UL 2461 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_RES_UPDATE_FAILED 0x17UL 2462 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_DISABLED 0x18UL 2463 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_ASSET_TEST_FAILED 0x19UL 2464 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_RES_UPDATE_FAILED 0x1aUL 2465 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_DISABLED 0x1bUL 2466 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_ASSET_TEST_FAILED 0x1cUL 2467 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_RES_UPDATE_FAILED 0x1dUL 2468 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_DISABLED 0x1eUL 2469 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_ASSET_TEST_FAILED 0x1fUL 2470 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED 0x20UL 2471 #define FUNC_CFG_CMD_ERR_CODE_INVALID_KDNET_MODE 0x21UL 2472 #define FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 0x22UL 2473 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 2474 u8 unused_0[7]; 2475 }; 2476 2477 /* hwrm_func_qstats_input (size:192b/24B) */ 2478 struct hwrm_func_qstats_input { 2479 __le16 req_type; 2480 __le16 cmpl_ring; 2481 __le16 seq_id; 2482 __le16 target_id; 2483 __le64 resp_addr; 2484 __le16 fid; 2485 u8 flags; 2486 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2487 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2488 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2489 u8 unused_0[5]; 2490 }; 2491 2492 /* hwrm_func_qstats_output (size:1408b/176B) */ 2493 struct hwrm_func_qstats_output { 2494 __le16 error_code; 2495 __le16 req_type; 2496 __le16 seq_id; 2497 __le16 resp_len; 2498 __le64 tx_ucast_pkts; 2499 __le64 tx_mcast_pkts; 2500 __le64 tx_bcast_pkts; 2501 __le64 tx_discard_pkts; 2502 __le64 tx_drop_pkts; 2503 __le64 tx_ucast_bytes; 2504 __le64 tx_mcast_bytes; 2505 __le64 tx_bcast_bytes; 2506 __le64 rx_ucast_pkts; 2507 __le64 rx_mcast_pkts; 2508 __le64 rx_bcast_pkts; 2509 __le64 rx_discard_pkts; 2510 __le64 rx_drop_pkts; 2511 __le64 rx_ucast_bytes; 2512 __le64 rx_mcast_bytes; 2513 __le64 rx_bcast_bytes; 2514 __le64 rx_agg_pkts; 2515 __le64 rx_agg_bytes; 2516 __le64 rx_agg_events; 2517 __le64 rx_agg_aborts; 2518 u8 clear_seq; 2519 u8 unused_0[6]; 2520 u8 valid; 2521 }; 2522 2523 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2524 struct hwrm_func_qstats_ext_input { 2525 __le16 req_type; 2526 __le16 cmpl_ring; 2527 __le16 seq_id; 2528 __le16 target_id; 2529 __le64 resp_addr; 2530 __le16 fid; 2531 u8 flags; 2532 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2533 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2534 u8 unused_0[1]; 2535 __le32 enables; 2536 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2537 __le16 schq_id; 2538 __le16 traffic_class; 2539 u8 unused_1[4]; 2540 }; 2541 2542 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2543 struct hwrm_func_qstats_ext_output { 2544 __le16 error_code; 2545 __le16 req_type; 2546 __le16 seq_id; 2547 __le16 resp_len; 2548 __le64 rx_ucast_pkts; 2549 __le64 rx_mcast_pkts; 2550 __le64 rx_bcast_pkts; 2551 __le64 rx_discard_pkts; 2552 __le64 rx_error_pkts; 2553 __le64 rx_ucast_bytes; 2554 __le64 rx_mcast_bytes; 2555 __le64 rx_bcast_bytes; 2556 __le64 tx_ucast_pkts; 2557 __le64 tx_mcast_pkts; 2558 __le64 tx_bcast_pkts; 2559 __le64 tx_error_pkts; 2560 __le64 tx_discard_pkts; 2561 __le64 tx_ucast_bytes; 2562 __le64 tx_mcast_bytes; 2563 __le64 tx_bcast_bytes; 2564 __le64 rx_tpa_eligible_pkt; 2565 __le64 rx_tpa_eligible_bytes; 2566 __le64 rx_tpa_pkt; 2567 __le64 rx_tpa_bytes; 2568 __le64 rx_tpa_errors; 2569 __le64 rx_tpa_events; 2570 u8 unused_0[7]; 2571 u8 valid; 2572 }; 2573 2574 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2575 struct hwrm_func_clr_stats_input { 2576 __le16 req_type; 2577 __le16 cmpl_ring; 2578 __le16 seq_id; 2579 __le16 target_id; 2580 __le64 resp_addr; 2581 __le16 fid; 2582 u8 unused_0[6]; 2583 }; 2584 2585 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2586 struct hwrm_func_clr_stats_output { 2587 __le16 error_code; 2588 __le16 req_type; 2589 __le16 seq_id; 2590 __le16 resp_len; 2591 u8 unused_0[7]; 2592 u8 valid; 2593 }; 2594 2595 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2596 struct hwrm_func_vf_resc_free_input { 2597 __le16 req_type; 2598 __le16 cmpl_ring; 2599 __le16 seq_id; 2600 __le16 target_id; 2601 __le64 resp_addr; 2602 __le16 vf_id; 2603 u8 unused_0[6]; 2604 }; 2605 2606 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2607 struct hwrm_func_vf_resc_free_output { 2608 __le16 error_code; 2609 __le16 req_type; 2610 __le16 seq_id; 2611 __le16 resp_len; 2612 u8 unused_0[7]; 2613 u8 valid; 2614 }; 2615 2616 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2617 struct hwrm_func_drv_rgtr_input { 2618 __le16 req_type; 2619 __le16 cmpl_ring; 2620 __le16 seq_id; 2621 __le16 target_id; 2622 __le64 resp_addr; 2623 __le32 flags; 2624 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2625 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2626 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2627 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2628 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2629 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2630 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2631 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2632 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2633 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2634 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2635 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2636 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE 0x1000UL 2637 __le32 enables; 2638 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2639 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2640 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2641 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2642 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2643 __le16 os_type; 2644 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2645 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2646 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2647 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2648 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2649 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2650 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2651 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2652 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2653 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2654 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2655 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2656 u8 ver_maj_8b; 2657 u8 ver_min_8b; 2658 u8 ver_upd_8b; 2659 u8 unused_0[3]; 2660 __le32 timestamp; 2661 u8 unused_1[4]; 2662 __le32 vf_req_fwd[8]; 2663 __le32 async_event_fwd[8]; 2664 __le16 ver_maj; 2665 __le16 ver_min; 2666 __le16 ver_upd; 2667 __le16 ver_patch; 2668 }; 2669 2670 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2671 struct hwrm_func_drv_rgtr_output { 2672 __le16 error_code; 2673 __le16 req_type; 2674 __le16 seq_id; 2675 __le16 resp_len; 2676 __le32 flags; 2677 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2678 u8 unused_0[3]; 2679 u8 valid; 2680 }; 2681 2682 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2683 struct hwrm_func_drv_unrgtr_input { 2684 __le16 req_type; 2685 __le16 cmpl_ring; 2686 __le16 seq_id; 2687 __le16 target_id; 2688 __le64 resp_addr; 2689 __le32 flags; 2690 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2691 u8 unused_0[4]; 2692 }; 2693 2694 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2695 struct hwrm_func_drv_unrgtr_output { 2696 __le16 error_code; 2697 __le16 req_type; 2698 __le16 seq_id; 2699 __le16 resp_len; 2700 u8 unused_0[7]; 2701 u8 valid; 2702 }; 2703 2704 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2705 struct hwrm_func_buf_rgtr_input { 2706 __le16 req_type; 2707 __le16 cmpl_ring; 2708 __le16 seq_id; 2709 __le16 target_id; 2710 __le64 resp_addr; 2711 __le32 enables; 2712 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2713 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2714 __le16 vf_id; 2715 __le16 req_buf_num_pages; 2716 __le16 req_buf_page_size; 2717 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2718 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2719 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2720 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2721 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2722 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2723 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2724 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2725 __le16 req_buf_len; 2726 __le16 resp_buf_len; 2727 u8 unused_0[2]; 2728 __le64 req_buf_page_addr0; 2729 __le64 req_buf_page_addr1; 2730 __le64 req_buf_page_addr2; 2731 __le64 req_buf_page_addr3; 2732 __le64 req_buf_page_addr4; 2733 __le64 req_buf_page_addr5; 2734 __le64 req_buf_page_addr6; 2735 __le64 req_buf_page_addr7; 2736 __le64 req_buf_page_addr8; 2737 __le64 req_buf_page_addr9; 2738 __le64 error_buf_addr; 2739 __le64 resp_buf_addr; 2740 }; 2741 2742 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2743 struct hwrm_func_buf_rgtr_output { 2744 __le16 error_code; 2745 __le16 req_type; 2746 __le16 seq_id; 2747 __le16 resp_len; 2748 u8 unused_0[7]; 2749 u8 valid; 2750 }; 2751 2752 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2753 struct hwrm_func_drv_qver_input { 2754 __le16 req_type; 2755 __le16 cmpl_ring; 2756 __le16 seq_id; 2757 __le16 target_id; 2758 __le64 resp_addr; 2759 __le32 reserved; 2760 __le16 fid; 2761 u8 driver_type; 2762 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2763 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2764 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2765 u8 unused_0; 2766 }; 2767 2768 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2769 struct hwrm_func_drv_qver_output { 2770 __le16 error_code; 2771 __le16 req_type; 2772 __le16 seq_id; 2773 __le16 resp_len; 2774 __le16 os_type; 2775 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2776 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2777 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2778 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2779 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2780 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2781 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2782 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2783 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2784 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2785 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2786 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2787 u8 ver_maj_8b; 2788 u8 ver_min_8b; 2789 u8 ver_upd_8b; 2790 u8 unused_0[3]; 2791 __le16 ver_maj; 2792 __le16 ver_min; 2793 __le16 ver_upd; 2794 __le16 ver_patch; 2795 u8 unused_1[7]; 2796 u8 valid; 2797 }; 2798 2799 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2800 struct hwrm_func_resource_qcaps_input { 2801 __le16 req_type; 2802 __le16 cmpl_ring; 2803 __le16 seq_id; 2804 __le16 target_id; 2805 __le64 resp_addr; 2806 __le16 fid; 2807 u8 unused_0[6]; 2808 }; 2809 2810 /* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2811 struct hwrm_func_resource_qcaps_output { 2812 __le16 error_code; 2813 __le16 req_type; 2814 __le16 seq_id; 2815 __le16 resp_len; 2816 __le16 max_vfs; 2817 __le16 max_msix; 2818 __le16 vf_reservation_strategy; 2819 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2820 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2821 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2822 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2823 __le16 min_rsscos_ctx; 2824 __le16 max_rsscos_ctx; 2825 __le16 min_cmpl_rings; 2826 __le16 max_cmpl_rings; 2827 __le16 min_tx_rings; 2828 __le16 max_tx_rings; 2829 __le16 min_rx_rings; 2830 __le16 max_rx_rings; 2831 __le16 min_l2_ctxs; 2832 __le16 max_l2_ctxs; 2833 __le16 min_vnics; 2834 __le16 max_vnics; 2835 __le16 min_stat_ctx; 2836 __le16 max_stat_ctx; 2837 __le16 min_hw_ring_grps; 2838 __le16 max_hw_ring_grps; 2839 __le16 max_tx_scheduler_inputs; 2840 __le16 flags; 2841 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2842 __le16 min_msix; 2843 __le32 min_ktls_tx_key_ctxs; 2844 __le32 max_ktls_tx_key_ctxs; 2845 __le32 min_ktls_rx_key_ctxs; 2846 __le32 max_ktls_rx_key_ctxs; 2847 __le32 min_quic_tx_key_ctxs; 2848 __le32 max_quic_tx_key_ctxs; 2849 __le32 min_quic_rx_key_ctxs; 2850 __le32 max_quic_rx_key_ctxs; 2851 u8 unused_0[3]; 2852 u8 valid; 2853 }; 2854 2855 /* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2856 struct hwrm_func_vf_resource_cfg_input { 2857 __le16 req_type; 2858 __le16 cmpl_ring; 2859 __le16 seq_id; 2860 __le16 target_id; 2861 __le64 resp_addr; 2862 __le16 vf_id; 2863 __le16 max_msix; 2864 __le16 min_rsscos_ctx; 2865 __le16 max_rsscos_ctx; 2866 __le16 min_cmpl_rings; 2867 __le16 max_cmpl_rings; 2868 __le16 min_tx_rings; 2869 __le16 max_tx_rings; 2870 __le16 min_rx_rings; 2871 __le16 max_rx_rings; 2872 __le16 min_l2_ctxs; 2873 __le16 max_l2_ctxs; 2874 __le16 min_vnics; 2875 __le16 max_vnics; 2876 __le16 min_stat_ctx; 2877 __le16 max_stat_ctx; 2878 __le16 min_hw_ring_grps; 2879 __le16 max_hw_ring_grps; 2880 __le16 flags; 2881 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2882 __le16 min_msix; 2883 __le32 min_ktls_tx_key_ctxs; 2884 __le32 max_ktls_tx_key_ctxs; 2885 __le32 min_ktls_rx_key_ctxs; 2886 __le32 max_ktls_rx_key_ctxs; 2887 __le32 min_quic_tx_key_ctxs; 2888 __le32 max_quic_tx_key_ctxs; 2889 __le32 min_quic_rx_key_ctxs; 2890 __le32 max_quic_rx_key_ctxs; 2891 }; 2892 2893 /* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2894 struct hwrm_func_vf_resource_cfg_output { 2895 __le16 error_code; 2896 __le16 req_type; 2897 __le16 seq_id; 2898 __le16 resp_len; 2899 __le16 reserved_rsscos_ctx; 2900 __le16 reserved_cmpl_rings; 2901 __le16 reserved_tx_rings; 2902 __le16 reserved_rx_rings; 2903 __le16 reserved_l2_ctxs; 2904 __le16 reserved_vnics; 2905 __le16 reserved_stat_ctx; 2906 __le16 reserved_hw_ring_grps; 2907 __le32 reserved_ktls_tx_key_ctxs; 2908 __le32 reserved_ktls_rx_key_ctxs; 2909 __le32 reserved_quic_tx_key_ctxs; 2910 __le32 reserved_quic_rx_key_ctxs; 2911 u8 unused_0[7]; 2912 u8 valid; 2913 }; 2914 2915 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2916 struct hwrm_func_backing_store_qcaps_input { 2917 __le16 req_type; 2918 __le16 cmpl_ring; 2919 __le16 seq_id; 2920 __le16 target_id; 2921 __le64 resp_addr; 2922 }; 2923 2924 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2925 struct hwrm_func_backing_store_qcaps_output { 2926 __le16 error_code; 2927 __le16 req_type; 2928 __le16 seq_id; 2929 __le16 resp_len; 2930 __le32 qp_max_entries; 2931 __le16 qp_min_qp1_entries; 2932 __le16 qp_max_l2_entries; 2933 __le16 qp_entry_size; 2934 __le16 srq_max_l2_entries; 2935 __le32 srq_max_entries; 2936 __le16 srq_entry_size; 2937 __le16 cq_max_l2_entries; 2938 __le32 cq_max_entries; 2939 __le16 cq_entry_size; 2940 __le16 vnic_max_vnic_entries; 2941 __le16 vnic_max_ring_table_entries; 2942 __le16 vnic_entry_size; 2943 __le32 stat_max_entries; 2944 __le16 stat_entry_size; 2945 __le16 tqm_entry_size; 2946 __le32 tqm_min_entries_per_ring; 2947 __le32 tqm_max_entries_per_ring; 2948 __le32 mrav_max_entries; 2949 __le16 mrav_entry_size; 2950 __le16 tim_entry_size; 2951 __le32 tim_max_entries; 2952 __le16 mrav_num_entries_units; 2953 u8 tqm_entries_multiple; 2954 u8 ctx_kind_initializer; 2955 __le16 ctx_init_mask; 2956 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2957 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2958 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2959 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2960 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2961 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2962 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2963 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2964 u8 qp_init_offset; 2965 u8 srq_init_offset; 2966 u8 cq_init_offset; 2967 u8 vnic_init_offset; 2968 u8 tqm_fp_rings_count; 2969 u8 stat_init_offset; 2970 u8 mrav_init_offset; 2971 u8 tqm_fp_rings_count_ext; 2972 u8 tkc_init_offset; 2973 u8 rkc_init_offset; 2974 __le16 tkc_entry_size; 2975 __le16 rkc_entry_size; 2976 __le32 tkc_max_entries; 2977 __le32 rkc_max_entries; 2978 __le16 fast_qpmd_qp_num_entries; 2979 u8 rsvd1[5]; 2980 u8 valid; 2981 }; 2982 2983 /* tqm_fp_ring_cfg (size:128b/16B) */ 2984 struct tqm_fp_ring_cfg { 2985 u8 tqm_ring_pg_size_tqm_ring_lvl; 2986 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2987 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2988 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2989 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2990 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2991 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2992 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2993 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2994 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2995 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2996 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2997 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2998 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2999 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3000 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 3001 u8 unused[3]; 3002 __le32 tqm_ring_num_entries; 3003 __le64 tqm_ring_page_dir; 3004 }; 3005 3006 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 3007 struct hwrm_func_backing_store_cfg_input { 3008 __le16 req_type; 3009 __le16 cmpl_ring; 3010 __le16 seq_id; 3011 __le16 target_id; 3012 __le64 resp_addr; 3013 __le32 flags; 3014 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 3015 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 3016 __le32 enables; 3017 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 3018 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 3019 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 3020 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 3021 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 3022 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 3023 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 3024 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 3025 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 3026 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 3027 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 3028 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 3029 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 3030 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 3031 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 3032 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 3033 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 3034 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 3035 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 3036 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 3037 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 3038 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 3039 u8 qpc_pg_size_qpc_lvl; 3040 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 3041 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 3042 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 3043 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 3044 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 3045 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 3046 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 3047 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 3048 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 3049 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 3050 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 3051 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 3052 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 3053 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 3054 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 3055 u8 srq_pg_size_srq_lvl; 3056 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 3057 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 3058 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 3059 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 3060 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 3061 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 3062 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 3063 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 3064 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 3065 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 3066 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 3067 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 3068 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 3069 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 3070 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 3071 u8 cq_pg_size_cq_lvl; 3072 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 3073 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 3074 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 3075 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 3076 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 3077 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 3078 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 3079 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 3080 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 3081 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 3082 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 3083 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 3084 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 3085 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 3086 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 3087 u8 vnic_pg_size_vnic_lvl; 3088 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 3089 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 3090 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 3091 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 3092 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 3093 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 3094 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 3095 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 3096 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 3097 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 3098 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 3099 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 3100 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 3101 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 3102 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 3103 u8 stat_pg_size_stat_lvl; 3104 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 3105 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 3106 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 3107 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 3108 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 3109 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 3110 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 3111 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 3112 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 3113 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 3114 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 3115 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 3116 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 3117 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 3118 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 3119 u8 tqm_sp_pg_size_tqm_sp_lvl; 3120 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 3121 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 3122 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 3123 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 3124 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 3125 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 3126 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 3127 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 3128 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 3129 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 3130 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 3131 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 3132 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 3133 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 3134 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 3135 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 3136 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 3137 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 3138 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 3139 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 3140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 3141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 3142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 3143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 3144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 3145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 3146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 3147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 3148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 3149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 3150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 3151 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 3152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 3153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 3154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 3155 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 3156 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 3157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 3158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 3159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 3160 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 3161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 3162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 3163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 3164 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 3165 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 3166 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 3167 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 3168 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 3169 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 3170 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 3171 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 3172 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 3173 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 3174 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 3175 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 3176 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 3177 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 3178 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 3179 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 3180 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 3181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 3182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 3183 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 3184 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 3185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 3186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 3187 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 3188 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 3189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 3190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 3191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 3192 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 3193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 3194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 3195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 3196 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 3197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 3198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 3199 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 3200 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 3201 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 3202 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 3203 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 3204 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 3205 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 3206 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 3207 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 3208 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 3209 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 3210 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 3211 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 3212 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 3213 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 3214 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 3215 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 3216 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 3217 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3218 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3219 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3220 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3221 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3222 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3223 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3224 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3225 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3226 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3227 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3228 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3229 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3230 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3231 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3232 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3233 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3235 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3236 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3240 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3244 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3247 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3249 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3251 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3252 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3256 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3257 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3258 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3259 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3260 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3261 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3262 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3263 u8 mrav_pg_size_mrav_lvl; 3264 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3265 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3266 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3267 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3268 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3269 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3270 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3271 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3272 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3273 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3274 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3275 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3276 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3277 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3278 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3279 u8 tim_pg_size_tim_lvl; 3280 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3281 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3282 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3283 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3284 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3285 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3286 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3287 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3288 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3289 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3290 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3291 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3292 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3293 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3294 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3295 __le64 qpc_page_dir; 3296 __le64 srq_page_dir; 3297 __le64 cq_page_dir; 3298 __le64 vnic_page_dir; 3299 __le64 stat_page_dir; 3300 __le64 tqm_sp_page_dir; 3301 __le64 tqm_ring0_page_dir; 3302 __le64 tqm_ring1_page_dir; 3303 __le64 tqm_ring2_page_dir; 3304 __le64 tqm_ring3_page_dir; 3305 __le64 tqm_ring4_page_dir; 3306 __le64 tqm_ring5_page_dir; 3307 __le64 tqm_ring6_page_dir; 3308 __le64 tqm_ring7_page_dir; 3309 __le64 mrav_page_dir; 3310 __le64 tim_page_dir; 3311 __le32 qp_num_entries; 3312 __le32 srq_num_entries; 3313 __le32 cq_num_entries; 3314 __le32 stat_num_entries; 3315 __le32 tqm_sp_num_entries; 3316 __le32 tqm_ring0_num_entries; 3317 __le32 tqm_ring1_num_entries; 3318 __le32 tqm_ring2_num_entries; 3319 __le32 tqm_ring3_num_entries; 3320 __le32 tqm_ring4_num_entries; 3321 __le32 tqm_ring5_num_entries; 3322 __le32 tqm_ring6_num_entries; 3323 __le32 tqm_ring7_num_entries; 3324 __le32 mrav_num_entries; 3325 __le32 tim_num_entries; 3326 __le16 qp_num_qp1_entries; 3327 __le16 qp_num_l2_entries; 3328 __le16 qp_entry_size; 3329 __le16 srq_num_l2_entries; 3330 __le16 srq_entry_size; 3331 __le16 cq_num_l2_entries; 3332 __le16 cq_entry_size; 3333 __le16 vnic_num_vnic_entries; 3334 __le16 vnic_num_ring_table_entries; 3335 __le16 vnic_entry_size; 3336 __le16 stat_entry_size; 3337 __le16 tqm_entry_size; 3338 __le16 mrav_entry_size; 3339 __le16 tim_entry_size; 3340 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3341 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3342 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3343 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3344 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3345 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3346 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3347 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3348 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3349 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3350 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3351 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3352 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3353 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3354 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3355 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3356 u8 ring8_unused[3]; 3357 __le32 tqm_ring8_num_entries; 3358 __le64 tqm_ring8_page_dir; 3359 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3360 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3361 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3362 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3363 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3364 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3365 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3366 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3367 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3368 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3369 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3370 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3371 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3372 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3373 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3374 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3375 u8 ring9_unused[3]; 3376 __le32 tqm_ring9_num_entries; 3377 __le64 tqm_ring9_page_dir; 3378 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3379 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3380 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3381 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3382 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3383 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3384 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3385 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3386 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3387 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3388 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3389 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3390 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3391 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3392 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3393 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3394 u8 ring10_unused[3]; 3395 __le32 tqm_ring10_num_entries; 3396 __le64 tqm_ring10_page_dir; 3397 __le32 tkc_num_entries; 3398 __le32 rkc_num_entries; 3399 __le64 tkc_page_dir; 3400 __le64 rkc_page_dir; 3401 __le16 tkc_entry_size; 3402 __le16 rkc_entry_size; 3403 u8 tkc_pg_size_tkc_lvl; 3404 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3405 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3406 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3407 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3408 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3409 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3410 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3411 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3412 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3413 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3414 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3415 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3416 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3417 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3418 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3419 u8 rkc_pg_size_rkc_lvl; 3420 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3421 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3422 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3423 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3424 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3425 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3426 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3427 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3428 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3429 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3430 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3431 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3432 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3433 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3434 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3435 __le16 qp_num_fast_qpmd_entries; 3436 }; 3437 3438 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3439 struct hwrm_func_backing_store_cfg_output { 3440 __le16 error_code; 3441 __le16 req_type; 3442 __le16 seq_id; 3443 __le16 resp_len; 3444 u8 unused_0[7]; 3445 u8 valid; 3446 }; 3447 3448 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3449 struct hwrm_error_recovery_qcfg_input { 3450 __le16 req_type; 3451 __le16 cmpl_ring; 3452 __le16 seq_id; 3453 __le16 target_id; 3454 __le64 resp_addr; 3455 u8 unused_0[8]; 3456 }; 3457 3458 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3459 struct hwrm_error_recovery_qcfg_output { 3460 __le16 error_code; 3461 __le16 req_type; 3462 __le16 seq_id; 3463 __le16 resp_len; 3464 __le32 flags; 3465 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3466 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3467 __le32 driver_polling_freq; 3468 __le32 master_func_wait_period; 3469 __le32 normal_func_wait_period; 3470 __le32 master_func_wait_period_after_reset; 3471 __le32 max_bailout_time_after_reset; 3472 __le32 fw_health_status_reg; 3473 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3474 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3475 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3476 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3477 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3478 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3479 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3480 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3481 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3482 __le32 fw_heartbeat_reg; 3483 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3484 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3485 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3486 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3487 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3488 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3489 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3490 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3491 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3492 __le32 fw_reset_cnt_reg; 3493 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3494 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3495 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3496 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3497 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3498 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3499 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3500 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3501 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3502 __le32 reset_inprogress_reg; 3503 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3504 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3505 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3506 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3507 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3508 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3509 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3510 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3511 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3512 __le32 reset_inprogress_reg_mask; 3513 u8 unused_0[3]; 3514 u8 reg_array_cnt; 3515 __le32 reset_reg[16]; 3516 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3517 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3518 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3519 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3520 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3521 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3522 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3523 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3524 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3525 __le32 reset_reg_val[16]; 3526 u8 delay_after_reset[16]; 3527 __le32 err_recovery_cnt_reg; 3528 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3529 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3530 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3531 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3532 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3533 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3534 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3535 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3536 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3537 u8 unused_1[3]; 3538 u8 valid; 3539 }; 3540 3541 /* hwrm_func_echo_response_input (size:192b/24B) */ 3542 struct hwrm_func_echo_response_input { 3543 __le16 req_type; 3544 __le16 cmpl_ring; 3545 __le16 seq_id; 3546 __le16 target_id; 3547 __le64 resp_addr; 3548 __le32 event_data1; 3549 __le32 event_data2; 3550 }; 3551 3552 /* hwrm_func_echo_response_output (size:128b/16B) */ 3553 struct hwrm_func_echo_response_output { 3554 __le16 error_code; 3555 __le16 req_type; 3556 __le16 seq_id; 3557 __le16 resp_len; 3558 u8 unused_0[7]; 3559 u8 valid; 3560 }; 3561 3562 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3563 struct hwrm_func_ptp_pin_qcfg_input { 3564 __le16 req_type; 3565 __le16 cmpl_ring; 3566 __le16 seq_id; 3567 __le16 target_id; 3568 __le64 resp_addr; 3569 u8 unused_0[8]; 3570 }; 3571 3572 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3573 struct hwrm_func_ptp_pin_qcfg_output { 3574 __le16 error_code; 3575 __le16 req_type; 3576 __le16 seq_id; 3577 __le16 resp_len; 3578 u8 num_pins; 3579 u8 state; 3580 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3581 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3582 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3583 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3584 u8 pin0_usage; 3585 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3586 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3587 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3588 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3589 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3590 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3591 u8 pin1_usage; 3592 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3593 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3594 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3595 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3596 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3597 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3598 u8 pin2_usage; 3599 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3600 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3601 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3602 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3603 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3604 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3605 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3606 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3607 u8 pin3_usage; 3608 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3609 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3610 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3611 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3612 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3613 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3614 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3615 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3616 u8 unused_0; 3617 u8 valid; 3618 }; 3619 3620 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3621 struct hwrm_func_ptp_pin_cfg_input { 3622 __le16 req_type; 3623 __le16 cmpl_ring; 3624 __le16 seq_id; 3625 __le16 target_id; 3626 __le64 resp_addr; 3627 __le32 enables; 3628 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3629 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3630 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3631 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3632 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3633 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3634 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3635 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3636 u8 pin0_state; 3637 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3638 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3639 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3640 u8 pin0_usage; 3641 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3642 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3643 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3644 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3645 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3646 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3647 u8 pin1_state; 3648 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3649 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3650 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3651 u8 pin1_usage; 3652 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3653 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3654 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3655 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3656 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3657 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3658 u8 pin2_state; 3659 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3660 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3661 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3662 u8 pin2_usage; 3663 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3664 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3665 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3666 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3667 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3668 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3669 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3670 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3671 u8 pin3_state; 3672 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3673 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3674 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3675 u8 pin3_usage; 3676 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3677 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3678 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3679 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3680 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3681 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3682 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3683 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3684 u8 unused_0[4]; 3685 }; 3686 3687 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3688 struct hwrm_func_ptp_pin_cfg_output { 3689 __le16 error_code; 3690 __le16 req_type; 3691 __le16 seq_id; 3692 __le16 resp_len; 3693 u8 unused_0[7]; 3694 u8 valid; 3695 }; 3696 3697 /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3698 struct hwrm_func_ptp_cfg_input { 3699 __le16 req_type; 3700 __le16 cmpl_ring; 3701 __le16 seq_id; 3702 __le16 target_id; 3703 __le64 resp_addr; 3704 __le16 enables; 3705 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3706 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3707 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3708 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3709 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3710 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3711 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3712 u8 ptp_pps_event; 3713 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3714 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3715 u8 ptp_freq_adj_dll_source; 3716 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3717 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3718 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3719 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3720 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3721 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3722 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3723 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3724 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3725 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3726 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3727 u8 ptp_freq_adj_dll_phase; 3728 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3729 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3730 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3731 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3732 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3733 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3734 u8 unused_0[3]; 3735 __le32 ptp_freq_adj_ext_period; 3736 __le32 ptp_freq_adj_ext_up; 3737 __le32 ptp_freq_adj_ext_phase_lower; 3738 __le32 ptp_freq_adj_ext_phase_upper; 3739 __le64 ptp_set_time; 3740 }; 3741 3742 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3743 struct hwrm_func_ptp_cfg_output { 3744 __le16 error_code; 3745 __le16 req_type; 3746 __le16 seq_id; 3747 __le16 resp_len; 3748 u8 unused_0[7]; 3749 u8 valid; 3750 }; 3751 3752 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3753 struct hwrm_func_ptp_ts_query_input { 3754 __le16 req_type; 3755 __le16 cmpl_ring; 3756 __le16 seq_id; 3757 __le16 target_id; 3758 __le64 resp_addr; 3759 __le32 flags; 3760 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3761 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3762 u8 unused_0[4]; 3763 }; 3764 3765 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3766 struct hwrm_func_ptp_ts_query_output { 3767 __le16 error_code; 3768 __le16 req_type; 3769 __le16 seq_id; 3770 __le16 resp_len; 3771 __le64 pps_event_ts; 3772 __le64 ptm_local_ts; 3773 __le64 ptm_system_ts; 3774 __le32 ptm_link_delay; 3775 u8 unused_0[3]; 3776 u8 valid; 3777 }; 3778 3779 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3780 struct hwrm_func_ptp_ext_cfg_input { 3781 __le16 req_type; 3782 __le16 cmpl_ring; 3783 __le16 seq_id; 3784 __le16 target_id; 3785 __le64 resp_addr; 3786 __le16 enables; 3787 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3788 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3789 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3790 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3791 __le16 phc_master_fid; 3792 __le16 phc_sec_fid; 3793 u8 phc_sec_mode; 3794 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3795 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3796 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3797 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3798 u8 unused_0; 3799 __le32 failover_timer; 3800 u8 unused_1[4]; 3801 }; 3802 3803 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3804 struct hwrm_func_ptp_ext_cfg_output { 3805 __le16 error_code; 3806 __le16 req_type; 3807 __le16 seq_id; 3808 __le16 resp_len; 3809 u8 unused_0[7]; 3810 u8 valid; 3811 }; 3812 3813 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3814 struct hwrm_func_ptp_ext_qcfg_input { 3815 __le16 req_type; 3816 __le16 cmpl_ring; 3817 __le16 seq_id; 3818 __le16 target_id; 3819 __le64 resp_addr; 3820 u8 unused_0[8]; 3821 }; 3822 3823 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3824 struct hwrm_func_ptp_ext_qcfg_output { 3825 __le16 error_code; 3826 __le16 req_type; 3827 __le16 seq_id; 3828 __le16 resp_len; 3829 __le16 phc_master_fid; 3830 __le16 phc_sec_fid; 3831 __le16 phc_active_fid0; 3832 __le16 phc_active_fid1; 3833 __le32 last_failover_event; 3834 __le16 from_fid; 3835 __le16 to_fid; 3836 u8 unused_0[7]; 3837 u8 valid; 3838 }; 3839 3840 /* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */ 3841 struct hwrm_func_backing_store_cfg_v2_input { 3842 __le16 req_type; 3843 __le16 cmpl_ring; 3844 __le16 seq_id; 3845 __le16 target_id; 3846 __le64 resp_addr; 3847 __le16 type; 3848 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3849 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3850 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3851 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3852 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3853 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3854 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3855 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3856 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3857 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3858 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3859 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3860 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3861 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3862 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3863 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3864 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3865 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3866 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3867 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3868 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3869 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3870 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3871 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3872 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3873 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3874 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3875 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3876 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3877 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3878 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3879 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3880 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3881 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3882 __le16 instance; 3883 __le32 flags; 3884 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3885 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3886 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3887 __le64 page_dir; 3888 __le32 num_entries; 3889 __le16 entry_size; 3890 u8 page_size_pbl_level; 3891 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3892 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3893 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3894 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3895 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3896 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3897 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3898 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3899 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3900 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3901 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3902 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3903 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3904 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3905 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3906 u8 subtype_valid_cnt; 3907 __le32 split_entry_0; 3908 __le32 split_entry_1; 3909 __le32 split_entry_2; 3910 __le32 split_entry_3; 3911 __le32 enables; 3912 #define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL 3913 __le32 next_bs_offset; 3914 }; 3915 3916 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3917 struct hwrm_func_backing_store_cfg_v2_output { 3918 __le16 error_code; 3919 __le16 req_type; 3920 __le16 seq_id; 3921 __le16 resp_len; 3922 u8 rsvd0[7]; 3923 u8 valid; 3924 }; 3925 3926 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3927 struct hwrm_func_backing_store_qcfg_v2_input { 3928 __le16 req_type; 3929 __le16 cmpl_ring; 3930 __le16 seq_id; 3931 __le16 target_id; 3932 __le64 resp_addr; 3933 __le16 type; 3934 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3935 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3936 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3937 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3938 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3939 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3940 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3941 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3942 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3943 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3944 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3945 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3946 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3947 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3948 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3949 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3950 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3951 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3952 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3953 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3954 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3955 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3956 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3957 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3958 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3959 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3960 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3961 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3962 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3963 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3964 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3965 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3966 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3967 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3968 __le16 instance; 3969 u8 rsvd[4]; 3970 }; 3971 3972 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3973 struct hwrm_func_backing_store_qcfg_v2_output { 3974 __le16 error_code; 3975 __le16 req_type; 3976 __le16 seq_id; 3977 __le16 resp_len; 3978 __le16 type; 3979 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3980 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3981 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3982 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3983 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3984 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3985 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3986 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3987 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3988 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3989 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3990 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3991 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3992 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3993 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3994 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3995 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3996 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3997 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3998 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3999 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 4000 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 4001 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE 0x26UL 4002 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL 4003 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL 4004 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 4005 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ERR_QPC_TRACE 0x2aUL 4006 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 4007 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 4008 __le16 instance; 4009 __le32 flags; 4010 __le64 page_dir; 4011 __le32 num_entries; 4012 u8 page_size_pbl_level; 4013 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 4014 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 4015 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 4016 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 4017 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 4018 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 4019 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 4020 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 4021 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 4022 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 4023 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 4024 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 4025 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 4026 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 4027 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 4028 u8 subtype_valid_cnt; 4029 u8 rsvd[2]; 4030 __le32 split_entry_0; 4031 __le32 split_entry_1; 4032 __le32 split_entry_2; 4033 __le32 split_entry_3; 4034 u8 rsvd2[7]; 4035 u8 valid; 4036 }; 4037 4038 /* qpc_split_entries (size:128b/16B) */ 4039 struct qpc_split_entries { 4040 __le32 qp_num_l2_entries; 4041 __le32 qp_num_qp1_entries; 4042 __le32 qp_num_fast_qpmd_entries; 4043 __le32 rsvd; 4044 }; 4045 4046 /* srq_split_entries (size:128b/16B) */ 4047 struct srq_split_entries { 4048 __le32 srq_num_l2_entries; 4049 __le32 rsvd; 4050 __le32 rsvd2[2]; 4051 }; 4052 4053 /* cq_split_entries (size:128b/16B) */ 4054 struct cq_split_entries { 4055 __le32 cq_num_l2_entries; 4056 __le32 rsvd; 4057 __le32 rsvd2[2]; 4058 }; 4059 4060 /* vnic_split_entries (size:128b/16B) */ 4061 struct vnic_split_entries { 4062 __le32 vnic_num_vnic_entries; 4063 __le32 rsvd; 4064 __le32 rsvd2[2]; 4065 }; 4066 4067 /* mrav_split_entries (size:128b/16B) */ 4068 struct mrav_split_entries { 4069 __le32 mrav_num_av_entries; 4070 __le32 rsvd; 4071 __le32 rsvd2[2]; 4072 }; 4073 4074 /* ts_split_entries (size:128b/16B) */ 4075 struct ts_split_entries { 4076 __le32 region_num_entries; 4077 u8 tsid; 4078 u8 lkup_static_bkt_cnt_exp[2]; 4079 u8 locked; 4080 __le32 rsvd2[2]; 4081 }; 4082 4083 /* ck_split_entries (size:128b/16B) */ 4084 struct ck_split_entries { 4085 __le32 num_quic_entries; 4086 __le32 rsvd; 4087 __le32 rsvd2[2]; 4088 }; 4089 4090 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 4091 struct hwrm_func_backing_store_qcaps_v2_input { 4092 __le16 req_type; 4093 __le16 cmpl_ring; 4094 __le16 seq_id; 4095 __le16 target_id; 4096 __le64 resp_addr; 4097 __le16 type; 4098 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 4099 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 4100 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 4101 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 4102 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 4103 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 4104 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 4105 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 4106 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 4107 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 4108 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 4109 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 4110 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 4111 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 4112 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 4113 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 4114 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 4115 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 4116 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 4117 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 4118 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 4119 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 4120 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 4121 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 4122 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 4123 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 4124 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE 0x26UL 4125 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL 4126 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL 4127 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 4128 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4129 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 4130 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 4131 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 4132 u8 rsvd[6]; 4133 }; 4134 4135 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 4136 struct hwrm_func_backing_store_qcaps_v2_output { 4137 __le16 error_code; 4138 __le16 req_type; 4139 __le16 seq_id; 4140 __le16 resp_len; 4141 __le16 type; 4142 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 4143 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 4144 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 4145 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 4146 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 4147 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 4148 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 4149 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 4150 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 4151 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 4152 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 4153 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 4154 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 4155 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 4156 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 4157 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 4158 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 4159 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 4160 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 4161 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 4162 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 4163 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 4164 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 4165 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 4166 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 4167 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 4168 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE 0x26UL 4169 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL 4170 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL 4171 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 4172 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4173 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ERR_QPC_TRACE 0x2bUL 4174 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 4175 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 4176 __le16 entry_size; 4177 __le32 flags; 4178 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 4179 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 4180 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 4181 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 4182 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL 4183 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL 4184 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL 4185 __le32 instance_bit_map; 4186 u8 ctx_init_value; 4187 u8 ctx_init_offset; 4188 u8 entry_multiple; 4189 u8 rsvd; 4190 __le32 max_num_entries; 4191 __le32 min_num_entries; 4192 __le16 next_valid_type; 4193 u8 subtype_valid_cnt; 4194 u8 exact_cnt_bit_map; 4195 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 4196 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 4197 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 4198 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 4199 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 4200 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 4201 __le32 split_entry_0; 4202 __le32 split_entry_1; 4203 __le32 split_entry_2; 4204 __le32 split_entry_3; 4205 __le16 max_instance_count; 4206 u8 rsvd3; 4207 u8 valid; 4208 }; 4209 4210 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 4211 struct hwrm_func_dbr_pacing_qcfg_input { 4212 __le16 req_type; 4213 __le16 cmpl_ring; 4214 __le16 seq_id; 4215 __le16 target_id; 4216 __le64 resp_addr; 4217 }; 4218 4219 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 4220 struct hwrm_func_dbr_pacing_qcfg_output { 4221 __le16 error_code; 4222 __le16 req_type; 4223 __le16 seq_id; 4224 __le16 resp_len; 4225 u8 flags; 4226 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 4227 u8 unused_0[7]; 4228 __le32 dbr_stat_db_fifo_reg; 4229 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 4230 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 4231 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4232 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 4233 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 4234 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 4235 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 4236 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 4237 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 4238 __le32 dbr_stat_db_fifo_reg_watermark_mask; 4239 u8 dbr_stat_db_fifo_reg_watermark_shift; 4240 u8 unused_1[3]; 4241 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 4242 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 4243 u8 unused_2[3]; 4244 __le32 dbr_throttling_aeq_arm_reg; 4245 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 4246 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 4247 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4248 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 4249 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 4250 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 4251 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 4252 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 4253 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 4254 u8 dbr_throttling_aeq_arm_reg_val; 4255 u8 unused_3[3]; 4256 __le32 dbr_stat_db_max_fifo_depth; 4257 __le32 primary_nq_id; 4258 __le32 pacing_threshold; 4259 u8 unused_4[7]; 4260 u8 valid; 4261 }; 4262 4263 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 4264 struct hwrm_func_drv_if_change_input { 4265 __le16 req_type; 4266 __le16 cmpl_ring; 4267 __le16 seq_id; 4268 __le16 target_id; 4269 __le64 resp_addr; 4270 __le32 flags; 4271 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 4272 __le32 unused; 4273 }; 4274 4275 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 4276 struct hwrm_func_drv_if_change_output { 4277 __le16 error_code; 4278 __le16 req_type; 4279 __le16 seq_id; 4280 __le16 resp_len; 4281 __le32 flags; 4282 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4283 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 4284 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4285 u8 unused_0[3]; 4286 u8 valid; 4287 }; 4288 4289 /* hwrm_port_phy_cfg_input (size:512b/64B) */ 4290 struct hwrm_port_phy_cfg_input { 4291 __le16 req_type; 4292 __le16 cmpl_ring; 4293 __le16 seq_id; 4294 __le16 target_id; 4295 __le64 resp_addr; 4296 __le32 flags; 4297 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4298 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4299 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4300 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4301 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4302 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4303 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4304 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4305 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4306 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4307 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4308 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4309 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4310 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4311 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4312 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4313 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4314 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4315 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4316 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4317 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4318 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4319 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4320 #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_ENABLE 0x800000UL 4321 #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_DISABLE 0x1000000UL 4322 #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_ENABLE 0x2000000UL 4323 #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_DISABLE 0x4000000UL 4324 __le32 enables; 4325 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4326 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4327 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4328 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4329 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4330 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4331 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4332 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4333 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4334 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4335 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4336 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4337 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4338 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4339 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4340 __le16 port_id; 4341 __le16 force_link_speed; 4342 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4343 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4344 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4345 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4346 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4347 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4348 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4349 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4350 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4351 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4352 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4353 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4354 u8 auto_mode; 4355 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4356 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4357 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4358 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4359 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4360 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4361 u8 auto_duplex; 4362 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4363 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4364 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4365 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4366 u8 auto_pause; 4367 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4368 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4369 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4370 u8 mgmt_flag; 4371 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4372 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4373 __le16 auto_link_speed; 4374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4375 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4376 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4377 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4378 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4379 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4380 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4381 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4382 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4383 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4384 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4385 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4386 __le16 auto_link_speed_mask; 4387 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4388 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4389 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4390 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4391 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4392 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4393 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4394 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4395 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4396 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4397 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4398 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4399 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4400 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4401 u8 wirespeed; 4402 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4403 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4404 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4405 u8 lpbk; 4406 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4407 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4408 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4409 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4410 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4411 u8 force_pause; 4412 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4413 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4414 u8 unused_1; 4415 __le32 preemphasis; 4416 __le16 eee_link_speed_mask; 4417 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4418 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4419 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4420 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4421 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4422 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4423 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4424 __le16 force_pam4_link_speed; 4425 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4426 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4427 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4428 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4429 __le32 tx_lpi_timer; 4430 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4431 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4432 __le16 auto_link_pam4_speed_mask; 4433 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4434 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4435 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4436 __le16 force_link_speeds2; 4437 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4438 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4439 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4440 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4441 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4442 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4443 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4444 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4445 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4446 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4447 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4448 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4449 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4450 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4451 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4452 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4453 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4454 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4455 __le16 auto_link_speeds2_mask; 4456 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4457 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4458 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4459 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4460 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4461 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4462 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4463 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4464 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4465 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4466 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4467 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4468 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4469 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4470 __le16 auto_link_speeds2_ext_mask; 4471 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_200GB_PAM4_224 0x1UL 4472 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_400GB_PAM4_224 0x2UL 4473 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_800GB_PAM4_224 0x4UL 4474 u8 unused_2[4]; 4475 }; 4476 4477 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 4478 struct hwrm_port_phy_cfg_output { 4479 __le16 error_code; 4480 __le16 req_type; 4481 __le16 seq_id; 4482 __le16 resp_len; 4483 u8 unused_0[7]; 4484 u8 valid; 4485 }; 4486 4487 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4488 struct hwrm_port_phy_cfg_cmd_err { 4489 u8 code; 4490 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4491 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4492 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4493 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4494 u8 unused_0[7]; 4495 }; 4496 4497 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4498 struct hwrm_port_phy_qcfg_input { 4499 __le16 req_type; 4500 __le16 cmpl_ring; 4501 __le16 seq_id; 4502 __le16 target_id; 4503 __le64 resp_addr; 4504 __le16 port_id; 4505 u8 unused_0[6]; 4506 }; 4507 4508 /* hwrm_port_phy_qcfg_output (size:896b/112B) */ 4509 struct hwrm_port_phy_qcfg_output { 4510 __le16 error_code; 4511 __le16 req_type; 4512 __le16 seq_id; 4513 __le16 resp_len; 4514 u8 link; 4515 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4516 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4517 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4518 #define PORT_PHY_QCFG_RESP_LINK_NO_SD 0x3UL 4519 #define PORT_PHY_QCFG_RESP_LINK_NO_LOCK 0x4UL 4520 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_NO_LOCK 4521 u8 active_fec_signal_mode; 4522 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4523 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4524 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4525 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4526 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4527 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 0x3UL 4528 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 4529 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4530 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4531 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4532 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4533 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4534 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4535 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4536 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4537 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4538 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4539 __le16 link_speed; 4540 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4541 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4542 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4543 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4544 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4545 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4546 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4547 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4548 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4549 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4550 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4551 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4552 #define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL 4553 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4554 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4555 u8 duplex_cfg; 4556 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4557 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4558 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4559 u8 pause; 4560 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4561 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4562 __le16 support_speeds; 4563 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4564 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4565 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4566 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4567 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4568 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4569 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4570 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4571 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4572 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4573 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4574 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4575 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4576 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4577 __le16 force_link_speed; 4578 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4579 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4580 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4581 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4582 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4583 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4584 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4585 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4586 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4587 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4588 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4589 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4590 u8 auto_mode; 4591 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4592 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4593 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4594 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4595 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4596 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4597 u8 auto_pause; 4598 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4599 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4600 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4601 __le16 auto_link_speed; 4602 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4603 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4604 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4605 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4606 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4607 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4608 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4609 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4610 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4611 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4612 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4613 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4614 __le16 auto_link_speed_mask; 4615 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4616 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4617 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4618 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4619 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4620 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4621 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4622 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4623 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4624 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4625 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4626 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4627 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4628 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4629 u8 wirespeed; 4630 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4631 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4632 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4633 u8 lpbk; 4634 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4635 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4636 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4637 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4638 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4639 u8 force_pause; 4640 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4641 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4642 u8 module_status; 4643 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4644 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4645 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4646 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4647 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4648 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4649 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED 0x6UL 4650 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4651 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4652 __le32 preemphasis; 4653 u8 phy_maj; 4654 u8 phy_min; 4655 u8 phy_bld; 4656 u8 phy_type; 4657 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4658 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4659 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4660 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4661 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4662 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4663 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4664 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4665 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4666 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4667 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4668 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4669 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4670 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4671 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4672 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4673 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4674 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4675 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4676 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4677 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4678 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4679 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4680 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4681 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4682 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4683 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4684 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4685 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4686 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4687 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4688 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4689 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4690 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4691 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4692 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4693 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4694 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4695 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4696 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4697 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4698 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4699 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4700 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4701 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4702 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4703 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4704 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4705 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4706 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4707 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4708 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4709 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4710 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4711 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4712 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4713 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8 0x38UL 4714 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8 0x39UL 4715 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8 0x3aUL 4716 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4717 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4718 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4719 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEDR4 0x3eUL 4720 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 0x3fUL 4721 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 4722 u8 media_type; 4723 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4724 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4725 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4726 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4727 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL 4728 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 4729 u8 xcvr_pkg_type; 4730 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4731 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4732 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4733 u8 eee_config_phy_addr; 4734 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4735 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4736 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4737 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4738 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4739 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4740 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4741 u8 parallel_detect; 4742 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4743 __le16 link_partner_adv_speeds; 4744 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4745 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4746 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4747 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4748 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4749 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4750 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4751 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4752 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4753 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4754 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4755 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4756 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4757 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4758 u8 link_partner_adv_auto_mode; 4759 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4760 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4761 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4762 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4763 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4764 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4765 u8 link_partner_adv_pause; 4766 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4767 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4768 __le16 adv_eee_link_speed_mask; 4769 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4770 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4771 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4772 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4773 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4774 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4775 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4776 __le16 link_partner_adv_eee_link_speed_mask; 4777 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4778 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4779 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4780 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4781 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4782 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4783 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4784 __le32 xcvr_identifier_type_tx_lpi_timer; 4785 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4786 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4787 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4788 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4789 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4790 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4791 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4792 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4793 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4794 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4795 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4796 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4797 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4798 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4799 __le16 fec_cfg; 4800 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4801 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4802 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4803 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4804 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4805 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4806 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4807 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4808 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4809 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4810 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4811 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4812 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4813 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4814 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4815 u8 duplex_state; 4816 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4817 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4818 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4819 u8 option_flags; 4820 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4821 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4822 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4823 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_LINK_TRAINING 0x8UL 4824 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_PRECODING 0x10UL 4825 char phy_vendor_name[16]; 4826 char phy_vendor_partnumber[16]; 4827 __le16 support_pam4_speeds; 4828 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4829 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4830 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4831 __le16 force_pam4_link_speed; 4832 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4833 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4834 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4835 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4836 __le16 auto_pam4_link_speed_mask; 4837 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4838 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4839 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4840 u8 link_partner_pam4_adv_speeds; 4841 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4842 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4843 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4844 u8 link_down_reason; 4845 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4846 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL 4847 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED 0x4UL 4848 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT 0x8UL 4849 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST 0x10UL 4850 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_TX_LASER_DISABLED 0x20UL 4851 __le16 support_speeds2; 4852 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4853 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4854 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4855 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4856 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4857 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4858 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4859 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4860 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4861 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4862 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4863 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4864 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4865 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4866 __le16 force_link_speeds2; 4867 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4868 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4869 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4870 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4871 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4872 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4873 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4874 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4875 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4876 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4877 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4878 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4879 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4880 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4881 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4882 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4883 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4884 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4885 __le16 auto_link_speeds2; 4886 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4887 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4888 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4889 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4890 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4891 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4892 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4893 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4894 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4895 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4896 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4897 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4898 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4899 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4900 u8 active_lanes; 4901 u8 rsvd1; 4902 __le16 support_speeds2_ext; 4903 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4904 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4905 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4906 __le16 auto_link_speeds2_ext; 4907 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4908 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4909 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4910 u8 rsvd2[3]; 4911 u8 valid; 4912 }; 4913 4914 /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4915 struct hwrm_port_mac_cfg_input { 4916 __le16 req_type; 4917 __le16 cmpl_ring; 4918 __le16 seq_id; 4919 __le16 target_id; 4920 __le64 resp_addr; 4921 __le32 flags; 4922 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4923 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4924 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4925 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4926 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4927 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4928 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4929 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4930 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4931 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4932 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4933 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4934 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4935 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4936 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4937 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4938 __le32 enables; 4939 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4940 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4941 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4942 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4943 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4944 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4945 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4946 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4947 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4948 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4949 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4950 __le16 port_id; 4951 u8 ipg; 4952 u8 lpbk; 4953 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4954 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4955 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4956 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4957 u8 vlan_pri2cos_map_pri; 4958 u8 reserved1; 4959 u8 tunnel_pri2cos_map_pri; 4960 u8 dscp2pri_map_pri; 4961 __le16 rx_ts_capture_ptp_msg_type; 4962 __le16 tx_ts_capture_ptp_msg_type; 4963 u8 cos_field_cfg; 4964 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4965 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4966 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4967 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4968 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4969 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4970 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4971 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4972 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4973 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4974 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4975 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4976 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4977 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4978 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4979 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4980 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4981 u8 unused_0[3]; 4982 __le32 ptp_freq_adj_ppb; 4983 u8 unused_1[3]; 4984 u8 ptp_load_control; 4985 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4986 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4987 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4988 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4989 __le64 ptp_adj_phase; 4990 }; 4991 4992 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4993 struct hwrm_port_mac_cfg_output { 4994 __le16 error_code; 4995 __le16 req_type; 4996 __le16 seq_id; 4997 __le16 resp_len; 4998 __le16 mru; 4999 __le16 mtu; 5000 u8 ipg; 5001 u8 lpbk; 5002 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 5003 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 5004 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 5005 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 5006 u8 unused_0; 5007 u8 valid; 5008 }; 5009 5010 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 5011 struct hwrm_port_mac_ptp_qcfg_input { 5012 __le16 req_type; 5013 __le16 cmpl_ring; 5014 __le16 seq_id; 5015 __le16 target_id; 5016 __le64 resp_addr; 5017 __le16 port_id; 5018 u8 unused_0[6]; 5019 }; 5020 5021 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 5022 struct hwrm_port_mac_ptp_qcfg_output { 5023 __le16 error_code; 5024 __le16 req_type; 5025 __le16 seq_id; 5026 __le16 resp_len; 5027 u8 flags; 5028 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 5029 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 5030 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 5031 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 5032 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 5033 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 5034 u8 unused_0[3]; 5035 __le32 rx_ts_reg_off_lower; 5036 __le32 rx_ts_reg_off_upper; 5037 __le32 rx_ts_reg_off_seq_id; 5038 __le32 rx_ts_reg_off_src_id_0; 5039 __le32 rx_ts_reg_off_src_id_1; 5040 __le32 rx_ts_reg_off_src_id_2; 5041 __le32 rx_ts_reg_off_domain_id; 5042 __le32 rx_ts_reg_off_fifo; 5043 __le32 rx_ts_reg_off_fifo_adv; 5044 __le32 rx_ts_reg_off_granularity; 5045 __le32 tx_ts_reg_off_lower; 5046 __le32 tx_ts_reg_off_upper; 5047 __le32 tx_ts_reg_off_seq_id; 5048 __le32 tx_ts_reg_off_fifo; 5049 __le32 tx_ts_reg_off_granularity; 5050 __le32 ts_ref_clock_reg_lower; 5051 __le32 ts_ref_clock_reg_upper; 5052 u8 unused_1[7]; 5053 u8 valid; 5054 }; 5055 5056 /* tx_port_stats (size:3264b/408B) */ 5057 struct tx_port_stats { 5058 __le64 tx_64b_frames; 5059 __le64 tx_65b_127b_frames; 5060 __le64 tx_128b_255b_frames; 5061 __le64 tx_256b_511b_frames; 5062 __le64 tx_512b_1023b_frames; 5063 __le64 tx_1024b_1518b_frames; 5064 __le64 tx_good_vlan_frames; 5065 __le64 tx_1519b_2047b_frames; 5066 __le64 tx_2048b_4095b_frames; 5067 __le64 tx_4096b_9216b_frames; 5068 __le64 tx_9217b_16383b_frames; 5069 __le64 tx_good_frames; 5070 __le64 tx_total_frames; 5071 __le64 tx_ucast_frames; 5072 __le64 tx_mcast_frames; 5073 __le64 tx_bcast_frames; 5074 __le64 tx_pause_frames; 5075 __le64 tx_pfc_frames; 5076 __le64 tx_jabber_frames; 5077 __le64 tx_fcs_err_frames; 5078 __le64 tx_control_frames; 5079 __le64 tx_oversz_frames; 5080 __le64 tx_single_dfrl_frames; 5081 __le64 tx_multi_dfrl_frames; 5082 __le64 tx_single_coll_frames; 5083 __le64 tx_multi_coll_frames; 5084 __le64 tx_late_coll_frames; 5085 __le64 tx_excessive_coll_frames; 5086 __le64 tx_frag_frames; 5087 __le64 tx_err; 5088 __le64 tx_tagged_frames; 5089 __le64 tx_dbl_tagged_frames; 5090 __le64 tx_runt_frames; 5091 __le64 tx_fifo_underruns; 5092 __le64 tx_pfc_ena_frames_pri0; 5093 __le64 tx_pfc_ena_frames_pri1; 5094 __le64 tx_pfc_ena_frames_pri2; 5095 __le64 tx_pfc_ena_frames_pri3; 5096 __le64 tx_pfc_ena_frames_pri4; 5097 __le64 tx_pfc_ena_frames_pri5; 5098 __le64 tx_pfc_ena_frames_pri6; 5099 __le64 tx_pfc_ena_frames_pri7; 5100 __le64 tx_eee_lpi_events; 5101 __le64 tx_eee_lpi_duration; 5102 __le64 tx_llfc_logical_msgs; 5103 __le64 tx_hcfc_msgs; 5104 __le64 tx_total_collisions; 5105 __le64 tx_bytes; 5106 __le64 tx_xthol_frames; 5107 __le64 tx_stat_discard; 5108 __le64 tx_stat_error; 5109 }; 5110 5111 /* rx_port_stats (size:4224b/528B) */ 5112 struct rx_port_stats { 5113 __le64 rx_64b_frames; 5114 __le64 rx_65b_127b_frames; 5115 __le64 rx_128b_255b_frames; 5116 __le64 rx_256b_511b_frames; 5117 __le64 rx_512b_1023b_frames; 5118 __le64 rx_1024b_1518b_frames; 5119 __le64 rx_good_vlan_frames; 5120 __le64 rx_1519b_2047b_frames; 5121 __le64 rx_2048b_4095b_frames; 5122 __le64 rx_4096b_9216b_frames; 5123 __le64 rx_9217b_16383b_frames; 5124 __le64 rx_total_frames; 5125 __le64 rx_ucast_frames; 5126 __le64 rx_mcast_frames; 5127 __le64 rx_bcast_frames; 5128 __le64 rx_fcs_err_frames; 5129 __le64 rx_ctrl_frames; 5130 __le64 rx_pause_frames; 5131 __le64 rx_pfc_frames; 5132 __le64 rx_unsupported_opcode_frames; 5133 __le64 rx_unsupported_da_pausepfc_frames; 5134 __le64 rx_wrong_sa_frames; 5135 __le64 rx_align_err_frames; 5136 __le64 rx_oor_len_frames; 5137 __le64 rx_code_err_frames; 5138 __le64 rx_false_carrier_frames; 5139 __le64 rx_ovrsz_frames; 5140 __le64 rx_jbr_frames; 5141 __le64 rx_mtu_err_frames; 5142 __le64 rx_match_crc_frames; 5143 __le64 rx_promiscuous_frames; 5144 __le64 rx_tagged_frames; 5145 __le64 rx_double_tagged_frames; 5146 __le64 rx_trunc_frames; 5147 __le64 rx_good_frames; 5148 __le64 rx_pfc_xon2xoff_frames_pri0; 5149 __le64 rx_pfc_xon2xoff_frames_pri1; 5150 __le64 rx_pfc_xon2xoff_frames_pri2; 5151 __le64 rx_pfc_xon2xoff_frames_pri3; 5152 __le64 rx_pfc_xon2xoff_frames_pri4; 5153 __le64 rx_pfc_xon2xoff_frames_pri5; 5154 __le64 rx_pfc_xon2xoff_frames_pri6; 5155 __le64 rx_pfc_xon2xoff_frames_pri7; 5156 __le64 rx_pfc_ena_frames_pri0; 5157 __le64 rx_pfc_ena_frames_pri1; 5158 __le64 rx_pfc_ena_frames_pri2; 5159 __le64 rx_pfc_ena_frames_pri3; 5160 __le64 rx_pfc_ena_frames_pri4; 5161 __le64 rx_pfc_ena_frames_pri5; 5162 __le64 rx_pfc_ena_frames_pri6; 5163 __le64 rx_pfc_ena_frames_pri7; 5164 __le64 rx_sch_crc_err_frames; 5165 __le64 rx_undrsz_frames; 5166 __le64 rx_frag_frames; 5167 __le64 rx_eee_lpi_events; 5168 __le64 rx_eee_lpi_duration; 5169 __le64 rx_llfc_physical_msgs; 5170 __le64 rx_llfc_logical_msgs; 5171 __le64 rx_llfc_msgs_with_crc_err; 5172 __le64 rx_hcfc_msgs; 5173 __le64 rx_hcfc_msgs_with_crc_err; 5174 __le64 rx_bytes; 5175 __le64 rx_runt_bytes; 5176 __le64 rx_runt_frames; 5177 __le64 rx_stat_discard; 5178 __le64 rx_stat_err; 5179 }; 5180 5181 /* hwrm_port_qstats_input (size:320b/40B) */ 5182 struct hwrm_port_qstats_input { 5183 __le16 req_type; 5184 __le16 cmpl_ring; 5185 __le16 seq_id; 5186 __le16 target_id; 5187 __le64 resp_addr; 5188 __le16 port_id; 5189 u8 flags; 5190 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5191 u8 unused_0[5]; 5192 __le64 tx_stat_host_addr; 5193 __le64 rx_stat_host_addr; 5194 }; 5195 5196 /* hwrm_port_qstats_output (size:128b/16B) */ 5197 struct hwrm_port_qstats_output { 5198 __le16 error_code; 5199 __le16 req_type; 5200 __le16 seq_id; 5201 __le16 resp_len; 5202 __le16 tx_stat_size; 5203 __le16 rx_stat_size; 5204 u8 flags; 5205 #define PORT_QSTATS_RESP_FLAGS_CLEARED 0x1UL 5206 u8 unused_0[2]; 5207 u8 valid; 5208 }; 5209 5210 /* tx_port_stats_ext (size:2048b/256B) */ 5211 struct tx_port_stats_ext { 5212 __le64 tx_bytes_cos0; 5213 __le64 tx_bytes_cos1; 5214 __le64 tx_bytes_cos2; 5215 __le64 tx_bytes_cos3; 5216 __le64 tx_bytes_cos4; 5217 __le64 tx_bytes_cos5; 5218 __le64 tx_bytes_cos6; 5219 __le64 tx_bytes_cos7; 5220 __le64 tx_packets_cos0; 5221 __le64 tx_packets_cos1; 5222 __le64 tx_packets_cos2; 5223 __le64 tx_packets_cos3; 5224 __le64 tx_packets_cos4; 5225 __le64 tx_packets_cos5; 5226 __le64 tx_packets_cos6; 5227 __le64 tx_packets_cos7; 5228 __le64 pfc_pri0_tx_duration_us; 5229 __le64 pfc_pri0_tx_transitions; 5230 __le64 pfc_pri1_tx_duration_us; 5231 __le64 pfc_pri1_tx_transitions; 5232 __le64 pfc_pri2_tx_duration_us; 5233 __le64 pfc_pri2_tx_transitions; 5234 __le64 pfc_pri3_tx_duration_us; 5235 __le64 pfc_pri3_tx_transitions; 5236 __le64 pfc_pri4_tx_duration_us; 5237 __le64 pfc_pri4_tx_transitions; 5238 __le64 pfc_pri5_tx_duration_us; 5239 __le64 pfc_pri5_tx_transitions; 5240 __le64 pfc_pri6_tx_duration_us; 5241 __le64 pfc_pri6_tx_transitions; 5242 __le64 pfc_pri7_tx_duration_us; 5243 __le64 pfc_pri7_tx_transitions; 5244 }; 5245 5246 /* rx_port_stats_ext (size:3904b/488B) */ 5247 struct rx_port_stats_ext { 5248 __le64 link_down_events; 5249 __le64 continuous_pause_events; 5250 __le64 resume_pause_events; 5251 __le64 continuous_roce_pause_events; 5252 __le64 resume_roce_pause_events; 5253 __le64 rx_bytes_cos0; 5254 __le64 rx_bytes_cos1; 5255 __le64 rx_bytes_cos2; 5256 __le64 rx_bytes_cos3; 5257 __le64 rx_bytes_cos4; 5258 __le64 rx_bytes_cos5; 5259 __le64 rx_bytes_cos6; 5260 __le64 rx_bytes_cos7; 5261 __le64 rx_packets_cos0; 5262 __le64 rx_packets_cos1; 5263 __le64 rx_packets_cos2; 5264 __le64 rx_packets_cos3; 5265 __le64 rx_packets_cos4; 5266 __le64 rx_packets_cos5; 5267 __le64 rx_packets_cos6; 5268 __le64 rx_packets_cos7; 5269 __le64 pfc_pri0_rx_duration_us; 5270 __le64 pfc_pri0_rx_transitions; 5271 __le64 pfc_pri1_rx_duration_us; 5272 __le64 pfc_pri1_rx_transitions; 5273 __le64 pfc_pri2_rx_duration_us; 5274 __le64 pfc_pri2_rx_transitions; 5275 __le64 pfc_pri3_rx_duration_us; 5276 __le64 pfc_pri3_rx_transitions; 5277 __le64 pfc_pri4_rx_duration_us; 5278 __le64 pfc_pri4_rx_transitions; 5279 __le64 pfc_pri5_rx_duration_us; 5280 __le64 pfc_pri5_rx_transitions; 5281 __le64 pfc_pri6_rx_duration_us; 5282 __le64 pfc_pri6_rx_transitions; 5283 __le64 pfc_pri7_rx_duration_us; 5284 __le64 pfc_pri7_rx_transitions; 5285 __le64 rx_bits; 5286 __le64 rx_buffer_passed_threshold; 5287 __le64 rx_pcs_symbol_err; 5288 __le64 rx_corrected_bits; 5289 __le64 rx_discard_bytes_cos0; 5290 __le64 rx_discard_bytes_cos1; 5291 __le64 rx_discard_bytes_cos2; 5292 __le64 rx_discard_bytes_cos3; 5293 __le64 rx_discard_bytes_cos4; 5294 __le64 rx_discard_bytes_cos5; 5295 __le64 rx_discard_bytes_cos6; 5296 __le64 rx_discard_bytes_cos7; 5297 __le64 rx_discard_packets_cos0; 5298 __le64 rx_discard_packets_cos1; 5299 __le64 rx_discard_packets_cos2; 5300 __le64 rx_discard_packets_cos3; 5301 __le64 rx_discard_packets_cos4; 5302 __le64 rx_discard_packets_cos5; 5303 __le64 rx_discard_packets_cos6; 5304 __le64 rx_discard_packets_cos7; 5305 __le64 rx_fec_corrected_blocks; 5306 __le64 rx_fec_uncorrectable_blocks; 5307 __le64 rx_filter_miss; 5308 __le64 rx_fec_symbol_err; 5309 }; 5310 5311 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 5312 struct hwrm_port_qstats_ext_input { 5313 __le16 req_type; 5314 __le16 cmpl_ring; 5315 __le16 seq_id; 5316 __le16 target_id; 5317 __le64 resp_addr; 5318 __le16 port_id; 5319 __le16 tx_stat_size; 5320 __le16 rx_stat_size; 5321 u8 flags; 5322 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 5323 u8 unused_0; 5324 __le64 tx_stat_host_addr; 5325 __le64 rx_stat_host_addr; 5326 }; 5327 5328 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 5329 struct hwrm_port_qstats_ext_output { 5330 __le16 error_code; 5331 __le16 req_type; 5332 __le16 seq_id; 5333 __le16 resp_len; 5334 __le16 tx_stat_size; 5335 __le16 rx_stat_size; 5336 __le16 total_active_cos_queues; 5337 u8 flags; 5338 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5339 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED 0x2UL 5340 u8 valid; 5341 }; 5342 5343 /* hwrm_port_lpbk_qstats_input (size:256b/32B) */ 5344 struct hwrm_port_lpbk_qstats_input { 5345 __le16 req_type; 5346 __le16 cmpl_ring; 5347 __le16 seq_id; 5348 __le16 target_id; 5349 __le64 resp_addr; 5350 __le16 lpbk_stat_size; 5351 u8 flags; 5352 #define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5353 u8 unused_0[5]; 5354 __le64 lpbk_stat_host_addr; 5355 }; 5356 5357 /* hwrm_port_lpbk_qstats_output (size:128b/16B) */ 5358 struct hwrm_port_lpbk_qstats_output { 5359 __le16 error_code; 5360 __le16 req_type; 5361 __le16 seq_id; 5362 __le16 resp_len; 5363 __le16 lpbk_stat_size; 5364 u8 unused_0[5]; 5365 u8 valid; 5366 }; 5367 5368 /* port_lpbk_stats (size:640b/80B) */ 5369 struct port_lpbk_stats { 5370 __le64 lpbk_ucast_frames; 5371 __le64 lpbk_mcast_frames; 5372 __le64 lpbk_bcast_frames; 5373 __le64 lpbk_ucast_bytes; 5374 __le64 lpbk_mcast_bytes; 5375 __le64 lpbk_bcast_bytes; 5376 __le64 lpbk_tx_discards; 5377 __le64 lpbk_tx_errors; 5378 __le64 lpbk_rx_discards; 5379 __le64 lpbk_rx_errors; 5380 }; 5381 5382 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5383 struct hwrm_port_ecn_qstats_input { 5384 __le16 req_type; 5385 __le16 cmpl_ring; 5386 __le16 seq_id; 5387 __le16 target_id; 5388 __le64 resp_addr; 5389 __le16 port_id; 5390 __le16 ecn_stat_buf_size; 5391 u8 flags; 5392 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5393 u8 unused_0[3]; 5394 __le64 ecn_stat_host_addr; 5395 }; 5396 5397 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5398 struct hwrm_port_ecn_qstats_output { 5399 __le16 error_code; 5400 __le16 req_type; 5401 __le16 seq_id; 5402 __le16 resp_len; 5403 __le16 ecn_stat_buf_size; 5404 u8 mark_en; 5405 u8 unused_0[4]; 5406 u8 valid; 5407 }; 5408 5409 /* port_stats_ecn (size:512b/64B) */ 5410 struct port_stats_ecn { 5411 __le64 mark_cnt_cos0; 5412 __le64 mark_cnt_cos1; 5413 __le64 mark_cnt_cos2; 5414 __le64 mark_cnt_cos3; 5415 __le64 mark_cnt_cos4; 5416 __le64 mark_cnt_cos5; 5417 __le64 mark_cnt_cos6; 5418 __le64 mark_cnt_cos7; 5419 }; 5420 5421 /* hwrm_port_clr_stats_input (size:192b/24B) */ 5422 struct hwrm_port_clr_stats_input { 5423 __le16 req_type; 5424 __le16 cmpl_ring; 5425 __le16 seq_id; 5426 __le16 target_id; 5427 __le64 resp_addr; 5428 __le16 port_id; 5429 u8 flags; 5430 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5431 u8 unused_0[5]; 5432 }; 5433 5434 /* hwrm_port_clr_stats_output (size:128b/16B) */ 5435 struct hwrm_port_clr_stats_output { 5436 __le16 error_code; 5437 __le16 req_type; 5438 __le16 seq_id; 5439 __le16 resp_len; 5440 u8 unused_0[7]; 5441 u8 valid; 5442 }; 5443 5444 /* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ 5445 struct hwrm_port_lpbk_clr_stats_input { 5446 __le16 req_type; 5447 __le16 cmpl_ring; 5448 __le16 seq_id; 5449 __le16 target_id; 5450 __le64 resp_addr; 5451 __le16 port_id; 5452 u8 unused_0[6]; 5453 }; 5454 5455 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5456 struct hwrm_port_lpbk_clr_stats_output { 5457 __le16 error_code; 5458 __le16 req_type; 5459 __le16 seq_id; 5460 __le16 resp_len; 5461 u8 unused_0[7]; 5462 u8 valid; 5463 }; 5464 5465 /* hwrm_port_ts_query_input (size:320b/40B) */ 5466 struct hwrm_port_ts_query_input { 5467 __le16 req_type; 5468 __le16 cmpl_ring; 5469 __le16 seq_id; 5470 __le16 target_id; 5471 __le64 resp_addr; 5472 __le32 flags; 5473 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5474 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5475 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5476 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5477 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5478 __le16 port_id; 5479 u8 unused_0[2]; 5480 __le16 enables; 5481 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5482 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5483 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5484 __le16 ts_req_timeout; 5485 __le32 ptp_seq_id; 5486 __le16 ptp_hdr_offset; 5487 u8 unused_1[6]; 5488 }; 5489 5490 /* hwrm_port_ts_query_output (size:192b/24B) */ 5491 struct hwrm_port_ts_query_output { 5492 __le16 error_code; 5493 __le16 req_type; 5494 __le16 seq_id; 5495 __le16 resp_len; 5496 __le64 ptp_msg_ts; 5497 __le16 ptp_msg_seqid; 5498 u8 unused_0[5]; 5499 u8 valid; 5500 }; 5501 5502 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5503 struct hwrm_port_phy_qcaps_input { 5504 __le16 req_type; 5505 __le16 cmpl_ring; 5506 __le16 seq_id; 5507 __le16 target_id; 5508 __le64 resp_addr; 5509 __le16 port_id; 5510 u8 unused_0[6]; 5511 }; 5512 5513 /* hwrm_port_phy_qcaps_output (size:384b/48B) */ 5514 struct hwrm_port_phy_qcaps_output { 5515 __le16 error_code; 5516 __le16 req_type; 5517 __le16 seq_id; 5518 __le16 resp_len; 5519 u8 flags; 5520 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5521 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5522 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5523 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5524 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5525 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5526 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5527 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5528 u8 port_cnt; 5529 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5530 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5531 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5532 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5533 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5534 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5535 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5536 __le16 supported_speeds_force_mode; 5537 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5538 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5539 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5540 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5541 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5542 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5543 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5544 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5545 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5546 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5547 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5548 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5549 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5550 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5551 __le16 supported_speeds_auto_mode; 5552 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5553 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5554 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5555 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5556 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5557 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5558 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5559 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5560 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5561 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5562 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5563 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5564 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5565 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5566 __le16 supported_speeds_eee_mode; 5567 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5568 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5569 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5570 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5571 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5572 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5573 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5574 __le32 tx_lpi_timer_low; 5575 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5576 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5577 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5578 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5579 __le32 valid_tx_lpi_timer_high; 5580 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5581 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5582 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5583 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5584 __le16 supported_pam4_speeds_auto_mode; 5585 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5586 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5587 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5588 __le16 supported_pam4_speeds_force_mode; 5589 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5590 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5591 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5592 __le16 flags2; 5593 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5594 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5595 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5596 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5597 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5598 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_ADV_STATS_SUPPORTED 0x20UL 5599 #define PORT_PHY_QCAPS_RESP_FLAGS2_ADSM_REPORT_SUPPORTED 0x40UL 5600 #define PORT_PHY_QCAPS_RESP_FLAGS2_PM_EVENT_LOG_SUPPORTED 0x80UL 5601 #define PORT_PHY_QCAPS_RESP_FLAGS2_FDRSTAT_CMD_SUPPORTED 0x100UL 5602 u8 internal_port_cnt; 5603 u8 unused_0; 5604 __le16 supported_speeds2_force_mode; 5605 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5606 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5607 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5608 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5609 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5610 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5611 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5612 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5613 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5614 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5615 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5616 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5617 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5618 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5619 __le16 supported_speeds2_auto_mode; 5620 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5621 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5622 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5623 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5624 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5625 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5626 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5627 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5628 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5629 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5630 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5631 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5632 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5633 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5634 __le16 supported_speeds2_ext_force_mode; 5635 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_200GB_PAM4_224 0x1UL 5636 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_400GB_PAM4_224 0x2UL 5637 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_800GB_PAM4_224 0x4UL 5638 __le16 supported_speeds2_ext_auto_mode; 5639 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_200GB_PAM4_224 0x1UL 5640 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_400GB_PAM4_224 0x2UL 5641 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_800GB_PAM4_224 0x4UL 5642 u8 unused_1[7]; 5643 u8 valid; 5644 }; 5645 5646 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */ 5647 struct hwrm_port_phy_i2c_write_input { 5648 __le16 req_type; 5649 __le16 cmpl_ring; 5650 __le16 seq_id; 5651 __le16 target_id; 5652 __le64 resp_addr; 5653 __le32 flags; 5654 __le32 enables; 5655 #define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL 5656 #define PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER 0x2UL 5657 __le16 port_id; 5658 u8 i2c_slave_addr; 5659 u8 bank_number; 5660 __le16 page_number; 5661 __le16 page_offset; 5662 u8 data_length; 5663 u8 unused_1[7]; 5664 __le32 data[16]; 5665 }; 5666 5667 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */ 5668 struct hwrm_port_phy_i2c_write_output { 5669 __le16 error_code; 5670 __le16 req_type; 5671 __le16 seq_id; 5672 __le16 resp_len; 5673 u8 unused_0[7]; 5674 u8 valid; 5675 }; 5676 5677 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5678 struct hwrm_port_phy_i2c_read_input { 5679 __le16 req_type; 5680 __le16 cmpl_ring; 5681 __le16 seq_id; 5682 __le16 target_id; 5683 __le64 resp_addr; 5684 __le32 flags; 5685 __le32 enables; 5686 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5687 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5688 __le16 port_id; 5689 u8 i2c_slave_addr; 5690 u8 bank_number; 5691 __le16 page_number; 5692 __le16 page_offset; 5693 u8 data_length; 5694 u8 unused_1[7]; 5695 }; 5696 5697 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5698 struct hwrm_port_phy_i2c_read_output { 5699 __le16 error_code; 5700 __le16 req_type; 5701 __le16 seq_id; 5702 __le16 resp_len; 5703 __le32 data[16]; 5704 u8 unused_0[7]; 5705 u8 valid; 5706 }; 5707 5708 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5709 struct hwrm_port_phy_mdio_write_input { 5710 __le16 req_type; 5711 __le16 cmpl_ring; 5712 __le16 seq_id; 5713 __le16 target_id; 5714 __le64 resp_addr; 5715 __le32 unused_0[2]; 5716 __le16 port_id; 5717 u8 phy_addr; 5718 u8 dev_addr; 5719 __le16 reg_addr; 5720 __le16 reg_data; 5721 u8 cl45_mdio; 5722 u8 unused_1[7]; 5723 }; 5724 5725 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5726 struct hwrm_port_phy_mdio_write_output { 5727 __le16 error_code; 5728 __le16 req_type; 5729 __le16 seq_id; 5730 __le16 resp_len; 5731 u8 unused_0[7]; 5732 u8 valid; 5733 }; 5734 5735 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5736 struct hwrm_port_phy_mdio_read_input { 5737 __le16 req_type; 5738 __le16 cmpl_ring; 5739 __le16 seq_id; 5740 __le16 target_id; 5741 __le64 resp_addr; 5742 __le32 unused_0[2]; 5743 __le16 port_id; 5744 u8 phy_addr; 5745 u8 dev_addr; 5746 __le16 reg_addr; 5747 u8 cl45_mdio; 5748 u8 unused_1; 5749 }; 5750 5751 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5752 struct hwrm_port_phy_mdio_read_output { 5753 __le16 error_code; 5754 __le16 req_type; 5755 __le16 seq_id; 5756 __le16 resp_len; 5757 __le16 reg_data; 5758 u8 unused_0[5]; 5759 u8 valid; 5760 }; 5761 5762 /* hwrm_port_led_cfg_input (size:512b/64B) */ 5763 struct hwrm_port_led_cfg_input { 5764 __le16 req_type; 5765 __le16 cmpl_ring; 5766 __le16 seq_id; 5767 __le16 target_id; 5768 __le64 resp_addr; 5769 __le32 enables; 5770 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5771 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5772 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5773 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5774 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5775 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5776 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5777 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5778 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5779 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5780 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5781 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5782 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5783 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5784 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5785 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5786 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5787 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5788 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5789 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5790 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5791 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5792 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5793 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5794 __le16 port_id; 5795 u8 num_leds; 5796 u8 rsvd; 5797 u8 led0_id; 5798 u8 led0_state; 5799 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5800 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5801 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5802 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5803 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5804 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5805 u8 led0_color; 5806 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5807 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5808 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5809 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5810 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5811 u8 unused_0; 5812 __le16 led0_blink_on; 5813 __le16 led0_blink_off; 5814 u8 led0_group_id; 5815 u8 rsvd0; 5816 u8 led1_id; 5817 u8 led1_state; 5818 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5819 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5820 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5821 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5822 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5823 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5824 u8 led1_color; 5825 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5826 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5827 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5828 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5829 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5830 u8 unused_1; 5831 __le16 led1_blink_on; 5832 __le16 led1_blink_off; 5833 u8 led1_group_id; 5834 u8 rsvd1; 5835 u8 led2_id; 5836 u8 led2_state; 5837 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5838 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5839 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5840 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5841 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5842 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5843 u8 led2_color; 5844 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5845 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5846 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5847 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5848 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5849 u8 unused_2; 5850 __le16 led2_blink_on; 5851 __le16 led2_blink_off; 5852 u8 led2_group_id; 5853 u8 rsvd2; 5854 u8 led3_id; 5855 u8 led3_state; 5856 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5857 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5858 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5859 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5860 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5861 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5862 u8 led3_color; 5863 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5864 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5865 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5866 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5867 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5868 u8 unused_3; 5869 __le16 led3_blink_on; 5870 __le16 led3_blink_off; 5871 u8 led3_group_id; 5872 u8 rsvd3; 5873 }; 5874 5875 /* hwrm_port_led_cfg_output (size:128b/16B) */ 5876 struct hwrm_port_led_cfg_output { 5877 __le16 error_code; 5878 __le16 req_type; 5879 __le16 seq_id; 5880 __le16 resp_len; 5881 u8 unused_0[7]; 5882 u8 valid; 5883 }; 5884 5885 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5886 struct hwrm_port_led_qcfg_input { 5887 __le16 req_type; 5888 __le16 cmpl_ring; 5889 __le16 seq_id; 5890 __le16 target_id; 5891 __le64 resp_addr; 5892 __le16 port_id; 5893 u8 unused_0[6]; 5894 }; 5895 5896 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5897 struct hwrm_port_led_qcfg_output { 5898 __le16 error_code; 5899 __le16 req_type; 5900 __le16 seq_id; 5901 __le16 resp_len; 5902 u8 num_leds; 5903 u8 led0_id; 5904 u8 led0_type; 5905 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5906 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5907 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5908 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5909 u8 led0_state; 5910 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5911 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5912 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5913 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5914 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5915 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5916 u8 led0_color; 5917 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5918 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5919 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5920 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5921 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5922 u8 unused_0; 5923 __le16 led0_blink_on; 5924 __le16 led0_blink_off; 5925 u8 led0_group_id; 5926 u8 led1_id; 5927 u8 led1_type; 5928 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5929 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5930 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5931 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5932 u8 led1_state; 5933 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5934 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5935 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5936 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5937 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5938 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5939 u8 led1_color; 5940 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5941 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5942 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5943 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5944 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5945 u8 unused_1; 5946 __le16 led1_blink_on; 5947 __le16 led1_blink_off; 5948 u8 led1_group_id; 5949 u8 led2_id; 5950 u8 led2_type; 5951 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5952 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5953 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5954 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5955 u8 led2_state; 5956 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5957 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5958 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5959 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5960 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5961 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5962 u8 led2_color; 5963 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5964 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5965 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5966 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5967 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5968 u8 unused_2; 5969 __le16 led2_blink_on; 5970 __le16 led2_blink_off; 5971 u8 led2_group_id; 5972 u8 led3_id; 5973 u8 led3_type; 5974 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5975 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5976 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5977 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5978 u8 led3_state; 5979 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5980 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5981 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5982 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5983 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5984 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5985 u8 led3_color; 5986 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5987 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5988 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5989 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5990 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5991 u8 unused_3; 5992 __le16 led3_blink_on; 5993 __le16 led3_blink_off; 5994 u8 led3_group_id; 5995 u8 unused_4[6]; 5996 u8 valid; 5997 }; 5998 5999 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 6000 struct hwrm_port_led_qcaps_input { 6001 __le16 req_type; 6002 __le16 cmpl_ring; 6003 __le16 seq_id; 6004 __le16 target_id; 6005 __le64 resp_addr; 6006 __le16 port_id; 6007 u8 unused_0[6]; 6008 }; 6009 6010 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 6011 struct hwrm_port_led_qcaps_output { 6012 __le16 error_code; 6013 __le16 req_type; 6014 __le16 seq_id; 6015 __le16 resp_len; 6016 u8 num_leds; 6017 u8 unused[3]; 6018 u8 led0_id; 6019 u8 led0_type; 6020 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 6021 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 6022 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 6023 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 6024 u8 led0_group_id; 6025 u8 unused_0; 6026 __le16 led0_state_caps; 6027 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 6028 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 6029 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 6030 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6031 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6032 __le16 led0_color_caps; 6033 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 6034 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6035 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6036 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6037 u8 led1_id; 6038 u8 led1_type; 6039 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 6040 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 6041 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 6042 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 6043 u8 led1_group_id; 6044 u8 unused_1; 6045 __le16 led1_state_caps; 6046 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 6047 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 6048 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 6049 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6050 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6051 __le16 led1_color_caps; 6052 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 6053 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6054 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6055 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6056 u8 led2_id; 6057 u8 led2_type; 6058 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 6059 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 6060 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 6061 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 6062 u8 led2_group_id; 6063 u8 unused_2; 6064 __le16 led2_state_caps; 6065 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 6066 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 6067 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 6068 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6069 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6070 __le16 led2_color_caps; 6071 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 6072 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6073 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6074 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6075 u8 led3_id; 6076 u8 led3_type; 6077 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 6078 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 6079 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 6080 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 6081 u8 led3_group_id; 6082 u8 unused_3; 6083 __le16 led3_state_caps; 6084 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 6085 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 6086 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 6087 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6088 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6089 __le16 led3_color_caps; 6090 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 6091 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6092 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6093 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6094 u8 unused_4[3]; 6095 u8 valid; 6096 }; 6097 6098 /* hwrm_port_phy_fdrstat_input (size:192b/24B) */ 6099 struct hwrm_port_phy_fdrstat_input { 6100 __le16 req_type; 6101 __le16 cmpl_ring; 6102 __le16 seq_id; 6103 __le16 target_id; 6104 __le64 resp_addr; 6105 __le16 port_id; 6106 __le16 rsvd[2]; 6107 __le16 ops; 6108 #define PORT_PHY_FDRSTAT_REQ_OPS_START 0x0UL 6109 #define PORT_PHY_FDRSTAT_REQ_OPS_STOP 0x1UL 6110 #define PORT_PHY_FDRSTAT_REQ_OPS_CLEAR 0x2UL 6111 #define PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 0x3UL 6112 #define PORT_PHY_FDRSTAT_REQ_OPS_LAST PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 6113 }; 6114 6115 /* hwrm_port_phy_fdrstat_output (size:3072b/384B) */ 6116 struct hwrm_port_phy_fdrstat_output { 6117 __le16 error_code; 6118 __le16 req_type; 6119 __le16 seq_id; 6120 __le16 resp_len; 6121 __le64 start_time; 6122 __le64 end_time; 6123 __le64 cmic_start_time; 6124 __le64 cmic_end_time; 6125 __le64 accumulated_uncorrected_codewords; 6126 __le64 accumulated_corrected_codewords; 6127 __le64 accumulated_total_codewords; 6128 __le64 accumulated_symbol_errors; 6129 __le64 accumulated_codewords_err_s[17]; 6130 __le64 uncorrected_codewords; 6131 __le64 corrected_codewords; 6132 __le64 total_codewords; 6133 __le64 symbol_errors; 6134 __le64 codewords_err_s[17]; 6135 __le32 window_size; 6136 __le16 unused_0[1]; 6137 u8 unused_1; 6138 u8 valid; 6139 }; 6140 6141 /* hwrm_port_phy_fdrstat_cmd_err (size:64b/8B) */ 6142 struct hwrm_port_phy_fdrstat_cmd_err { 6143 u8 code; 6144 #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_UNKNOWN 0x0UL 6145 #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 0x1UL 6146 #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_LAST PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 6147 u8 unused_0[7]; 6148 }; 6149 6150 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ 6151 struct hwrm_port_mac_qcaps_input { 6152 __le16 req_type; 6153 __le16 cmpl_ring; 6154 __le16 seq_id; 6155 __le16 target_id; 6156 __le64 resp_addr; 6157 __le16 port_id; 6158 u8 unused_0[6]; 6159 }; 6160 6161 /* hwrm_port_mac_qcaps_output (size:128b/16B) */ 6162 struct hwrm_port_mac_qcaps_output { 6163 __le16 error_code; 6164 __le16 req_type; 6165 __le16 seq_id; 6166 __le16 resp_len; 6167 u8 flags; 6168 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 6169 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 6170 u8 unused_0[6]; 6171 u8 valid; 6172 }; 6173 6174 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 6175 struct hwrm_queue_qportcfg_input { 6176 __le16 req_type; 6177 __le16 cmpl_ring; 6178 __le16 seq_id; 6179 __le16 target_id; 6180 __le64 resp_addr; 6181 __le32 flags; 6182 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 6183 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 6184 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 6185 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 6186 __le16 port_id; 6187 u8 drv_qmap_cap; 6188 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 6189 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 6190 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 6191 u8 unused_0; 6192 }; 6193 6194 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 6195 struct hwrm_queue_qportcfg_output { 6196 __le16 error_code; 6197 __le16 req_type; 6198 __le16 seq_id; 6199 __le16 resp_len; 6200 u8 max_configurable_queues; 6201 u8 max_configurable_lossless_queues; 6202 u8 queue_cfg_allowed; 6203 u8 queue_cfg_info; 6204 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6205 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 6206 u8 queue_pfcenable_cfg_allowed; 6207 u8 queue_pri2cos_cfg_allowed; 6208 u8 queue_cos2bw_cfg_allowed; 6209 u8 queue_id0; 6210 u8 queue_id0_service_profile; 6211 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 6212 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 6213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 6217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 6218 u8 queue_id1; 6219 u8 queue_id1_service_profile; 6220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 6221 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 6222 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 6226 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 6227 u8 queue_id2; 6228 u8 queue_id2_service_profile; 6229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 6230 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 6231 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6232 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 6235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 6236 u8 queue_id3; 6237 u8 queue_id3_service_profile; 6238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 6239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 6240 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6241 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 6244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 6245 u8 queue_id4; 6246 u8 queue_id4_service_profile; 6247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 6248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 6249 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6250 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6251 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6252 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 6253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 6254 u8 queue_id5; 6255 u8 queue_id5_service_profile; 6256 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 6257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 6258 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6259 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6260 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 6262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 6263 u8 queue_id6; 6264 u8 queue_id6_service_profile; 6265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 6266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 6267 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6268 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6269 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6270 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 6271 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 6272 u8 queue_id7; 6273 u8 queue_id7_service_profile; 6274 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 6275 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 6276 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6277 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6278 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 6280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 6281 u8 queue_id0_service_profile_type; 6282 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6283 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 6284 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 6285 char qid0_name[16]; 6286 char qid1_name[16]; 6287 char qid2_name[16]; 6288 char qid3_name[16]; 6289 char qid4_name[16]; 6290 char qid5_name[16]; 6291 char qid6_name[16]; 6292 char qid7_name[16]; 6293 u8 queue_id1_service_profile_type; 6294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 6296 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 6297 u8 queue_id2_service_profile_type; 6298 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6299 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 6300 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 6301 u8 queue_id3_service_profile_type; 6302 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6303 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 6304 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 6305 u8 queue_id4_service_profile_type; 6306 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6307 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 6308 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 6309 u8 queue_id5_service_profile_type; 6310 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6311 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 6312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 6313 u8 queue_id6_service_profile_type; 6314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6315 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 6316 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 6317 u8 queue_id7_service_profile_type; 6318 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6319 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 6320 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 6321 u8 valid; 6322 }; 6323 6324 /* hwrm_queue_qcfg_input (size:192b/24B) */ 6325 struct hwrm_queue_qcfg_input { 6326 __le16 req_type; 6327 __le16 cmpl_ring; 6328 __le16 seq_id; 6329 __le16 target_id; 6330 __le64 resp_addr; 6331 __le32 flags; 6332 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 6333 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6334 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6335 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 6336 __le32 queue_id; 6337 }; 6338 6339 /* hwrm_queue_qcfg_output (size:128b/16B) */ 6340 struct hwrm_queue_qcfg_output { 6341 __le16 error_code; 6342 __le16 req_type; 6343 __le16 seq_id; 6344 __le16 resp_len; 6345 __le32 queue_len; 6346 u8 service_profile; 6347 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 6348 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 6349 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 6350 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 6351 u8 queue_cfg_info; 6352 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6353 u8 unused_0; 6354 u8 valid; 6355 }; 6356 6357 /* hwrm_queue_cfg_input (size:320b/40B) */ 6358 struct hwrm_queue_cfg_input { 6359 __le16 req_type; 6360 __le16 cmpl_ring; 6361 __le16 seq_id; 6362 __le16 target_id; 6363 __le64 resp_addr; 6364 __le32 flags; 6365 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6366 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 6367 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 6368 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 6369 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6370 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 6371 __le32 enables; 6372 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 6373 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 6374 __le32 queue_id; 6375 __le32 dflt_len; 6376 u8 service_profile; 6377 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 6378 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 6379 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 6380 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 6381 u8 unused_0[7]; 6382 }; 6383 6384 /* hwrm_queue_cfg_output (size:128b/16B) */ 6385 struct hwrm_queue_cfg_output { 6386 __le16 error_code; 6387 __le16 req_type; 6388 __le16 seq_id; 6389 __le16 resp_len; 6390 u8 unused_0[7]; 6391 u8 valid; 6392 }; 6393 6394 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 6395 struct hwrm_queue_pfcenable_qcfg_input { 6396 __le16 req_type; 6397 __le16 cmpl_ring; 6398 __le16 seq_id; 6399 __le16 target_id; 6400 __le64 resp_addr; 6401 __le16 port_id; 6402 u8 unused_0[6]; 6403 }; 6404 6405 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 6406 struct hwrm_queue_pfcenable_qcfg_output { 6407 __le16 error_code; 6408 __le16 req_type; 6409 __le16 seq_id; 6410 __le16 resp_len; 6411 __le32 flags; 6412 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 6413 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 6414 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 6415 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 6416 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 6417 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 6418 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 6419 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 6420 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6421 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6422 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6423 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6424 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6425 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6426 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6427 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6428 u8 unused_0[3]; 6429 u8 valid; 6430 }; 6431 6432 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 6433 struct hwrm_queue_pfcenable_cfg_input { 6434 __le16 req_type; 6435 __le16 cmpl_ring; 6436 __le16 seq_id; 6437 __le16 target_id; 6438 __le64 resp_addr; 6439 __le32 flags; 6440 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 6441 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 6442 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 6443 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 6444 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 6445 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 6446 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 6447 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 6448 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6449 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6450 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6451 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6452 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6453 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6454 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6455 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6456 __le16 port_id; 6457 u8 unused_0[2]; 6458 }; 6459 6460 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6461 struct hwrm_queue_pfcenable_cfg_output { 6462 __le16 error_code; 6463 __le16 req_type; 6464 __le16 seq_id; 6465 __le16 resp_len; 6466 u8 unused_0[7]; 6467 u8 valid; 6468 }; 6469 6470 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6471 struct hwrm_queue_pri2cos_qcfg_input { 6472 __le16 req_type; 6473 __le16 cmpl_ring; 6474 __le16 seq_id; 6475 __le16 target_id; 6476 __le64 resp_addr; 6477 __le32 flags; 6478 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6479 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6480 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6481 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6482 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6483 u8 port_id; 6484 u8 unused_0[3]; 6485 }; 6486 6487 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6488 struct hwrm_queue_pri2cos_qcfg_output { 6489 __le16 error_code; 6490 __le16 req_type; 6491 __le16 seq_id; 6492 __le16 resp_len; 6493 u8 pri0_cos_queue_id; 6494 u8 pri1_cos_queue_id; 6495 u8 pri2_cos_queue_id; 6496 u8 pri3_cos_queue_id; 6497 u8 pri4_cos_queue_id; 6498 u8 pri5_cos_queue_id; 6499 u8 pri6_cos_queue_id; 6500 u8 pri7_cos_queue_id; 6501 u8 queue_cfg_info; 6502 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6503 u8 unused_0[6]; 6504 u8 valid; 6505 }; 6506 6507 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6508 struct hwrm_queue_pri2cos_cfg_input { 6509 __le16 req_type; 6510 __le16 cmpl_ring; 6511 __le16 seq_id; 6512 __le16 target_id; 6513 __le64 resp_addr; 6514 __le32 flags; 6515 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6516 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6517 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6518 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6519 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6520 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6521 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6522 __le32 enables; 6523 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6524 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6525 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6526 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6527 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6528 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6529 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6530 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6531 u8 port_id; 6532 u8 pri0_cos_queue_id; 6533 u8 pri1_cos_queue_id; 6534 u8 pri2_cos_queue_id; 6535 u8 pri3_cos_queue_id; 6536 u8 pri4_cos_queue_id; 6537 u8 pri5_cos_queue_id; 6538 u8 pri6_cos_queue_id; 6539 u8 pri7_cos_queue_id; 6540 u8 unused_0[7]; 6541 }; 6542 6543 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6544 struct hwrm_queue_pri2cos_cfg_output { 6545 __le16 error_code; 6546 __le16 req_type; 6547 __le16 seq_id; 6548 __le16 resp_len; 6549 u8 unused_0[7]; 6550 u8 valid; 6551 }; 6552 6553 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6554 struct hwrm_queue_cos2bw_qcfg_input { 6555 __le16 req_type; 6556 __le16 cmpl_ring; 6557 __le16 seq_id; 6558 __le16 target_id; 6559 __le64 resp_addr; 6560 __le16 port_id; 6561 u8 unused_0[6]; 6562 }; 6563 6564 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6565 struct hwrm_queue_cos2bw_qcfg_output { 6566 __le16 error_code; 6567 __le16 req_type; 6568 __le16 seq_id; 6569 __le16 resp_len; 6570 u8 queue_id0; 6571 u8 unused_0; 6572 __le16 unused_1; 6573 __le32 queue_id0_min_bw; 6574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6589 __le32 queue_id0_max_bw; 6590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6605 u8 queue_id0_tsa_assign; 6606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6610 u8 queue_id0_pri_lvl; 6611 u8 queue_id0_bw_weight; 6612 struct { 6613 u8 queue_id; 6614 __le32 queue_id_min_bw; 6615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6630 __le32 queue_id_max_bw; 6631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6646 u8 queue_id_tsa_assign; 6647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6651 u8 queue_id_pri_lvl; 6652 u8 queue_id_bw_weight; 6653 } __packed cfg[7]; 6654 u8 unused_2[4]; 6655 u8 valid; 6656 }; 6657 6658 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6659 struct hwrm_queue_cos2bw_cfg_input { 6660 __le16 req_type; 6661 __le16 cmpl_ring; 6662 __le16 seq_id; 6663 __le16 target_id; 6664 __le64 resp_addr; 6665 __le32 flags; 6666 __le32 enables; 6667 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6668 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6669 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6670 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6671 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6672 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6673 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6674 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6675 __le16 port_id; 6676 u8 queue_id0; 6677 u8 unused_0; 6678 __le32 queue_id0_min_bw; 6679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6684 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6689 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6694 __le32 queue_id0_max_bw; 6695 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6696 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6697 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6698 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6700 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6701 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6702 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6703 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6704 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6705 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6706 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6707 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6708 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6710 u8 queue_id0_tsa_assign; 6711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6713 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6715 u8 queue_id0_pri_lvl; 6716 u8 queue_id0_bw_weight; 6717 struct { 6718 u8 queue_id; 6719 __le32 queue_id_min_bw; 6720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6721 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6722 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6723 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6724 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6735 __le32 queue_id_max_bw; 6736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6740 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6743 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6751 u8 queue_id_tsa_assign; 6752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6756 u8 queue_id_pri_lvl; 6757 u8 queue_id_bw_weight; 6758 } __packed cfg[7]; 6759 u8 unused_1[5]; 6760 }; 6761 6762 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6763 struct hwrm_queue_cos2bw_cfg_output { 6764 __le16 error_code; 6765 __le16 req_type; 6766 __le16 seq_id; 6767 __le16 resp_len; 6768 u8 unused_0[7]; 6769 u8 valid; 6770 }; 6771 6772 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6773 struct hwrm_queue_dscp_qcaps_input { 6774 __le16 req_type; 6775 __le16 cmpl_ring; 6776 __le16 seq_id; 6777 __le16 target_id; 6778 __le64 resp_addr; 6779 u8 port_id; 6780 u8 unused_0[7]; 6781 }; 6782 6783 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6784 struct hwrm_queue_dscp_qcaps_output { 6785 __le16 error_code; 6786 __le16 req_type; 6787 __le16 seq_id; 6788 __le16 resp_len; 6789 u8 num_dscp_bits; 6790 u8 unused_0; 6791 __le16 max_entries; 6792 u8 unused_1[3]; 6793 u8 valid; 6794 }; 6795 6796 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6797 struct hwrm_queue_dscp2pri_qcfg_input { 6798 __le16 req_type; 6799 __le16 cmpl_ring; 6800 __le16 seq_id; 6801 __le16 target_id; 6802 __le64 resp_addr; 6803 __le64 dest_data_addr; 6804 u8 port_id; 6805 u8 unused_0; 6806 __le16 dest_data_buffer_size; 6807 u8 unused_1[4]; 6808 }; 6809 6810 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6811 struct hwrm_queue_dscp2pri_qcfg_output { 6812 __le16 error_code; 6813 __le16 req_type; 6814 __le16 seq_id; 6815 __le16 resp_len; 6816 __le16 entry_cnt; 6817 u8 default_pri; 6818 u8 unused_0[4]; 6819 u8 valid; 6820 }; 6821 6822 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6823 struct hwrm_queue_dscp2pri_cfg_input { 6824 __le16 req_type; 6825 __le16 cmpl_ring; 6826 __le16 seq_id; 6827 __le16 target_id; 6828 __le64 resp_addr; 6829 __le64 src_data_addr; 6830 __le32 flags; 6831 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6832 __le32 enables; 6833 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6834 u8 port_id; 6835 u8 default_pri; 6836 __le16 entry_cnt; 6837 u8 unused_0[4]; 6838 }; 6839 6840 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6841 struct hwrm_queue_dscp2pri_cfg_output { 6842 __le16 error_code; 6843 __le16 req_type; 6844 __le16 seq_id; 6845 __le16 resp_len; 6846 u8 unused_0[7]; 6847 u8 valid; 6848 }; 6849 6850 /* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ 6851 struct hwrm_queue_pfcwd_timeout_qcaps_input { 6852 __le16 req_type; 6853 __le16 cmpl_ring; 6854 __le16 seq_id; 6855 __le16 target_id; 6856 __le64 resp_addr; 6857 }; 6858 6859 /* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ 6860 struct hwrm_queue_pfcwd_timeout_qcaps_output { 6861 __le16 error_code; 6862 __le16 req_type; 6863 __le16 seq_id; 6864 __le16 resp_len; 6865 __le16 max_pfcwd_timeout; 6866 u8 unused_0[5]; 6867 u8 valid; 6868 }; 6869 6870 /* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ 6871 struct hwrm_queue_pfcwd_timeout_cfg_input { 6872 __le16 req_type; 6873 __le16 cmpl_ring; 6874 __le16 seq_id; 6875 __le16 target_id; 6876 __le64 resp_addr; 6877 __le16 pfcwd_timeout_value; 6878 u8 unused_0[6]; 6879 }; 6880 6881 /* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ 6882 struct hwrm_queue_pfcwd_timeout_cfg_output { 6883 __le16 error_code; 6884 __le16 req_type; 6885 __le16 seq_id; 6886 __le16 resp_len; 6887 u8 unused_0[7]; 6888 u8 valid; 6889 }; 6890 6891 /* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ 6892 struct hwrm_queue_pfcwd_timeout_qcfg_input { 6893 __le16 req_type; 6894 __le16 cmpl_ring; 6895 __le16 seq_id; 6896 __le16 target_id; 6897 __le64 resp_addr; 6898 }; 6899 6900 /* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ 6901 struct hwrm_queue_pfcwd_timeout_qcfg_output { 6902 __le16 error_code; 6903 __le16 req_type; 6904 __le16 seq_id; 6905 __le16 resp_len; 6906 __le16 pfcwd_timeout_value; 6907 u8 unused_0[5]; 6908 u8 valid; 6909 }; 6910 6911 /* hwrm_vnic_alloc_input (size:192b/24B) */ 6912 struct hwrm_vnic_alloc_input { 6913 __le16 req_type; 6914 __le16 cmpl_ring; 6915 __le16 seq_id; 6916 __le16 target_id; 6917 __le64 resp_addr; 6918 __le32 flags; 6919 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6920 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6921 #define VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID 0x4UL 6922 __le16 virtio_net_fid; 6923 __le16 vnic_id; 6924 }; 6925 6926 /* hwrm_vnic_alloc_output (size:128b/16B) */ 6927 struct hwrm_vnic_alloc_output { 6928 __le16 error_code; 6929 __le16 req_type; 6930 __le16 seq_id; 6931 __le16 resp_len; 6932 __le32 vnic_id; 6933 u8 unused_0[3]; 6934 u8 valid; 6935 }; 6936 6937 /* hwrm_vnic_update_input (size:256b/32B) */ 6938 struct hwrm_vnic_update_input { 6939 __le16 req_type; 6940 __le16 cmpl_ring; 6941 __le16 seq_id; 6942 __le16 target_id; 6943 __le64 resp_addr; 6944 __le32 vnic_id; 6945 __le32 enables; 6946 #define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID 0x1UL 6947 #define VNIC_UPDATE_REQ_ENABLES_MRU_VALID 0x2UL 6948 #define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID 0x4UL 6949 u8 vnic_state; 6950 #define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL 6951 #define VNIC_UPDATE_REQ_VNIC_STATE_DROP 0x1UL 6952 #define VNIC_UPDATE_REQ_VNIC_STATE_LAST VNIC_UPDATE_REQ_VNIC_STATE_DROP 6953 u8 metadata_format_type; 6954 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL 6955 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL 6956 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL 6957 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL 6958 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL 6959 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 6960 __le16 mru; 6961 u8 unused_1[4]; 6962 }; 6963 6964 /* hwrm_vnic_update_output (size:128b/16B) */ 6965 struct hwrm_vnic_update_output { 6966 __le16 error_code; 6967 __le16 req_type; 6968 __le16 seq_id; 6969 __le16 resp_len; 6970 u8 unused_0[7]; 6971 u8 valid; 6972 }; 6973 6974 /* hwrm_vnic_free_input (size:192b/24B) */ 6975 struct hwrm_vnic_free_input { 6976 __le16 req_type; 6977 __le16 cmpl_ring; 6978 __le16 seq_id; 6979 __le16 target_id; 6980 __le64 resp_addr; 6981 __le32 vnic_id; 6982 u8 unused_0[4]; 6983 }; 6984 6985 /* hwrm_vnic_free_output (size:128b/16B) */ 6986 struct hwrm_vnic_free_output { 6987 __le16 error_code; 6988 __le16 req_type; 6989 __le16 seq_id; 6990 __le16 resp_len; 6991 u8 unused_0[7]; 6992 u8 valid; 6993 }; 6994 6995 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6996 struct hwrm_vnic_cfg_input { 6997 __le16 req_type; 6998 __le16 cmpl_ring; 6999 __le16 seq_id; 7000 __le16 target_id; 7001 __le64 resp_addr; 7002 __le32 flags; 7003 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 7004 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 7005 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 7006 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 7007 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 7008 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 7009 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 7010 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 7011 #define VNIC_CFG_REQ_FLAGS_DEST_QP 0x100UL 7012 __le32 enables; 7013 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 7014 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 7015 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 7016 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 7017 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 7018 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 7019 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 7020 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 7021 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 7022 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 7023 #define VNIC_CFG_REQ_ENABLES_QP_ID 0x400UL 7024 __le16 vnic_id; 7025 __le16 dflt_ring_grp; 7026 __le16 rss_rule; 7027 __le16 cos_rule; 7028 __le16 lb_rule; 7029 __le16 mru; 7030 __le16 default_rx_ring_id; 7031 __le16 default_cmpl_ring_id; 7032 __le16 queue_id; 7033 u8 rx_csum_v2_mode; 7034 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 7035 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 7036 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 7037 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 7038 u8 l2_cqe_mode; 7039 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 7040 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 7041 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 7042 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 7043 __le32 qp_id; 7044 }; 7045 7046 /* hwrm_vnic_cfg_output (size:128b/16B) */ 7047 struct hwrm_vnic_cfg_output { 7048 __le16 error_code; 7049 __le16 req_type; 7050 __le16 seq_id; 7051 __le16 resp_len; 7052 u8 unused_0[7]; 7053 u8 valid; 7054 }; 7055 7056 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 7057 struct hwrm_vnic_qcaps_input { 7058 __le16 req_type; 7059 __le16 cmpl_ring; 7060 __le16 seq_id; 7061 __le16 target_id; 7062 __le64 resp_addr; 7063 __le32 enables; 7064 u8 unused_0[4]; 7065 }; 7066 7067 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 7068 struct hwrm_vnic_qcaps_output { 7069 __le16 error_code; 7070 __le16 req_type; 7071 __le16 seq_id; 7072 __le16 resp_len; 7073 __le16 mru; 7074 u8 unused_0[2]; 7075 __le32 flags; 7076 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 7077 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 7078 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 7079 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 7080 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 7081 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 7082 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 7083 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 7084 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 7085 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 7086 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 7087 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 7088 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 7089 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 7090 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 7091 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 7092 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 7093 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 7094 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 7095 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 7096 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 7097 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 7098 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 7099 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 7100 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 7101 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 7102 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 7103 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 7104 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 7105 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 7106 #define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP 0x40000000UL 7107 __le16 max_aggs_supported; 7108 u8 unused_1[5]; 7109 u8 valid; 7110 }; 7111 7112 /* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 7113 struct hwrm_vnic_tpa_cfg_input { 7114 __le16 req_type; 7115 __le16 cmpl_ring; 7116 __le16 seq_id; 7117 __le16 target_id; 7118 __le64 resp_addr; 7119 __le32 flags; 7120 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 7121 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 7122 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 7123 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 7124 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 7125 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 7126 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 7127 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 7128 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 7129 __le32 enables; 7130 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 7131 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 7132 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 7133 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 7134 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 7135 __le16 vnic_id; 7136 __le16 max_agg_segs; 7137 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 7138 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 7139 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 7140 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 7141 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 7142 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 7143 __le16 max_aggs; 7144 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 7145 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 7146 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 7147 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 7148 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 7149 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 7150 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 7151 u8 unused_0[2]; 7152 __le32 max_agg_timer; 7153 __le32 min_agg_len; 7154 __le32 tnl_tpa_en_bitmap; 7155 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 7156 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 7157 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 7158 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 7159 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 7160 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 7161 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 7162 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 7163 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 7164 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 7165 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 7166 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 7167 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 7168 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 7169 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 7170 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 7171 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 7172 u8 unused_1[4]; 7173 }; 7174 7175 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 7176 struct hwrm_vnic_tpa_cfg_output { 7177 __le16 error_code; 7178 __le16 req_type; 7179 __le16 seq_id; 7180 __le16 resp_len; 7181 u8 unused_0[7]; 7182 u8 valid; 7183 }; 7184 7185 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 7186 struct hwrm_vnic_tpa_qcfg_input { 7187 __le16 req_type; 7188 __le16 cmpl_ring; 7189 __le16 seq_id; 7190 __le16 target_id; 7191 __le64 resp_addr; 7192 __le16 vnic_id; 7193 u8 unused_0[6]; 7194 }; 7195 7196 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 7197 struct hwrm_vnic_tpa_qcfg_output { 7198 __le16 error_code; 7199 __le16 req_type; 7200 __le16 seq_id; 7201 __le16 resp_len; 7202 __le32 flags; 7203 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 7204 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 7205 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 7206 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 7207 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 7208 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 7209 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 7210 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 7211 __le16 max_agg_segs; 7212 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 7213 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 7214 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 7215 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 7216 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 7217 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 7218 __le16 max_aggs; 7219 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 7220 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 7221 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 7222 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 7223 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 7224 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 7225 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 7226 __le32 max_agg_timer; 7227 __le32 min_agg_len; 7228 __le32 tnl_tpa_en_bitmap; 7229 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 7230 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 7231 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 7232 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 7233 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 7234 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 7235 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 7236 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 7237 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 7238 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 7239 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 7240 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 7241 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 7242 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 7243 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 7244 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 7245 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 7246 u8 unused_0[3]; 7247 u8 valid; 7248 }; 7249 7250 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 7251 struct hwrm_vnic_rss_cfg_input { 7252 __le16 req_type; 7253 __le16 cmpl_ring; 7254 __le16 seq_id; 7255 __le16 target_id; 7256 __le64 resp_addr; 7257 __le32 hash_type; 7258 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 7259 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 7260 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 7261 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 7262 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 7263 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 7264 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 7265 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 7266 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 7267 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 7268 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 7269 __le16 vnic_id; 7270 u8 ring_table_pair_index; 7271 u8 hash_mode_flags; 7272 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 7273 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 7274 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 7275 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 7276 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 7277 __le64 ring_grp_tbl_addr; 7278 __le64 hash_key_tbl_addr; 7279 __le16 rss_ctx_idx; 7280 u8 flags; 7281 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 7282 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 7283 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 7284 u8 ring_select_mode; 7285 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 7286 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 7287 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 7288 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 7289 u8 unused_1[4]; 7290 }; 7291 7292 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 7293 struct hwrm_vnic_rss_cfg_output { 7294 __le16 error_code; 7295 __le16 req_type; 7296 __le16 seq_id; 7297 __le16 resp_len; 7298 u8 unused_0[7]; 7299 u8 valid; 7300 }; 7301 7302 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 7303 struct hwrm_vnic_rss_cfg_cmd_err { 7304 u8 code; 7305 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7306 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 7307 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNABLE_TO_GET_RSS_CFG 0x2UL 7308 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_UNSUPPORTED 0x3UL 7309 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_ERR 0x4UL 7310 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_MODE_FAIL 0x5UL 7311 #define VNIC_RSS_CFG_CMD_ERR_CODE_RING_GRP_TABLE_ALLOC_ERR 0x6UL 7312 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_KEY_ALLOC_ERR 0x7UL 7313 #define VNIC_RSS_CFG_CMD_ERR_CODE_DMA_FAILED 0x8UL 7314 #define VNIC_RSS_CFG_CMD_ERR_CODE_RX_RING_ALLOC_ERR 0x9UL 7315 #define VNIC_RSS_CFG_CMD_ERR_CODE_CMPL_RING_ALLOC_ERR 0xaUL 7316 #define VNIC_RSS_CFG_CMD_ERR_CODE_HW_SET_RSS_FAILED 0xbUL 7317 #define VNIC_RSS_CFG_CMD_ERR_CODE_CTX_INVALID 0xcUL 7318 #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_INVALID 0xdUL 7319 #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 0xeUL 7320 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 7321 u8 unused_0[7]; 7322 }; 7323 7324 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 7325 struct hwrm_vnic_rss_qcfg_input { 7326 __le16 req_type; 7327 __le16 cmpl_ring; 7328 __le16 seq_id; 7329 __le16 target_id; 7330 __le64 resp_addr; 7331 __le16 rss_ctx_idx; 7332 __le16 vnic_id; 7333 u8 unused_0[4]; 7334 }; 7335 7336 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 7337 struct hwrm_vnic_rss_qcfg_output { 7338 __le16 error_code; 7339 __le16 req_type; 7340 __le16 seq_id; 7341 __le16 resp_len; 7342 __le32 hash_type; 7343 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 7344 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 7345 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 7346 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 7347 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 7348 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 7349 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 7350 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 7351 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 7352 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 7353 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 7354 u8 unused_0[4]; 7355 __le32 hash_key[10]; 7356 u8 hash_mode_flags; 7357 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 7358 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 7359 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 7360 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 7361 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 7362 u8 ring_select_mode; 7363 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 7364 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 7365 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 7366 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 7367 u8 unused_1[5]; 7368 u8 valid; 7369 }; 7370 7371 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 7372 struct hwrm_vnic_plcmodes_cfg_input { 7373 __le16 req_type; 7374 __le16 cmpl_ring; 7375 __le16 seq_id; 7376 __le16 target_id; 7377 __le64 resp_addr; 7378 __le32 flags; 7379 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 7380 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 7381 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 7382 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 7383 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 7384 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 7385 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 7386 __le32 enables; 7387 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 7388 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 7389 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 7390 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 7391 __le32 vnic_id; 7392 __le16 jumbo_thresh; 7393 __le16 hds_offset; 7394 __le16 hds_threshold; 7395 __le16 max_bds; 7396 u8 unused_0[4]; 7397 }; 7398 7399 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 7400 struct hwrm_vnic_plcmodes_cfg_output { 7401 __le16 error_code; 7402 __le16 req_type; 7403 __le16 seq_id; 7404 __le16 resp_len; 7405 u8 unused_0[7]; 7406 u8 valid; 7407 }; 7408 7409 /* hwrm_vnic_plcmodes_cfg_cmd_err (size:64b/8B) */ 7410 struct hwrm_vnic_plcmodes_cfg_cmd_err { 7411 u8 code; 7412 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7413 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 0x1UL 7414 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_LAST VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 7415 u8 unused_0[7]; 7416 }; 7417 7418 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 7419 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 7420 __le16 req_type; 7421 __le16 cmpl_ring; 7422 __le16 seq_id; 7423 __le16 target_id; 7424 __le64 resp_addr; 7425 }; 7426 7427 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 7428 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 7429 __le16 error_code; 7430 __le16 req_type; 7431 __le16 seq_id; 7432 __le16 resp_len; 7433 __le16 rss_cos_lb_ctx_id; 7434 u8 unused_0[5]; 7435 u8 valid; 7436 }; 7437 7438 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 7439 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 7440 __le16 req_type; 7441 __le16 cmpl_ring; 7442 __le16 seq_id; 7443 __le16 target_id; 7444 __le64 resp_addr; 7445 __le16 rss_cos_lb_ctx_id; 7446 u8 unused_0[6]; 7447 }; 7448 7449 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 7450 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 7451 __le16 error_code; 7452 __le16 req_type; 7453 __le16 seq_id; 7454 __le16 resp_len; 7455 u8 unused_0[7]; 7456 u8 valid; 7457 }; 7458 7459 /* hwrm_ring_alloc_input (size:768b/96B) */ 7460 struct hwrm_ring_alloc_input { 7461 __le16 req_type; 7462 __le16 cmpl_ring; 7463 __le16 seq_id; 7464 __le16 target_id; 7465 __le64 resp_addr; 7466 __le32 enables; 7467 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 7468 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 7469 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 7470 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 7471 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 7472 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 7473 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 7474 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 7475 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 7476 #define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL 7477 #define RING_ALLOC_REQ_ENABLES_DPI_VALID 0x2000UL 7478 u8 ring_type; 7479 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 7480 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 7481 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 7482 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7483 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 7484 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 7485 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 7486 u8 cmpl_coal_cnt; 7487 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 7488 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 7489 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 7490 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 7491 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 7492 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 7493 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 7494 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 7495 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 7496 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 7497 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 7498 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 7499 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 7500 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 7501 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 7502 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 7503 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 7504 __le16 flags; 7505 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 7506 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7507 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7508 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7509 #define RING_ALLOC_REQ_FLAGS_DPI_ROCE_MANAGED 0x10UL 7510 #define RING_ALLOC_REQ_FLAGS_TIMER_RESET 0x20UL 7511 __le64 page_tbl_addr; 7512 __le32 fbo; 7513 u8 page_size; 7514 u8 page_tbl_depth; 7515 __le16 schq_id; 7516 __le32 length; 7517 __le16 logical_id; 7518 __le16 cmpl_ring_id; 7519 __le16 queue_id; 7520 __le16 rx_buf_size; 7521 __le16 rx_ring_id; 7522 __le16 nq_ring_id; 7523 __le16 ring_arb_cfg; 7524 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 7525 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 7526 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 7527 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 7528 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 7529 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 7530 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 7531 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 7532 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 7533 __le16 steering_tag; 7534 __le32 reserved3; 7535 __le32 stat_ctx_id; 7536 __le32 reserved4; 7537 __le32 max_bw; 7538 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 7539 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 7540 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 7541 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 7542 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 7543 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 7544 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 7545 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 7546 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 7547 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 7548 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 7549 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 7550 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 7551 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 7552 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 7553 u8 int_mode; 7554 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 7555 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 7556 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 7557 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 7558 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 7559 u8 mpc_chnls_type; 7560 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 7561 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 7562 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 7563 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 7564 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 7565 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 7566 u8 rx_rate_profile_sel; 7567 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_DEFAULT 0x0UL 7568 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 0x1UL 7569 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 7570 u8 unused_4; 7571 __le64 cq_handle; 7572 __le16 dpi; 7573 __le16 unused_5[3]; 7574 }; 7575 7576 /* hwrm_ring_alloc_output (size:128b/16B) */ 7577 struct hwrm_ring_alloc_output { 7578 __le16 error_code; 7579 __le16 req_type; 7580 __le16 seq_id; 7581 __le16 resp_len; 7582 __le16 ring_id; 7583 __le16 logical_ring_id; 7584 u8 push_buffer_index; 7585 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7586 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7587 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7588 u8 unused_0[2]; 7589 u8 valid; 7590 }; 7591 7592 /* hwrm_ring_free_input (size:256b/32B) */ 7593 struct hwrm_ring_free_input { 7594 __le16 req_type; 7595 __le16 cmpl_ring; 7596 __le16 seq_id; 7597 __le16 target_id; 7598 __le64 resp_addr; 7599 u8 ring_type; 7600 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7601 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7602 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7603 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7604 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7605 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7606 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7607 u8 flags; 7608 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7609 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7610 __le16 ring_id; 7611 __le32 prod_idx; 7612 __le32 opaque; 7613 __le32 unused_1; 7614 }; 7615 7616 /* hwrm_ring_free_output (size:128b/16B) */ 7617 struct hwrm_ring_free_output { 7618 __le16 error_code; 7619 __le16 req_type; 7620 __le16 seq_id; 7621 __le16 resp_len; 7622 u8 unused_0[7]; 7623 u8 valid; 7624 }; 7625 7626 /* hwrm_ring_reset_input (size:192b/24B) */ 7627 struct hwrm_ring_reset_input { 7628 __le16 req_type; 7629 __le16 cmpl_ring; 7630 __le16 seq_id; 7631 __le16 target_id; 7632 __le64 resp_addr; 7633 u8 ring_type; 7634 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7635 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7636 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7637 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7638 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7639 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7640 u8 unused_0; 7641 __le16 ring_id; 7642 u8 unused_1[4]; 7643 }; 7644 7645 /* hwrm_ring_reset_output (size:128b/16B) */ 7646 struct hwrm_ring_reset_output { 7647 __le16 error_code; 7648 __le16 req_type; 7649 __le16 seq_id; 7650 __le16 resp_len; 7651 u8 push_buffer_index; 7652 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7653 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7654 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7655 u8 unused_0[3]; 7656 u8 consumer_idx[3]; 7657 u8 valid; 7658 }; 7659 7660 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7661 struct hwrm_ring_aggint_qcaps_input { 7662 __le16 req_type; 7663 __le16 cmpl_ring; 7664 __le16 seq_id; 7665 __le16 target_id; 7666 __le64 resp_addr; 7667 }; 7668 7669 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7670 struct hwrm_ring_aggint_qcaps_output { 7671 __le16 error_code; 7672 __le16 req_type; 7673 __le16 seq_id; 7674 __le16 resp_len; 7675 __le32 cmpl_params; 7676 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7677 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7678 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7679 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7680 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7681 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7682 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7683 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7684 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7685 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TMR_RESET_ON_ALLOC 0x200UL 7686 __le32 nq_params; 7687 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7688 __le16 num_cmpl_dma_aggr_min; 7689 __le16 num_cmpl_dma_aggr_max; 7690 __le16 num_cmpl_dma_aggr_during_int_min; 7691 __le16 num_cmpl_dma_aggr_during_int_max; 7692 __le16 cmpl_aggr_dma_tmr_min; 7693 __le16 cmpl_aggr_dma_tmr_max; 7694 __le16 cmpl_aggr_dma_tmr_during_int_min; 7695 __le16 cmpl_aggr_dma_tmr_during_int_max; 7696 __le16 int_lat_tmr_min_min; 7697 __le16 int_lat_tmr_min_max; 7698 __le16 int_lat_tmr_max_min; 7699 __le16 int_lat_tmr_max_max; 7700 __le16 num_cmpl_aggr_int_min; 7701 __le16 num_cmpl_aggr_int_max; 7702 __le16 timer_units; 7703 u8 unused_0[1]; 7704 u8 valid; 7705 }; 7706 7707 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7708 struct hwrm_ring_cmpl_ring_qaggint_params_input { 7709 __le16 req_type; 7710 __le16 cmpl_ring; 7711 __le16 seq_id; 7712 __le16 target_id; 7713 __le64 resp_addr; 7714 __le16 ring_id; 7715 __le16 flags; 7716 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7717 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7718 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7719 u8 unused_0[4]; 7720 }; 7721 7722 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7723 struct hwrm_ring_cmpl_ring_qaggint_params_output { 7724 __le16 error_code; 7725 __le16 req_type; 7726 __le16 seq_id; 7727 __le16 resp_len; 7728 __le16 flags; 7729 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7730 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7731 __le16 num_cmpl_dma_aggr; 7732 __le16 num_cmpl_dma_aggr_during_int; 7733 __le16 cmpl_aggr_dma_tmr; 7734 __le16 cmpl_aggr_dma_tmr_during_int; 7735 __le16 int_lat_tmr_min; 7736 __le16 int_lat_tmr_max; 7737 __le16 num_cmpl_aggr_int; 7738 u8 unused_0[7]; 7739 u8 valid; 7740 }; 7741 7742 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7743 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7744 __le16 req_type; 7745 __le16 cmpl_ring; 7746 __le16 seq_id; 7747 __le16 target_id; 7748 __le64 resp_addr; 7749 __le16 ring_id; 7750 __le16 flags; 7751 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7752 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7753 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7754 __le16 num_cmpl_dma_aggr; 7755 __le16 num_cmpl_dma_aggr_during_int; 7756 __le16 cmpl_aggr_dma_tmr; 7757 __le16 cmpl_aggr_dma_tmr_during_int; 7758 __le16 int_lat_tmr_min; 7759 __le16 int_lat_tmr_max; 7760 __le16 num_cmpl_aggr_int; 7761 __le16 enables; 7762 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7763 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7764 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7765 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7766 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7767 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7768 u8 unused_0[4]; 7769 }; 7770 7771 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7772 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7773 __le16 error_code; 7774 __le16 req_type; 7775 __le16 seq_id; 7776 __le16 resp_len; 7777 u8 unused_0[7]; 7778 u8 valid; 7779 }; 7780 7781 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7782 struct hwrm_ring_grp_alloc_input { 7783 __le16 req_type; 7784 __le16 cmpl_ring; 7785 __le16 seq_id; 7786 __le16 target_id; 7787 __le64 resp_addr; 7788 __le16 cr; 7789 __le16 rr; 7790 __le16 ar; 7791 __le16 sc; 7792 }; 7793 7794 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7795 struct hwrm_ring_grp_alloc_output { 7796 __le16 error_code; 7797 __le16 req_type; 7798 __le16 seq_id; 7799 __le16 resp_len; 7800 __le32 ring_group_id; 7801 u8 unused_0[3]; 7802 u8 valid; 7803 }; 7804 7805 /* hwrm_ring_grp_free_input (size:192b/24B) */ 7806 struct hwrm_ring_grp_free_input { 7807 __le16 req_type; 7808 __le16 cmpl_ring; 7809 __le16 seq_id; 7810 __le16 target_id; 7811 __le64 resp_addr; 7812 __le32 ring_group_id; 7813 u8 unused_0[4]; 7814 }; 7815 7816 /* hwrm_ring_grp_free_output (size:128b/16B) */ 7817 struct hwrm_ring_grp_free_output { 7818 __le16 error_code; 7819 __le16 req_type; 7820 __le16 seq_id; 7821 __le16 resp_len; 7822 u8 unused_0[7]; 7823 u8 valid; 7824 }; 7825 7826 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7827 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7828 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7829 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7830 7831 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7832 struct hwrm_cfa_l2_filter_alloc_input { 7833 __le16 req_type; 7834 __le16 cmpl_ring; 7835 __le16 seq_id; 7836 __le16 target_id; 7837 __le64 resp_addr; 7838 __le32 flags; 7839 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7840 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7841 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7842 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7843 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7844 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7845 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7846 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7847 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7848 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7849 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7850 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7851 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7852 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7853 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7854 __le32 enables; 7855 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7856 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7857 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7858 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7859 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7860 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7861 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7862 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7863 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7864 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7865 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7866 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7867 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7868 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7869 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7870 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7871 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7872 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7873 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7874 u8 l2_addr[6]; 7875 u8 num_vlans; 7876 u8 t_num_vlans; 7877 u8 l2_addr_mask[6]; 7878 __le16 l2_ovlan; 7879 __le16 l2_ovlan_mask; 7880 __le16 l2_ivlan; 7881 __le16 l2_ivlan_mask; 7882 u8 unused_1[2]; 7883 u8 t_l2_addr[6]; 7884 u8 unused_2[2]; 7885 u8 t_l2_addr_mask[6]; 7886 __le16 t_l2_ovlan; 7887 __le16 t_l2_ovlan_mask; 7888 __le16 t_l2_ivlan; 7889 __le16 t_l2_ivlan_mask; 7890 u8 src_type; 7891 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7892 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7893 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7894 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7895 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7896 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7897 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7898 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7899 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7900 u8 unused_3; 7901 __le32 src_id; 7902 u8 tunnel_type; 7903 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7904 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7905 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7906 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7907 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7908 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7909 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7910 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7911 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7912 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7913 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7914 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7915 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7916 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7917 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7918 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7919 u8 unused_4; 7920 __le16 dst_id; 7921 __le16 mirror_vnic_id; 7922 u8 pri_hint; 7923 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7924 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7925 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7926 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7927 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7928 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7929 u8 unused_5; 7930 __le32 unused_6; 7931 __le64 l2_filter_id_hint; 7932 }; 7933 7934 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7935 struct hwrm_cfa_l2_filter_alloc_output { 7936 __le16 error_code; 7937 __le16 req_type; 7938 __le16 seq_id; 7939 __le16 resp_len; 7940 __le64 l2_filter_id; 7941 __le32 flow_id; 7942 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7943 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7944 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7945 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7946 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7947 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7948 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7949 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7950 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7951 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7952 u8 unused_0[3]; 7953 u8 valid; 7954 }; 7955 7956 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7957 struct hwrm_cfa_l2_filter_free_input { 7958 __le16 req_type; 7959 __le16 cmpl_ring; 7960 __le16 seq_id; 7961 __le16 target_id; 7962 __le64 resp_addr; 7963 __le64 l2_filter_id; 7964 }; 7965 7966 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7967 struct hwrm_cfa_l2_filter_free_output { 7968 __le16 error_code; 7969 __le16 req_type; 7970 __le16 seq_id; 7971 __le16 resp_len; 7972 u8 unused_0[7]; 7973 u8 valid; 7974 }; 7975 7976 /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7977 struct hwrm_cfa_l2_filter_cfg_input { 7978 __le16 req_type; 7979 __le16 cmpl_ring; 7980 __le16 seq_id; 7981 __le16 target_id; 7982 __le64 resp_addr; 7983 __le32 flags; 7984 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7985 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7986 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7987 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7988 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7989 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7990 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7991 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7992 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7993 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7994 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7995 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7996 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7997 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7998 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7999 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 8000 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP (0x3UL << 4) 8001 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP 8002 __le32 enables; 8003 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 8004 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 8005 #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 8006 #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 8007 __le64 l2_filter_id; 8008 __le32 dst_id; 8009 __le32 new_mirror_vnic_id; 8010 __le32 prof_func; 8011 __le32 l2_context_id; 8012 }; 8013 8014 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 8015 struct hwrm_cfa_l2_filter_cfg_output { 8016 __le16 error_code; 8017 __le16 req_type; 8018 __le16 seq_id; 8019 __le16 resp_len; 8020 u8 unused_0[7]; 8021 u8 valid; 8022 }; 8023 8024 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 8025 struct hwrm_cfa_l2_set_rx_mask_input { 8026 __le16 req_type; 8027 __le16 cmpl_ring; 8028 __le16 seq_id; 8029 __le16 target_id; 8030 __le64 resp_addr; 8031 __le32 vnic_id; 8032 __le32 mask; 8033 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 8034 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 8035 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 8036 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 8037 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 8038 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 8039 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 8040 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 8041 __le64 mc_tbl_addr; 8042 __le32 num_mc_entries; 8043 u8 unused_0[4]; 8044 __le64 vlan_tag_tbl_addr; 8045 __le32 num_vlan_tags; 8046 u8 unused_1[4]; 8047 }; 8048 8049 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 8050 struct hwrm_cfa_l2_set_rx_mask_output { 8051 __le16 error_code; 8052 __le16 req_type; 8053 __le16 seq_id; 8054 __le16 resp_len; 8055 u8 unused_0[7]; 8056 u8 valid; 8057 }; 8058 8059 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 8060 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 8061 u8 code; 8062 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 8063 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 8064 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_MAX_VLAN_TAGS 0x2UL 8065 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_VNIC_ID 0x3UL 8066 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 0x4UL 8067 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 8068 u8 unused_0[7]; 8069 }; 8070 8071 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 8072 struct hwrm_cfa_tunnel_filter_alloc_input { 8073 __le16 req_type; 8074 __le16 cmpl_ring; 8075 __le16 seq_id; 8076 __le16 target_id; 8077 __le64 resp_addr; 8078 __le32 flags; 8079 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 8080 __le32 enables; 8081 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 8082 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 8083 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 8084 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 8085 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 8086 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 8087 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 8088 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 8089 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 8090 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 8091 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 8092 __le64 l2_filter_id; 8093 u8 l2_addr[6]; 8094 __le16 l2_ivlan; 8095 __le32 l3_addr[4]; 8096 __le32 t_l3_addr[4]; 8097 u8 l3_addr_type; 8098 u8 t_l3_addr_type; 8099 u8 tunnel_type; 8100 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8101 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8102 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8103 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8104 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8105 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8106 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8107 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8108 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8109 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8110 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8111 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8112 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8113 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8114 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8115 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8116 u8 tunnel_flags; 8117 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 8118 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 8119 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 8120 __le32 vni; 8121 __le32 dst_vnic_id; 8122 __le32 mirror_vnic_id; 8123 }; 8124 8125 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 8126 struct hwrm_cfa_tunnel_filter_alloc_output { 8127 __le16 error_code; 8128 __le16 req_type; 8129 __le16 seq_id; 8130 __le16 resp_len; 8131 __le64 tunnel_filter_id; 8132 __le32 flow_id; 8133 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8134 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8135 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8136 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8137 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8138 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 8139 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8140 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8141 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8142 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 8143 u8 unused_0[3]; 8144 u8 valid; 8145 }; 8146 8147 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 8148 struct hwrm_cfa_tunnel_filter_free_input { 8149 __le16 req_type; 8150 __le16 cmpl_ring; 8151 __le16 seq_id; 8152 __le16 target_id; 8153 __le64 resp_addr; 8154 __le64 tunnel_filter_id; 8155 }; 8156 8157 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 8158 struct hwrm_cfa_tunnel_filter_free_output { 8159 __le16 error_code; 8160 __le16 req_type; 8161 __le16 seq_id; 8162 __le16 resp_len; 8163 u8 unused_0[7]; 8164 u8 valid; 8165 }; 8166 8167 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 8168 struct hwrm_vxlan_ipv4_hdr { 8169 u8 ver_hlen; 8170 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 8171 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 8172 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 8173 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 8174 u8 tos; 8175 __be16 ip_id; 8176 __be16 flags_frag_offset; 8177 u8 ttl; 8178 u8 protocol; 8179 __be32 src_ip_addr; 8180 __be32 dest_ip_addr; 8181 }; 8182 8183 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 8184 struct hwrm_vxlan_ipv6_hdr { 8185 __be32 ver_tc_flow_label; 8186 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 8187 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 8188 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 8189 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 8190 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 8191 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 8192 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 8193 __be16 payload_len; 8194 u8 next_hdr; 8195 u8 ttl; 8196 __be32 src_ip_addr[4]; 8197 __be32 dest_ip_addr[4]; 8198 }; 8199 8200 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 8201 struct hwrm_cfa_encap_data_vxlan { 8202 u8 src_mac_addr[6]; 8203 __le16 unused_0; 8204 u8 dst_mac_addr[6]; 8205 u8 num_vlan_tags; 8206 u8 unused_1; 8207 __be16 ovlan_tpid; 8208 __be16 ovlan_tci; 8209 __be16 ivlan_tpid; 8210 __be16 ivlan_tci; 8211 __le32 l3[10]; 8212 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 8213 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 8214 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 8215 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 8216 __be16 src_port; 8217 __be16 dst_port; 8218 __be32 vni; 8219 u8 hdr_rsvd0[3]; 8220 u8 hdr_rsvd1; 8221 u8 hdr_flags; 8222 u8 unused[3]; 8223 }; 8224 8225 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 8226 struct hwrm_cfa_encap_record_alloc_input { 8227 __le16 req_type; 8228 __le16 cmpl_ring; 8229 __le16 seq_id; 8230 __le16 target_id; 8231 __le64 resp_addr; 8232 __le32 flags; 8233 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 8234 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 8235 u8 encap_type; 8236 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 8237 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 8238 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 8239 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 8240 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 8241 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 8242 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 8243 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 8244 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 8245 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 8246 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 8247 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 8248 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 8249 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 8250 u8 unused_0[3]; 8251 __le32 encap_data[20]; 8252 }; 8253 8254 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 8255 struct hwrm_cfa_encap_record_alloc_output { 8256 __le16 error_code; 8257 __le16 req_type; 8258 __le16 seq_id; 8259 __le16 resp_len; 8260 __le32 encap_record_id; 8261 u8 unused_0[3]; 8262 u8 valid; 8263 }; 8264 8265 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 8266 struct hwrm_cfa_encap_record_free_input { 8267 __le16 req_type; 8268 __le16 cmpl_ring; 8269 __le16 seq_id; 8270 __le16 target_id; 8271 __le64 resp_addr; 8272 __le32 encap_record_id; 8273 u8 unused_0[4]; 8274 }; 8275 8276 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 8277 struct hwrm_cfa_encap_record_free_output { 8278 __le16 error_code; 8279 __le16 req_type; 8280 __le16 seq_id; 8281 __le16 resp_len; 8282 u8 unused_0[7]; 8283 u8 valid; 8284 }; 8285 8286 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 8287 struct hwrm_cfa_ntuple_filter_alloc_input { 8288 __le16 req_type; 8289 __le16 cmpl_ring; 8290 __le16 seq_id; 8291 __le16 target_id; 8292 __le64 resp_addr; 8293 __le32 flags; 8294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 8295 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 8296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 8297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 8298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 8299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 8300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 8301 __le32 enables; 8302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 8303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 8304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 8305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 8306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 8307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 8308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 8309 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 8310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 8311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 8312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 8313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 8314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 8315 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 8316 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 8317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 8318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 8319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 8320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 8321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 8322 __le64 l2_filter_id; 8323 u8 src_macaddr[6]; 8324 __be16 ethertype; 8325 u8 ip_addr_type; 8326 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8327 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8330 u8 ip_protocol; 8331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 8335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 8336 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 8337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 8338 __le16 dst_id; 8339 __le16 rfs_ring_tbl_idx; 8340 u8 tunnel_type; 8341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8343 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8346 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8347 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8348 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8349 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8350 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8351 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8352 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8353 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8354 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8355 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8356 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8357 u8 pri_hint; 8358 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 8359 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 8360 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 8361 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 8362 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 8363 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 8364 __be32 src_ipaddr[4]; 8365 __be32 src_ipaddr_mask[4]; 8366 __be32 dst_ipaddr[4]; 8367 __be32 dst_ipaddr_mask[4]; 8368 __be16 src_port; 8369 __be16 src_port_mask; 8370 __be16 dst_port; 8371 __be16 dst_port_mask; 8372 __le64 ntuple_filter_id_hint; 8373 }; 8374 8375 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 8376 struct hwrm_cfa_ntuple_filter_alloc_output { 8377 __le16 error_code; 8378 __le16 req_type; 8379 __le16 seq_id; 8380 __le16 resp_len; 8381 __le64 ntuple_filter_id; 8382 __le32 flow_id; 8383 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8384 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8385 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8386 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8387 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8388 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 8389 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8390 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8391 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8392 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 8393 u8 unused_0[3]; 8394 u8 valid; 8395 }; 8396 8397 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 8398 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 8399 u8 code; 8400 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8401 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_MAC 0x65UL 8402 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_BC_MC_MAC 0x66UL 8403 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_VNIC 0x67UL 8404 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_PF_FID 0x68UL 8405 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L2_CTXT_ID 0x69UL 8406 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_CTXT_CFG 0x6aUL 8407 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_DATA_FLD 0x6bUL 8408 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_CFA_LAYOUT 0x6cUL 8409 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_CTXT_ALLOC_FAIL 0x6dUL 8410 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ROCE_FLOW_ERR 0x6eUL 8411 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_OWNER_FID 0x6fUL 8412 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_REF_CNT 0x70UL 8413 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_FLOW_TYPE 0x71UL 8414 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_IVLAN 0x72UL 8415 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_MAX_VLAN_ID 0x73UL 8416 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_TNL_REQ 0x74UL 8417 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_ADDR 0x75UL 8418 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_IVLAN 0x76UL 8419 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR 0x77UL 8420 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR_TYPE 0x78UL 8421 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_T_L3_ADDR_TYPE 0x79UL 8422 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DST_VNIC_ID 0x7aUL 8423 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VNI 0x7bUL 8424 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_DST_ID 0x7cUL 8425 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_FAIL_ROCE_L2_FLOW 0x7dUL 8426 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_NPAR_VLAN 0x7eUL 8427 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ATSP_ADD 0x7fUL 8428 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DFLT_VLAN_FAIL 0x80UL 8429 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L3_TYPE 0x81UL 8430 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 0x82UL 8431 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 8432 u8 unused_0[7]; 8433 }; 8434 8435 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 8436 struct hwrm_cfa_ntuple_filter_free_input { 8437 __le16 req_type; 8438 __le16 cmpl_ring; 8439 __le16 seq_id; 8440 __le16 target_id; 8441 __le64 resp_addr; 8442 __le64 ntuple_filter_id; 8443 }; 8444 8445 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 8446 struct hwrm_cfa_ntuple_filter_free_output { 8447 __le16 error_code; 8448 __le16 req_type; 8449 __le16 seq_id; 8450 __le16 resp_len; 8451 u8 unused_0[7]; 8452 u8 valid; 8453 }; 8454 8455 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 8456 struct hwrm_cfa_ntuple_filter_cfg_input { 8457 __le16 req_type; 8458 __le16 cmpl_ring; 8459 __le16 seq_id; 8460 __le16 target_id; 8461 __le64 resp_addr; 8462 __le32 enables; 8463 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 8464 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 8465 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 8466 __le32 flags; 8467 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 8468 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 8469 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 8470 __le64 ntuple_filter_id; 8471 __le32 new_dst_id; 8472 __le32 new_mirror_vnic_id; 8473 __le16 new_meter_instance_id; 8474 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 8475 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 8476 u8 unused_1[6]; 8477 }; 8478 8479 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 8480 struct hwrm_cfa_ntuple_filter_cfg_output { 8481 __le16 error_code; 8482 __le16 req_type; 8483 __le16 seq_id; 8484 __le16 resp_len; 8485 u8 unused_0[7]; 8486 u8 valid; 8487 }; 8488 8489 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 8490 struct hwrm_cfa_decap_filter_alloc_input { 8491 __le16 req_type; 8492 __le16 cmpl_ring; 8493 __le16 seq_id; 8494 __le16 target_id; 8495 __le64 resp_addr; 8496 __le32 flags; 8497 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 8498 __le32 enables; 8499 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 8500 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 8501 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 8502 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 8503 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 8504 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 8505 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 8506 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 8507 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 8508 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 8509 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 8510 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 8511 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 8512 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 8513 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 8514 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 8515 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 8516 __be32 tunnel_id; 8517 u8 tunnel_type; 8518 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8519 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8520 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8521 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8522 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8523 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8524 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8525 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8526 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8527 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8528 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8529 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8530 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8531 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8532 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8533 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8534 u8 unused_0; 8535 __le16 unused_1; 8536 u8 src_macaddr[6]; 8537 u8 unused_2[2]; 8538 u8 dst_macaddr[6]; 8539 __be16 ovlan_vid; 8540 __be16 ivlan_vid; 8541 __be16 t_ovlan_vid; 8542 __be16 t_ivlan_vid; 8543 __be16 ethertype; 8544 u8 ip_addr_type; 8545 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8546 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8547 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8548 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8549 u8 ip_protocol; 8550 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8551 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8552 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8553 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 8554 __le16 unused_3; 8555 __le32 unused_4; 8556 __be32 src_ipaddr[4]; 8557 __be32 dst_ipaddr[4]; 8558 __be16 src_port; 8559 __be16 dst_port; 8560 __le16 dst_id; 8561 __le16 l2_ctxt_ref_id; 8562 }; 8563 8564 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 8565 struct hwrm_cfa_decap_filter_alloc_output { 8566 __le16 error_code; 8567 __le16 req_type; 8568 __le16 seq_id; 8569 __le16 resp_len; 8570 __le32 decap_filter_id; 8571 u8 unused_0[3]; 8572 u8 valid; 8573 }; 8574 8575 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 8576 struct hwrm_cfa_decap_filter_free_input { 8577 __le16 req_type; 8578 __le16 cmpl_ring; 8579 __le16 seq_id; 8580 __le16 target_id; 8581 __le64 resp_addr; 8582 __le32 decap_filter_id; 8583 u8 unused_0[4]; 8584 }; 8585 8586 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 8587 struct hwrm_cfa_decap_filter_free_output { 8588 __le16 error_code; 8589 __le16 req_type; 8590 __le16 seq_id; 8591 __le16 resp_len; 8592 u8 unused_0[7]; 8593 u8 valid; 8594 }; 8595 8596 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 8597 struct hwrm_cfa_flow_alloc_input { 8598 __le16 req_type; 8599 __le16 cmpl_ring; 8600 __le16 seq_id; 8601 __le16 target_id; 8602 __le64 resp_addr; 8603 __le16 flags; 8604 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 8605 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 8606 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 8607 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 8608 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 8609 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 8610 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 8611 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 8612 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 8613 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 8614 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 8615 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 8616 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 8617 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 8618 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 8619 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 8620 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 8621 __le16 src_fid; 8622 __le32 tunnel_handle; 8623 __le16 action_flags; 8624 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 8625 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 8626 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 8627 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 8628 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 8629 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 8630 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 8631 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 8632 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 8633 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 8634 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 8635 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8636 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8637 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8638 __le16 dst_fid; 8639 __be16 l2_rewrite_vlan_tpid; 8640 __be16 l2_rewrite_vlan_tci; 8641 __le16 act_meter_id; 8642 __le16 ref_flow_handle; 8643 __be16 ethertype; 8644 __be16 outer_vlan_tci; 8645 __be16 dmac[3]; 8646 __be16 inner_vlan_tci; 8647 __be16 smac[3]; 8648 u8 ip_dst_mask_len; 8649 u8 ip_src_mask_len; 8650 __be32 ip_dst[4]; 8651 __be32 ip_src[4]; 8652 __be16 l4_src_port; 8653 __be16 l4_src_port_mask; 8654 __be16 l4_dst_port; 8655 __be16 l4_dst_port_mask; 8656 __be32 nat_ip_address[4]; 8657 __be16 l2_rewrite_dmac[3]; 8658 __be16 nat_port; 8659 __be16 l2_rewrite_smac[3]; 8660 u8 ip_proto; 8661 u8 tunnel_type; 8662 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8663 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8664 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8665 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8666 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8667 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8668 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8669 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8670 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8671 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8672 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8673 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8674 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8675 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8676 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8677 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8678 }; 8679 8680 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8681 struct hwrm_cfa_flow_alloc_output { 8682 __le16 error_code; 8683 __le16 req_type; 8684 __le16 seq_id; 8685 __le16 resp_len; 8686 __le16 flow_handle; 8687 u8 unused_0[2]; 8688 __le32 flow_id; 8689 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8690 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8691 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8692 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8693 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8694 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8695 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8696 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8697 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8698 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8699 __le64 ext_flow_handle; 8700 __le32 flow_counter_id; 8701 u8 unused_1[3]; 8702 u8 valid; 8703 }; 8704 8705 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8706 struct hwrm_cfa_flow_alloc_cmd_err { 8707 u8 code; 8708 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8709 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8710 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8711 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8712 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8713 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8714 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8715 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8716 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8717 u8 unused_0[7]; 8718 }; 8719 8720 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 8721 struct hwrm_cfa_flow_free_input { 8722 __le16 req_type; 8723 __le16 cmpl_ring; 8724 __le16 seq_id; 8725 __le16 target_id; 8726 __le64 resp_addr; 8727 __le16 flow_handle; 8728 __le16 unused_0; 8729 __le32 flow_counter_id; 8730 __le64 ext_flow_handle; 8731 }; 8732 8733 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 8734 struct hwrm_cfa_flow_free_output { 8735 __le16 error_code; 8736 __le16 req_type; 8737 __le16 seq_id; 8738 __le16 resp_len; 8739 __le64 packet; 8740 __le64 byte; 8741 u8 unused_0[7]; 8742 u8 valid; 8743 }; 8744 8745 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 8746 struct hwrm_cfa_flow_info_input { 8747 __le16 req_type; 8748 __le16 cmpl_ring; 8749 __le16 seq_id; 8750 __le16 target_id; 8751 __le64 resp_addr; 8752 __le16 flow_handle; 8753 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8754 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8755 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8756 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8757 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8758 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8759 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8760 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8761 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8762 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8763 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8764 u8 unused_0[6]; 8765 __le64 ext_flow_handle; 8766 }; 8767 8768 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8769 struct hwrm_cfa_flow_info_output { 8770 __le16 error_code; 8771 __le16 req_type; 8772 __le16 seq_id; 8773 __le16 resp_len; 8774 u8 flags; 8775 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8776 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8777 u8 profile; 8778 __le16 src_fid; 8779 __le16 dst_fid; 8780 __le16 l2_ctxt_id; 8781 __le64 em_info; 8782 __le64 tcam_info; 8783 __le64 vfp_tcam_info; 8784 __le16 ar_id; 8785 __le16 flow_handle; 8786 __le32 tunnel_handle; 8787 __le16 flow_timer; 8788 u8 unused_0[6]; 8789 __le32 flow_key_data[130]; 8790 __le32 flow_action_info[30]; 8791 u8 unused_1[7]; 8792 u8 valid; 8793 }; 8794 8795 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8796 struct hwrm_cfa_flow_stats_input { 8797 __le16 req_type; 8798 __le16 cmpl_ring; 8799 __le16 seq_id; 8800 __le16 target_id; 8801 __le64 resp_addr; 8802 __le16 num_flows; 8803 __le16 flow_handle_0; 8804 __le16 flow_handle_1; 8805 __le16 flow_handle_2; 8806 __le16 flow_handle_3; 8807 __le16 flow_handle_4; 8808 __le16 flow_handle_5; 8809 __le16 flow_handle_6; 8810 __le16 flow_handle_7; 8811 __le16 flow_handle_8; 8812 __le16 flow_handle_9; 8813 u8 unused_0[2]; 8814 __le32 flow_id_0; 8815 __le32 flow_id_1; 8816 __le32 flow_id_2; 8817 __le32 flow_id_3; 8818 __le32 flow_id_4; 8819 __le32 flow_id_5; 8820 __le32 flow_id_6; 8821 __le32 flow_id_7; 8822 __le32 flow_id_8; 8823 __le32 flow_id_9; 8824 }; 8825 8826 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8827 struct hwrm_cfa_flow_stats_output { 8828 __le16 error_code; 8829 __le16 req_type; 8830 __le16 seq_id; 8831 __le16 resp_len; 8832 __le64 packet_0; 8833 __le64 packet_1; 8834 __le64 packet_2; 8835 __le64 packet_3; 8836 __le64 packet_4; 8837 __le64 packet_5; 8838 __le64 packet_6; 8839 __le64 packet_7; 8840 __le64 packet_8; 8841 __le64 packet_9; 8842 __le64 byte_0; 8843 __le64 byte_1; 8844 __le64 byte_2; 8845 __le64 byte_3; 8846 __le64 byte_4; 8847 __le64 byte_5; 8848 __le64 byte_6; 8849 __le64 byte_7; 8850 __le64 byte_8; 8851 __le64 byte_9; 8852 __le16 flow_hits; 8853 u8 unused_0[5]; 8854 u8 valid; 8855 }; 8856 8857 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8858 struct hwrm_cfa_vfr_alloc_input { 8859 __le16 req_type; 8860 __le16 cmpl_ring; 8861 __le16 seq_id; 8862 __le16 target_id; 8863 __le64 resp_addr; 8864 __le16 vf_id; 8865 __le16 reserved; 8866 u8 unused_0[4]; 8867 char vfr_name[32]; 8868 }; 8869 8870 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8871 struct hwrm_cfa_vfr_alloc_output { 8872 __le16 error_code; 8873 __le16 req_type; 8874 __le16 seq_id; 8875 __le16 resp_len; 8876 __le16 rx_cfa_code; 8877 __le16 tx_cfa_action; 8878 u8 unused_0[3]; 8879 u8 valid; 8880 }; 8881 8882 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8883 struct hwrm_cfa_vfr_free_input { 8884 __le16 req_type; 8885 __le16 cmpl_ring; 8886 __le16 seq_id; 8887 __le16 target_id; 8888 __le64 resp_addr; 8889 char vfr_name[32]; 8890 __le16 vf_id; 8891 __le16 reserved; 8892 u8 unused_0[4]; 8893 }; 8894 8895 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8896 struct hwrm_cfa_vfr_free_output { 8897 __le16 error_code; 8898 __le16 req_type; 8899 __le16 seq_id; 8900 __le16 resp_len; 8901 u8 unused_0[7]; 8902 u8 valid; 8903 }; 8904 8905 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8906 struct hwrm_cfa_eem_qcaps_input { 8907 __le16 req_type; 8908 __le16 cmpl_ring; 8909 __le16 seq_id; 8910 __le16 target_id; 8911 __le64 resp_addr; 8912 __le32 flags; 8913 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8914 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8915 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8916 __le32 unused_0; 8917 }; 8918 8919 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8920 struct hwrm_cfa_eem_qcaps_output { 8921 __le16 error_code; 8922 __le16 req_type; 8923 __le16 seq_id; 8924 __le16 resp_len; 8925 __le32 flags; 8926 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8927 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8928 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8929 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8930 __le32 unused_0; 8931 __le32 supported; 8932 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8933 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8934 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8935 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8936 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8937 __le32 max_entries_supported; 8938 __le16 key_entry_size; 8939 __le16 record_entry_size; 8940 __le16 efc_entry_size; 8941 __le16 fid_entry_size; 8942 u8 unused_1[7]; 8943 u8 valid; 8944 }; 8945 8946 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8947 struct hwrm_cfa_eem_cfg_input { 8948 __le16 req_type; 8949 __le16 cmpl_ring; 8950 __le16 seq_id; 8951 __le16 target_id; 8952 __le64 resp_addr; 8953 __le32 flags; 8954 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8955 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8956 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8957 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8958 __le16 group_id; 8959 __le16 unused_0; 8960 __le32 num_entries; 8961 __le32 unused_1; 8962 __le16 key0_ctx_id; 8963 __le16 key1_ctx_id; 8964 __le16 record_ctx_id; 8965 __le16 efc_ctx_id; 8966 __le16 fid_ctx_id; 8967 __le16 unused_2; 8968 __le32 unused_3; 8969 }; 8970 8971 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8972 struct hwrm_cfa_eem_cfg_output { 8973 __le16 error_code; 8974 __le16 req_type; 8975 __le16 seq_id; 8976 __le16 resp_len; 8977 u8 unused_0[7]; 8978 u8 valid; 8979 }; 8980 8981 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8982 struct hwrm_cfa_eem_qcfg_input { 8983 __le16 req_type; 8984 __le16 cmpl_ring; 8985 __le16 seq_id; 8986 __le16 target_id; 8987 __le64 resp_addr; 8988 __le32 flags; 8989 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8990 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8991 __le32 unused_0; 8992 }; 8993 8994 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8995 struct hwrm_cfa_eem_qcfg_output { 8996 __le16 error_code; 8997 __le16 req_type; 8998 __le16 seq_id; 8999 __le16 resp_len; 9000 __le32 flags; 9001 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 9002 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 9003 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 9004 __le32 num_entries; 9005 __le16 key0_ctx_id; 9006 __le16 key1_ctx_id; 9007 __le16 record_ctx_id; 9008 __le16 efc_ctx_id; 9009 __le16 fid_ctx_id; 9010 u8 unused_2[5]; 9011 u8 valid; 9012 }; 9013 9014 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 9015 struct hwrm_cfa_eem_op_input { 9016 __le16 req_type; 9017 __le16 cmpl_ring; 9018 __le16 seq_id; 9019 __le16 target_id; 9020 __le64 resp_addr; 9021 __le32 flags; 9022 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 9023 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 9024 __le16 unused_0; 9025 __le16 op; 9026 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 9027 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 9028 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 9029 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 9030 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 9031 }; 9032 9033 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 9034 struct hwrm_cfa_eem_op_output { 9035 __le16 error_code; 9036 __le16 req_type; 9037 __le16 seq_id; 9038 __le16 resp_len; 9039 u8 unused_0[7]; 9040 u8 valid; 9041 }; 9042 9043 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 9044 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 9045 __le16 req_type; 9046 __le16 cmpl_ring; 9047 __le16 seq_id; 9048 __le16 target_id; 9049 __le64 resp_addr; 9050 __le32 unused_0[4]; 9051 }; 9052 9053 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 9054 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 9055 __le16 error_code; 9056 __le16 req_type; 9057 __le16 seq_id; 9058 __le16 resp_len; 9059 __le32 flags; 9060 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 9061 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 9062 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 9063 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 9064 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 9065 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 9066 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 9067 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 9068 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 9069 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 9070 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 9071 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 9072 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 9073 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 9074 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 9075 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 9076 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 9077 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 9078 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 9079 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 9080 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 9081 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 9082 u8 unused_0[3]; 9083 u8 valid; 9084 }; 9085 9086 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 9087 struct hwrm_tunnel_dst_port_query_input { 9088 __le16 req_type; 9089 __le16 cmpl_ring; 9090 __le16 seq_id; 9091 __le16 target_id; 9092 __le64 resp_addr; 9093 u8 tunnel_type; 9094 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 9095 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 9096 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 9097 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 9098 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 9099 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9100 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9101 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9102 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 9103 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9104 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 9105 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9106 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9107 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9108 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9109 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9110 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9111 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9112 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9113 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9114 u8 tunnel_next_proto; 9115 u8 unused_0[6]; 9116 }; 9117 9118 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 9119 struct hwrm_tunnel_dst_port_query_output { 9120 __le16 error_code; 9121 __le16 req_type; 9122 __le16 seq_id; 9123 __le16 resp_len; 9124 __le16 tunnel_dst_port_id; 9125 __be16 tunnel_dst_port_val; 9126 u8 upar_in_use; 9127 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 9128 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 9129 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 9130 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 9131 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 9132 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 9133 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 9134 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 9135 u8 status; 9136 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 9137 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 9138 u8 unused_0; 9139 u8 valid; 9140 }; 9141 9142 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 9143 struct hwrm_tunnel_dst_port_alloc_input { 9144 __le16 req_type; 9145 __le16 cmpl_ring; 9146 __le16 seq_id; 9147 __le16 target_id; 9148 __le64 resp_addr; 9149 u8 tunnel_type; 9150 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 9151 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 9152 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 9153 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 9154 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 9155 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9156 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9157 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9158 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 9159 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9160 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 9161 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9162 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9163 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9164 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9165 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9166 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9167 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9168 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9169 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9170 u8 tunnel_next_proto; 9171 __be16 tunnel_dst_port_val; 9172 u8 unused_0[4]; 9173 }; 9174 9175 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 9176 struct hwrm_tunnel_dst_port_alloc_output { 9177 __le16 error_code; 9178 __le16 req_type; 9179 __le16 seq_id; 9180 __le16 resp_len; 9181 __le16 tunnel_dst_port_id; 9182 u8 error_info; 9183 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 9184 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 9185 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 9186 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 9187 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 9188 u8 upar_in_use; 9189 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 9190 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 9191 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 9192 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 9193 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 9194 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 9195 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 9196 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 9197 u8 unused_0[3]; 9198 u8 valid; 9199 }; 9200 9201 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 9202 struct hwrm_tunnel_dst_port_free_input { 9203 __le16 req_type; 9204 __le16 cmpl_ring; 9205 __le16 seq_id; 9206 __le16 target_id; 9207 __le64 resp_addr; 9208 u8 tunnel_type; 9209 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 9210 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 9211 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 9212 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 9213 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 9214 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9215 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9216 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9217 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 9218 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9219 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 9220 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9221 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9222 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9223 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9224 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9225 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9226 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9227 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9228 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9229 u8 tunnel_next_proto; 9230 __le16 tunnel_dst_port_id; 9231 u8 unused_0[4]; 9232 }; 9233 9234 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 9235 struct hwrm_tunnel_dst_port_free_output { 9236 __le16 error_code; 9237 __le16 req_type; 9238 __le16 seq_id; 9239 __le16 resp_len; 9240 u8 error_info; 9241 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 9242 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 9243 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 9244 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 9245 u8 unused_1[6]; 9246 u8 valid; 9247 }; 9248 9249 /* ctx_hw_stats (size:1280b/160B) */ 9250 struct ctx_hw_stats { 9251 __le64 rx_ucast_pkts; 9252 __le64 rx_mcast_pkts; 9253 __le64 rx_bcast_pkts; 9254 __le64 rx_discard_pkts; 9255 __le64 rx_error_pkts; 9256 __le64 rx_ucast_bytes; 9257 __le64 rx_mcast_bytes; 9258 __le64 rx_bcast_bytes; 9259 __le64 tx_ucast_pkts; 9260 __le64 tx_mcast_pkts; 9261 __le64 tx_bcast_pkts; 9262 __le64 tx_error_pkts; 9263 __le64 tx_discard_pkts; 9264 __le64 tx_ucast_bytes; 9265 __le64 tx_mcast_bytes; 9266 __le64 tx_bcast_bytes; 9267 __le64 tpa_pkts; 9268 __le64 tpa_bytes; 9269 __le64 tpa_events; 9270 __le64 tpa_aborts; 9271 }; 9272 9273 /* ctx_hw_stats_ext (size:1408b/176B) */ 9274 struct ctx_hw_stats_ext { 9275 __le64 rx_ucast_pkts; 9276 __le64 rx_mcast_pkts; 9277 __le64 rx_bcast_pkts; 9278 __le64 rx_discard_pkts; 9279 __le64 rx_error_pkts; 9280 __le64 rx_ucast_bytes; 9281 __le64 rx_mcast_bytes; 9282 __le64 rx_bcast_bytes; 9283 __le64 tx_ucast_pkts; 9284 __le64 tx_mcast_pkts; 9285 __le64 tx_bcast_pkts; 9286 __le64 tx_error_pkts; 9287 __le64 tx_discard_pkts; 9288 __le64 tx_ucast_bytes; 9289 __le64 tx_mcast_bytes; 9290 __le64 tx_bcast_bytes; 9291 __le64 rx_tpa_eligible_pkt; 9292 __le64 rx_tpa_eligible_bytes; 9293 __le64 rx_tpa_pkt; 9294 __le64 rx_tpa_bytes; 9295 __le64 rx_tpa_errors; 9296 __le64 rx_tpa_events; 9297 }; 9298 9299 /* hwrm_stat_ctx_alloc_input (size:384b/48B) */ 9300 struct hwrm_stat_ctx_alloc_input { 9301 __le16 req_type; 9302 __le16 cmpl_ring; 9303 __le16 seq_id; 9304 __le16 target_id; 9305 __le64 resp_addr; 9306 __le64 stats_dma_addr; 9307 __le32 update_period_ms; 9308 u8 stat_ctx_flags; 9309 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 9310 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF 0x2UL 9311 u8 unused_0; 9312 __le16 stats_dma_length; 9313 __le16 flags; 9314 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 9315 __le16 steering_tag; 9316 __le32 stat_ctx_id; 9317 __le16 alloc_seq_id; 9318 u8 unused_1[6]; 9319 }; 9320 9321 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 9322 struct hwrm_stat_ctx_alloc_output { 9323 __le16 error_code; 9324 __le16 req_type; 9325 __le16 seq_id; 9326 __le16 resp_len; 9327 __le32 stat_ctx_id; 9328 u8 unused_0[3]; 9329 u8 valid; 9330 }; 9331 9332 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 9333 struct hwrm_stat_ctx_free_input { 9334 __le16 req_type; 9335 __le16 cmpl_ring; 9336 __le16 seq_id; 9337 __le16 target_id; 9338 __le64 resp_addr; 9339 __le32 stat_ctx_id; 9340 u8 unused_0[4]; 9341 }; 9342 9343 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 9344 struct hwrm_stat_ctx_free_output { 9345 __le16 error_code; 9346 __le16 req_type; 9347 __le16 seq_id; 9348 __le16 resp_len; 9349 __le32 stat_ctx_id; 9350 u8 unused_0[3]; 9351 u8 valid; 9352 }; 9353 9354 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 9355 struct hwrm_stat_ctx_query_input { 9356 __le16 req_type; 9357 __le16 cmpl_ring; 9358 __le16 seq_id; 9359 __le16 target_id; 9360 __le64 resp_addr; 9361 __le32 stat_ctx_id; 9362 u8 flags; 9363 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 9364 u8 unused_0[3]; 9365 }; 9366 9367 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 9368 struct hwrm_stat_ctx_query_output { 9369 __le16 error_code; 9370 __le16 req_type; 9371 __le16 seq_id; 9372 __le16 resp_len; 9373 __le64 tx_ucast_pkts; 9374 __le64 tx_mcast_pkts; 9375 __le64 tx_bcast_pkts; 9376 __le64 tx_discard_pkts; 9377 __le64 tx_error_pkts; 9378 __le64 tx_ucast_bytes; 9379 __le64 tx_mcast_bytes; 9380 __le64 tx_bcast_bytes; 9381 __le64 rx_ucast_pkts; 9382 __le64 rx_mcast_pkts; 9383 __le64 rx_bcast_pkts; 9384 __le64 rx_discard_pkts; 9385 __le64 rx_error_pkts; 9386 __le64 rx_ucast_bytes; 9387 __le64 rx_mcast_bytes; 9388 __le64 rx_bcast_bytes; 9389 __le64 rx_agg_pkts; 9390 __le64 rx_agg_bytes; 9391 __le64 rx_agg_events; 9392 __le64 rx_agg_aborts; 9393 u8 unused_0[7]; 9394 u8 valid; 9395 }; 9396 9397 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 9398 struct hwrm_stat_ext_ctx_query_input { 9399 __le16 req_type; 9400 __le16 cmpl_ring; 9401 __le16 seq_id; 9402 __le16 target_id; 9403 __le64 resp_addr; 9404 __le32 stat_ctx_id; 9405 u8 flags; 9406 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 9407 u8 unused_0[3]; 9408 }; 9409 9410 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 9411 struct hwrm_stat_ext_ctx_query_output { 9412 __le16 error_code; 9413 __le16 req_type; 9414 __le16 seq_id; 9415 __le16 resp_len; 9416 __le64 rx_ucast_pkts; 9417 __le64 rx_mcast_pkts; 9418 __le64 rx_bcast_pkts; 9419 __le64 rx_discard_pkts; 9420 __le64 rx_error_pkts; 9421 __le64 rx_ucast_bytes; 9422 __le64 rx_mcast_bytes; 9423 __le64 rx_bcast_bytes; 9424 __le64 tx_ucast_pkts; 9425 __le64 tx_mcast_pkts; 9426 __le64 tx_bcast_pkts; 9427 __le64 tx_error_pkts; 9428 __le64 tx_discard_pkts; 9429 __le64 tx_ucast_bytes; 9430 __le64 tx_mcast_bytes; 9431 __le64 tx_bcast_bytes; 9432 __le64 rx_tpa_eligible_pkt; 9433 __le64 rx_tpa_eligible_bytes; 9434 __le64 rx_tpa_pkt; 9435 __le64 rx_tpa_bytes; 9436 __le64 rx_tpa_errors; 9437 __le64 rx_tpa_events; 9438 u8 unused_0[7]; 9439 u8 valid; 9440 }; 9441 9442 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 9443 struct hwrm_stat_ctx_clr_stats_input { 9444 __le16 req_type; 9445 __le16 cmpl_ring; 9446 __le16 seq_id; 9447 __le16 target_id; 9448 __le64 resp_addr; 9449 __le32 stat_ctx_id; 9450 u8 unused_0[4]; 9451 }; 9452 9453 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 9454 struct hwrm_stat_ctx_clr_stats_output { 9455 __le16 error_code; 9456 __le16 req_type; 9457 __le16 seq_id; 9458 __le16 resp_len; 9459 u8 unused_0[7]; 9460 u8 valid; 9461 }; 9462 9463 /* hwrm_pcie_qstats_input (size:256b/32B) */ 9464 struct hwrm_pcie_qstats_input { 9465 __le16 req_type; 9466 __le16 cmpl_ring; 9467 __le16 seq_id; 9468 __le16 target_id; 9469 __le64 resp_addr; 9470 __le16 pcie_stat_size; 9471 u8 unused_0[6]; 9472 __le64 pcie_stat_host_addr; 9473 }; 9474 9475 /* hwrm_pcie_qstats_output (size:128b/16B) */ 9476 struct hwrm_pcie_qstats_output { 9477 __le16 error_code; 9478 __le16 req_type; 9479 __le16 seq_id; 9480 __le16 resp_len; 9481 __le16 pcie_stat_size; 9482 u8 unused_0[5]; 9483 u8 valid; 9484 }; 9485 9486 /* pcie_ctx_hw_stats (size:768b/96B) */ 9487 struct pcie_ctx_hw_stats { 9488 __le64 pcie_pl_signal_integrity; 9489 __le64 pcie_dl_signal_integrity; 9490 __le64 pcie_tl_signal_integrity; 9491 __le64 pcie_link_integrity; 9492 __le64 pcie_tx_traffic_rate; 9493 __le64 pcie_rx_traffic_rate; 9494 __le64 pcie_tx_dllp_statistics; 9495 __le64 pcie_rx_dllp_statistics; 9496 __le64 pcie_equalization_time; 9497 __le32 pcie_ltssm_histogram[4]; 9498 __le64 pcie_recovery_histogram; 9499 }; 9500 9501 /* pcie_ctx_hw_stats_v2 (size:4544b/568B) */ 9502 struct pcie_ctx_hw_stats_v2 { 9503 __le64 pcie_pl_signal_integrity; 9504 __le64 pcie_dl_signal_integrity; 9505 __le64 pcie_tl_signal_integrity; 9506 __le64 pcie_link_integrity; 9507 __le64 pcie_tx_traffic_rate; 9508 __le64 pcie_rx_traffic_rate; 9509 __le64 pcie_tx_dllp_statistics; 9510 __le64 pcie_rx_dllp_statistics; 9511 __le64 pcie_equalization_time; 9512 __le32 pcie_ltssm_histogram[4]; 9513 __le64 pcie_recovery_histogram; 9514 __le32 pcie_tl_credit_nph_histogram[8]; 9515 __le32 pcie_tl_credit_ph_histogram[8]; 9516 __le32 pcie_tl_credit_pd_histogram[8]; 9517 __le32 pcie_cmpl_latest_times[4]; 9518 __le32 pcie_cmpl_longest_time; 9519 __le32 pcie_cmpl_shortest_time; 9520 __le32 unused_0[2]; 9521 __le32 pcie_cmpl_latest_headers[4][4]; 9522 __le32 pcie_cmpl_longest_headers[4][4]; 9523 __le32 pcie_cmpl_shortest_headers[4][4]; 9524 __le32 pcie_wr_latency_histogram[12]; 9525 __le32 pcie_wr_latency_all_normal_count; 9526 __le32 unused_1; 9527 __le64 pcie_posted_packet_count; 9528 __le64 pcie_non_posted_packet_count; 9529 __le64 pcie_other_packet_count; 9530 __le64 pcie_blocked_packet_count; 9531 __le64 pcie_cmpl_packet_count; 9532 __le32 pcie_rd_latency_histogram[12]; 9533 __le32 pcie_rd_latency_all_normal_count; 9534 __le32 unused_2; 9535 }; 9536 9537 /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 9538 struct hwrm_stat_generic_qstats_input { 9539 __le16 req_type; 9540 __le16 cmpl_ring; 9541 __le16 seq_id; 9542 __le16 target_id; 9543 __le64 resp_addr; 9544 __le16 generic_stat_size; 9545 u8 flags; 9546 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 9547 u8 unused_0[5]; 9548 __le64 generic_stat_host_addr; 9549 }; 9550 9551 /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 9552 struct hwrm_stat_generic_qstats_output { 9553 __le16 error_code; 9554 __le16 req_type; 9555 __le16 seq_id; 9556 __le16 resp_len; 9557 __le16 generic_stat_size; 9558 u8 unused_0[5]; 9559 u8 valid; 9560 }; 9561 9562 /* generic_sw_hw_stats (size:1472b/184B) */ 9563 struct generic_sw_hw_stats { 9564 __le64 pcie_statistics_tx_tlp; 9565 __le64 pcie_statistics_rx_tlp; 9566 __le64 pcie_credit_fc_hdr_posted; 9567 __le64 pcie_credit_fc_hdr_nonposted; 9568 __le64 pcie_credit_fc_hdr_cmpl; 9569 __le64 pcie_credit_fc_data_posted; 9570 __le64 pcie_credit_fc_data_nonposted; 9571 __le64 pcie_credit_fc_data_cmpl; 9572 __le64 pcie_credit_fc_tgt_nonposted; 9573 __le64 pcie_credit_fc_tgt_data_posted; 9574 __le64 pcie_credit_fc_tgt_hdr_posted; 9575 __le64 pcie_credit_fc_cmpl_hdr_posted; 9576 __le64 pcie_credit_fc_cmpl_data_posted; 9577 __le64 pcie_cmpl_longest; 9578 __le64 pcie_cmpl_shortest; 9579 __le64 cache_miss_count_cfcq; 9580 __le64 cache_miss_count_cfcs; 9581 __le64 cache_miss_count_cfcc; 9582 __le64 cache_miss_count_cfcm; 9583 __le64 hw_db_recov_dbs_dropped; 9584 __le64 hw_db_recov_drops_serviced; 9585 __le64 hw_db_recov_dbs_recovered; 9586 __le64 hw_db_recov_oo_drop_count; 9587 }; 9588 9589 /* hwrm_fw_reset_input (size:192b/24B) */ 9590 struct hwrm_fw_reset_input { 9591 __le16 req_type; 9592 __le16 cmpl_ring; 9593 __le16 seq_id; 9594 __le16 target_id; 9595 __le64 resp_addr; 9596 u8 embedded_proc_type; 9597 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9598 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9599 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9600 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9601 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9602 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9603 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9604 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 9605 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 9606 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 9607 u8 selfrst_status; 9608 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 9609 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 9610 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9611 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9612 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 9613 u8 host_idx; 9614 u8 flags; 9615 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 9616 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 9617 u8 unused_0[4]; 9618 }; 9619 9620 /* hwrm_fw_reset_output (size:128b/16B) */ 9621 struct hwrm_fw_reset_output { 9622 __le16 error_code; 9623 __le16 req_type; 9624 __le16 seq_id; 9625 __le16 resp_len; 9626 u8 selfrst_status; 9627 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9628 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9629 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9630 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9631 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 9632 u8 unused_0[6]; 9633 u8 valid; 9634 }; 9635 9636 /* hwrm_fw_qstatus_input (size:192b/24B) */ 9637 struct hwrm_fw_qstatus_input { 9638 __le16 req_type; 9639 __le16 cmpl_ring; 9640 __le16 seq_id; 9641 __le16 target_id; 9642 __le64 resp_addr; 9643 u8 embedded_proc_type; 9644 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9645 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9646 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9647 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9648 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9649 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9650 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9651 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 9652 u8 unused_0[7]; 9653 }; 9654 9655 /* hwrm_fw_qstatus_output (size:128b/16B) */ 9656 struct hwrm_fw_qstatus_output { 9657 __le16 error_code; 9658 __le16 req_type; 9659 __le16 seq_id; 9660 __le16 resp_len; 9661 u8 selfrst_status; 9662 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9663 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9664 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9665 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 9666 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 9667 u8 nvm_option_action_status; 9668 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 9669 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 9670 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 9671 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 9672 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 9673 u8 unused_0[5]; 9674 u8 valid; 9675 }; 9676 9677 /* hwrm_fw_set_time_input (size:256b/32B) */ 9678 struct hwrm_fw_set_time_input { 9679 __le16 req_type; 9680 __le16 cmpl_ring; 9681 __le16 seq_id; 9682 __le16 target_id; 9683 __le64 resp_addr; 9684 __le16 year; 9685 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 9686 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 9687 u8 month; 9688 u8 day; 9689 u8 hour; 9690 u8 minute; 9691 u8 second; 9692 u8 unused_0; 9693 __le16 millisecond; 9694 __le16 zone; 9695 #define FW_SET_TIME_REQ_ZONE_UTC 0 9696 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 9697 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 9698 u8 unused_1[4]; 9699 }; 9700 9701 /* hwrm_fw_set_time_output (size:128b/16B) */ 9702 struct hwrm_fw_set_time_output { 9703 __le16 error_code; 9704 __le16 req_type; 9705 __le16 seq_id; 9706 __le16 resp_len; 9707 u8 unused_0[7]; 9708 u8 valid; 9709 }; 9710 9711 /* hwrm_struct_hdr (size:128b/16B) */ 9712 struct hwrm_struct_hdr { 9713 __le16 struct_id; 9714 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9715 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9716 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9717 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9718 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9719 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9720 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9721 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9722 #define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL 9723 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9724 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9725 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9726 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9727 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL 9728 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL 9729 #define STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 0x190UL 9730 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 9731 __le16 len; 9732 u8 version; 9733 #define STRUCT_HDR_VERSION_0 0x0UL 9734 #define STRUCT_HDR_VERSION_1 0x1UL 9735 #define STRUCT_HDR_VERSION_LAST STRUCT_HDR_VERSION_1 9736 u8 count; 9737 __le16 subtype; 9738 __le16 next_offset; 9739 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9740 u8 unused_0[6]; 9741 }; 9742 9743 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9744 struct hwrm_struct_data_dcbx_app { 9745 __be16 protocol_id; 9746 u8 protocol_selector; 9747 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9748 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9749 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9750 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9751 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9752 u8 priority; 9753 u8 valid; 9754 u8 unused_0[3]; 9755 }; 9756 9757 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9758 struct hwrm_fw_set_structured_data_input { 9759 __le16 req_type; 9760 __le16 cmpl_ring; 9761 __le16 seq_id; 9762 __le16 target_id; 9763 __le64 resp_addr; 9764 __le64 src_data_addr; 9765 __le16 data_len; 9766 u8 hdr_cnt; 9767 u8 unused_0[5]; 9768 }; 9769 9770 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9771 struct hwrm_fw_set_structured_data_output { 9772 __le16 error_code; 9773 __le16 req_type; 9774 __le16 seq_id; 9775 __le16 resp_len; 9776 u8 unused_0[7]; 9777 u8 valid; 9778 }; 9779 9780 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9781 struct hwrm_fw_set_structured_data_cmd_err { 9782 u8 code; 9783 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9784 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9785 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9786 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9787 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_ALREADY_ADDED 0x4UL 9788 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 0x5UL 9789 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 9790 u8 unused_0[7]; 9791 }; 9792 9793 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9794 struct hwrm_fw_get_structured_data_input { 9795 __le16 req_type; 9796 __le16 cmpl_ring; 9797 __le16 seq_id; 9798 __le16 target_id; 9799 __le64 resp_addr; 9800 __le64 dest_data_addr; 9801 __le16 data_len; 9802 __le16 structure_id; 9803 __le16 subtype; 9804 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9805 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9806 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9807 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9808 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9809 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9810 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9811 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9812 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9813 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_SUPPORTED 0x320UL 9814 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 0x321UL 9815 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 9816 u8 count; 9817 u8 unused_0; 9818 }; 9819 9820 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9821 struct hwrm_fw_get_structured_data_output { 9822 __le16 error_code; 9823 __le16 req_type; 9824 __le16 seq_id; 9825 __le16 resp_len; 9826 u8 hdr_cnt; 9827 u8 unused_0[6]; 9828 u8 valid; 9829 }; 9830 9831 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9832 struct hwrm_fw_get_structured_data_cmd_err { 9833 u8 code; 9834 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9835 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9836 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9837 u8 unused_0[7]; 9838 }; 9839 9840 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9841 struct hwrm_fw_livepatch_query_input { 9842 __le16 req_type; 9843 __le16 cmpl_ring; 9844 __le16 seq_id; 9845 __le16 target_id; 9846 __le64 resp_addr; 9847 u8 fw_target; 9848 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9849 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9850 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9851 u8 unused_0[7]; 9852 }; 9853 9854 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9855 struct hwrm_fw_livepatch_query_output { 9856 __le16 error_code; 9857 __le16 req_type; 9858 __le16 seq_id; 9859 __le16 resp_len; 9860 char install_ver[32]; 9861 char active_ver[32]; 9862 __le16 status_flags; 9863 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9864 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9865 u8 unused_0[5]; 9866 u8 valid; 9867 }; 9868 9869 /* hwrm_fw_livepatch_input (size:256b/32B) */ 9870 struct hwrm_fw_livepatch_input { 9871 __le16 req_type; 9872 __le16 cmpl_ring; 9873 __le16 seq_id; 9874 __le16 target_id; 9875 __le64 resp_addr; 9876 u8 opcode; 9877 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9878 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9879 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9880 u8 fw_target; 9881 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9882 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9883 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9884 u8 loadtype; 9885 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9886 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9887 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9888 u8 flags; 9889 __le32 patch_len; 9890 __le64 host_addr; 9891 }; 9892 9893 /* hwrm_fw_livepatch_output (size:128b/16B) */ 9894 struct hwrm_fw_livepatch_output { 9895 __le16 error_code; 9896 __le16 req_type; 9897 __le16 seq_id; 9898 __le16 resp_len; 9899 u8 unused_0[7]; 9900 u8 valid; 9901 }; 9902 9903 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9904 struct hwrm_fw_livepatch_cmd_err { 9905 u8 code; 9906 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9907 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9908 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9909 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9910 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9911 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9912 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9913 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9914 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9915 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9916 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9917 u8 unused_0[7]; 9918 }; 9919 9920 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9921 struct hwrm_exec_fwd_resp_input { 9922 __le16 req_type; 9923 __le16 cmpl_ring; 9924 __le16 seq_id; 9925 __le16 target_id; 9926 __le64 resp_addr; 9927 __le32 encap_request[26]; 9928 __le16 encap_resp_target_id; 9929 u8 unused_0[6]; 9930 }; 9931 9932 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9933 struct hwrm_exec_fwd_resp_output { 9934 __le16 error_code; 9935 __le16 req_type; 9936 __le16 seq_id; 9937 __le16 resp_len; 9938 u8 unused_0[7]; 9939 u8 valid; 9940 }; 9941 9942 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9943 struct hwrm_reject_fwd_resp_input { 9944 __le16 req_type; 9945 __le16 cmpl_ring; 9946 __le16 seq_id; 9947 __le16 target_id; 9948 __le64 resp_addr; 9949 __le32 encap_request[26]; 9950 __le16 encap_resp_target_id; 9951 u8 unused_0[6]; 9952 }; 9953 9954 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9955 struct hwrm_reject_fwd_resp_output { 9956 __le16 error_code; 9957 __le16 req_type; 9958 __le16 seq_id; 9959 __le16 resp_len; 9960 u8 unused_0[7]; 9961 u8 valid; 9962 }; 9963 9964 /* hwrm_fwd_resp_input (size:1024b/128B) */ 9965 struct hwrm_fwd_resp_input { 9966 __le16 req_type; 9967 __le16 cmpl_ring; 9968 __le16 seq_id; 9969 __le16 target_id; 9970 __le64 resp_addr; 9971 __le16 encap_resp_target_id; 9972 __le16 encap_resp_cmpl_ring; 9973 __le16 encap_resp_len; 9974 u8 unused_0; 9975 u8 unused_1; 9976 __le64 encap_resp_addr; 9977 __le32 encap_resp[24]; 9978 }; 9979 9980 /* hwrm_fwd_resp_output (size:128b/16B) */ 9981 struct hwrm_fwd_resp_output { 9982 __le16 error_code; 9983 __le16 req_type; 9984 __le16 seq_id; 9985 __le16 resp_len; 9986 u8 unused_0[7]; 9987 u8 valid; 9988 }; 9989 9990 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9991 struct hwrm_fwd_async_event_cmpl_input { 9992 __le16 req_type; 9993 __le16 cmpl_ring; 9994 __le16 seq_id; 9995 __le16 target_id; 9996 __le64 resp_addr; 9997 __le16 encap_async_event_target_id; 9998 u8 unused_0[6]; 9999 __le32 encap_async_event_cmpl[4]; 10000 }; 10001 10002 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 10003 struct hwrm_fwd_async_event_cmpl_output { 10004 __le16 error_code; 10005 __le16 req_type; 10006 __le16 seq_id; 10007 __le16 resp_len; 10008 u8 unused_0[7]; 10009 u8 valid; 10010 }; 10011 10012 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 10013 struct hwrm_temp_monitor_query_input { 10014 __le16 req_type; 10015 __le16 cmpl_ring; 10016 __le16 seq_id; 10017 __le16 target_id; 10018 __le64 resp_addr; 10019 }; 10020 10021 /* hwrm_temp_monitor_query_output (size:192b/24B) */ 10022 struct hwrm_temp_monitor_query_output { 10023 __le16 error_code; 10024 __le16 req_type; 10025 __le16 seq_id; 10026 __le16 resp_len; 10027 u8 temp; 10028 u8 phy_temp; 10029 u8 om_temp; 10030 u8 flags; 10031 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 10032 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 10033 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 10034 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 10035 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 10036 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 10037 u8 temp2; 10038 u8 phy_temp2; 10039 u8 om_temp2; 10040 u8 warn_threshold; 10041 u8 critical_threshold; 10042 u8 fatal_threshold; 10043 u8 shutdown_threshold; 10044 u8 unused_0[4]; 10045 u8 valid; 10046 }; 10047 10048 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 10049 struct hwrm_wol_filter_alloc_input { 10050 __le16 req_type; 10051 __le16 cmpl_ring; 10052 __le16 seq_id; 10053 __le16 target_id; 10054 __le64 resp_addr; 10055 __le32 flags; 10056 __le32 enables; 10057 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 10058 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 10059 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 10060 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 10061 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 10062 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 10063 __le16 port_id; 10064 u8 wol_type; 10065 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 10066 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 10067 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 10068 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 10069 u8 unused_0[5]; 10070 u8 mac_address[6]; 10071 __le16 pattern_offset; 10072 __le16 pattern_buf_size; 10073 __le16 pattern_mask_size; 10074 u8 unused_1[4]; 10075 __le64 pattern_buf_addr; 10076 __le64 pattern_mask_addr; 10077 }; 10078 10079 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 10080 struct hwrm_wol_filter_alloc_output { 10081 __le16 error_code; 10082 __le16 req_type; 10083 __le16 seq_id; 10084 __le16 resp_len; 10085 u8 wol_filter_id; 10086 u8 unused_0[6]; 10087 u8 valid; 10088 }; 10089 10090 /* hwrm_wol_filter_free_input (size:256b/32B) */ 10091 struct hwrm_wol_filter_free_input { 10092 __le16 req_type; 10093 __le16 cmpl_ring; 10094 __le16 seq_id; 10095 __le16 target_id; 10096 __le64 resp_addr; 10097 __le32 flags; 10098 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 10099 __le32 enables; 10100 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 10101 __le16 port_id; 10102 u8 wol_filter_id; 10103 u8 unused_0[5]; 10104 }; 10105 10106 /* hwrm_wol_filter_free_output (size:128b/16B) */ 10107 struct hwrm_wol_filter_free_output { 10108 __le16 error_code; 10109 __le16 req_type; 10110 __le16 seq_id; 10111 __le16 resp_len; 10112 u8 unused_0[7]; 10113 u8 valid; 10114 }; 10115 10116 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 10117 struct hwrm_wol_filter_qcfg_input { 10118 __le16 req_type; 10119 __le16 cmpl_ring; 10120 __le16 seq_id; 10121 __le16 target_id; 10122 __le64 resp_addr; 10123 __le16 port_id; 10124 __le16 handle; 10125 u8 unused_0[4]; 10126 __le64 pattern_buf_addr; 10127 __le16 pattern_buf_size; 10128 u8 unused_1[6]; 10129 __le64 pattern_mask_addr; 10130 __le16 pattern_mask_size; 10131 u8 unused_2[6]; 10132 }; 10133 10134 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 10135 struct hwrm_wol_filter_qcfg_output { 10136 __le16 error_code; 10137 __le16 req_type; 10138 __le16 seq_id; 10139 __le16 resp_len; 10140 __le16 next_handle; 10141 u8 wol_filter_id; 10142 u8 wol_type; 10143 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 10144 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 10145 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 10146 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 10147 __le32 unused_0; 10148 u8 mac_address[6]; 10149 __le16 pattern_offset; 10150 __le16 pattern_size; 10151 __le16 pattern_mask_size; 10152 u8 unused_1[3]; 10153 u8 valid; 10154 }; 10155 10156 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 10157 struct hwrm_wol_reason_qcfg_input { 10158 __le16 req_type; 10159 __le16 cmpl_ring; 10160 __le16 seq_id; 10161 __le16 target_id; 10162 __le64 resp_addr; 10163 __le16 port_id; 10164 u8 unused_0[6]; 10165 __le64 wol_pkt_buf_addr; 10166 __le16 wol_pkt_buf_size; 10167 u8 unused_1[6]; 10168 }; 10169 10170 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 10171 struct hwrm_wol_reason_qcfg_output { 10172 __le16 error_code; 10173 __le16 req_type; 10174 __le16 seq_id; 10175 __le16 resp_len; 10176 u8 wol_filter_id; 10177 u8 wol_reason; 10178 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 10179 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 10180 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 10181 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 10182 u8 wol_pkt_len; 10183 u8 unused_0[4]; 10184 u8 valid; 10185 }; 10186 10187 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 10188 struct hwrm_dbg_read_direct_input { 10189 __le16 req_type; 10190 __le16 cmpl_ring; 10191 __le16 seq_id; 10192 __le16 target_id; 10193 __le64 resp_addr; 10194 __le64 host_dest_addr; 10195 __le32 read_addr; 10196 __le32 read_len32; 10197 }; 10198 10199 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 10200 struct hwrm_dbg_read_direct_output { 10201 __le16 error_code; 10202 __le16 req_type; 10203 __le16 seq_id; 10204 __le16 resp_len; 10205 __le32 crc32; 10206 u8 unused_0[3]; 10207 u8 valid; 10208 }; 10209 10210 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 10211 struct hwrm_dbg_qcaps_input { 10212 __le16 req_type; 10213 __le16 cmpl_ring; 10214 __le16 seq_id; 10215 __le16 target_id; 10216 __le64 resp_addr; 10217 __le16 fid; 10218 u8 unused_0[6]; 10219 }; 10220 10221 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 10222 struct hwrm_dbg_qcaps_output { 10223 __le16 error_code; 10224 __le16 req_type; 10225 __le16 seq_id; 10226 __le16 resp_len; 10227 __le16 fid; 10228 u8 unused_0[2]; 10229 __le32 coredump_component_disable_caps; 10230 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 10231 __le32 flags; 10232 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 10233 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 10234 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 10235 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 10236 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL 10237 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL 10238 #define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL 10239 #define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL 10240 u8 unused_1[3]; 10241 u8 valid; 10242 }; 10243 10244 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 10245 struct hwrm_dbg_qcfg_input { 10246 __le16 req_type; 10247 __le16 cmpl_ring; 10248 __le16 seq_id; 10249 __le16 target_id; 10250 __le64 resp_addr; 10251 __le16 fid; 10252 __le16 flags; 10253 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 10254 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 10255 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 10256 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 10257 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 10258 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 10259 __le32 coredump_component_disable_flags; 10260 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 10261 }; 10262 10263 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 10264 struct hwrm_dbg_qcfg_output { 10265 __le16 error_code; 10266 __le16 req_type; 10267 __le16 seq_id; 10268 __le16 resp_len; 10269 __le16 fid; 10270 u8 unused_0[2]; 10271 __le32 coredump_size; 10272 __le32 flags; 10273 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 10274 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 10275 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 10276 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 10277 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 10278 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 10279 __le16 async_cmpl_ring; 10280 u8 unused_2[2]; 10281 __le32 crashdump_size; 10282 u8 unused_3[3]; 10283 u8 valid; 10284 }; 10285 10286 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 10287 struct hwrm_dbg_crashdump_medium_cfg_input { 10288 __le16 req_type; 10289 __le16 cmpl_ring; 10290 __le16 seq_id; 10291 __le16 target_id; 10292 __le64 resp_addr; 10293 __le16 output_dest_flags; 10294 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 10295 __le16 pg_size_lvl; 10296 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 10297 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 10298 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 10299 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 10300 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 10301 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 10302 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 10303 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 10304 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 10305 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 10306 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 10307 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 10308 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 10309 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 10310 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 10311 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 10312 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 10313 __le32 size; 10314 __le32 coredump_component_disable_flags; 10315 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 10316 __le32 unused_0; 10317 __le64 pbl; 10318 }; 10319 10320 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 10321 struct hwrm_dbg_crashdump_medium_cfg_output { 10322 __le16 error_code; 10323 __le16 req_type; 10324 __le16 seq_id; 10325 __le16 resp_len; 10326 u8 unused_1[7]; 10327 u8 valid; 10328 }; 10329 10330 /* coredump_segment_record (size:128b/16B) */ 10331 struct coredump_segment_record { 10332 __le16 component_id; 10333 __le16 segment_id; 10334 __le16 max_instances; 10335 u8 version_hi; 10336 u8 version_low; 10337 u8 seg_flags; 10338 u8 compress_flags; 10339 #define SFLAG_COMPRESSED_ZLIB 0x1UL 10340 u8 unused_0[2]; 10341 __le32 segment_len; 10342 }; 10343 10344 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 10345 struct hwrm_dbg_coredump_list_input { 10346 __le16 req_type; 10347 __le16 cmpl_ring; 10348 __le16 seq_id; 10349 __le16 target_id; 10350 __le64 resp_addr; 10351 __le64 host_dest_addr; 10352 __le32 host_buf_len; 10353 __le16 seq_no; 10354 u8 flags; 10355 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 10356 u8 unused_0[1]; 10357 }; 10358 10359 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 10360 struct hwrm_dbg_coredump_list_output { 10361 __le16 error_code; 10362 __le16 req_type; 10363 __le16 seq_id; 10364 __le16 resp_len; 10365 u8 flags; 10366 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 10367 u8 unused_0; 10368 __le16 total_segments; 10369 __le16 data_len; 10370 u8 unused_1; 10371 u8 valid; 10372 }; 10373 10374 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 10375 struct hwrm_dbg_coredump_initiate_input { 10376 __le16 req_type; 10377 __le16 cmpl_ring; 10378 __le16 seq_id; 10379 __le16 target_id; 10380 __le64 resp_addr; 10381 __le16 component_id; 10382 __le16 segment_id; 10383 __le16 instance; 10384 __le16 unused_0; 10385 u8 seg_flags; 10386 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA 0x1UL 10387 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA 0x2UL 10388 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE 0x4UL 10389 u8 unused_1[7]; 10390 }; 10391 10392 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 10393 struct hwrm_dbg_coredump_initiate_output { 10394 __le16 error_code; 10395 __le16 req_type; 10396 __le16 seq_id; 10397 __le16 resp_len; 10398 u8 unused_0[7]; 10399 u8 valid; 10400 }; 10401 10402 /* coredump_data_hdr (size:128b/16B) */ 10403 struct coredump_data_hdr { 10404 __le32 address; 10405 __le32 flags_length; 10406 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 10407 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 10408 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 10409 __le32 instance; 10410 __le32 next_offset; 10411 }; 10412 10413 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 10414 struct hwrm_dbg_coredump_retrieve_input { 10415 __le16 req_type; 10416 __le16 cmpl_ring; 10417 __le16 seq_id; 10418 __le16 target_id; 10419 __le64 resp_addr; 10420 __le64 host_dest_addr; 10421 __le32 host_buf_len; 10422 __le32 unused_0; 10423 __le16 component_id; 10424 __le16 segment_id; 10425 __le16 instance; 10426 __le16 unused_1; 10427 u8 seg_flags; 10428 #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_LIVE_DATA 0x1UL 10429 #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_CRASHED_DATA 0x2UL 10430 #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_NO_COMPRESS 0x4UL 10431 u8 unused_2; 10432 __le16 unused_3; 10433 __le32 unused_4; 10434 __le32 seq_no; 10435 __le32 unused_5; 10436 }; 10437 10438 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 10439 struct hwrm_dbg_coredump_retrieve_output { 10440 __le16 error_code; 10441 __le16 req_type; 10442 __le16 seq_id; 10443 __le16 resp_len; 10444 u8 flags; 10445 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 10446 u8 unused_0; 10447 __le16 data_len; 10448 u8 unused_1[3]; 10449 u8 valid; 10450 }; 10451 10452 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 10453 struct hwrm_dbg_ring_info_get_input { 10454 __le16 req_type; 10455 __le16 cmpl_ring; 10456 __le16 seq_id; 10457 __le16 target_id; 10458 __le64 resp_addr; 10459 u8 ring_type; 10460 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 10461 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 10462 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 10463 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 10464 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 10465 u8 unused_0[3]; 10466 __le32 fw_ring_id; 10467 }; 10468 10469 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 10470 struct hwrm_dbg_ring_info_get_output { 10471 __le16 error_code; 10472 __le16 req_type; 10473 __le16 seq_id; 10474 __le16 resp_len; 10475 __le32 producer_index; 10476 __le32 consumer_index; 10477 __le32 cag_vector_ctrl; 10478 __le16 st_tag; 10479 u8 unused_0; 10480 u8 valid; 10481 }; 10482 10483 /* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ 10484 struct hwrm_dbg_log_buffer_flush_input { 10485 __le16 req_type; 10486 __le16 cmpl_ring; 10487 __le16 seq_id; 10488 __le16 target_id; 10489 __le64 resp_addr; 10490 __le16 type; 10491 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT_TRACE 0x0UL 10492 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT2_TRACE 0x1UL 10493 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT_TRACE 0x2UL 10494 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT2_TRACE 0x3UL 10495 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP0_TRACE 0x4UL 10496 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_L2_HWRM_TRACE 0x5UL 10497 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ROCE_HWRM_TRACE 0x6UL 10498 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA0_TRACE 0x7UL 10499 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE 0x8UL 10500 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL 10501 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL 10502 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 10503 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 0xcUL 10504 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 10505 u8 unused_1[2]; 10506 __le32 flags; 10507 #define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL 10508 }; 10509 10510 /* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ 10511 struct hwrm_dbg_log_buffer_flush_output { 10512 __le16 error_code; 10513 __le16 req_type; 10514 __le16 seq_id; 10515 __le16 resp_len; 10516 __le32 current_buffer_offset; 10517 u8 unused_1[3]; 10518 u8 valid; 10519 }; 10520 10521 /* hwrm_nvm_read_input (size:320b/40B) */ 10522 struct hwrm_nvm_read_input { 10523 __le16 req_type; 10524 __le16 cmpl_ring; 10525 __le16 seq_id; 10526 __le16 target_id; 10527 __le64 resp_addr; 10528 __le64 host_dest_addr; 10529 __le16 dir_idx; 10530 u8 unused_0[2]; 10531 __le32 offset; 10532 __le32 len; 10533 u8 unused_1[4]; 10534 }; 10535 10536 /* hwrm_nvm_read_output (size:128b/16B) */ 10537 struct hwrm_nvm_read_output { 10538 __le16 error_code; 10539 __le16 req_type; 10540 __le16 seq_id; 10541 __le16 resp_len; 10542 u8 unused_0[7]; 10543 u8 valid; 10544 }; 10545 10546 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 10547 struct hwrm_nvm_get_dir_entries_input { 10548 __le16 req_type; 10549 __le16 cmpl_ring; 10550 __le16 seq_id; 10551 __le16 target_id; 10552 __le64 resp_addr; 10553 __le64 host_dest_addr; 10554 }; 10555 10556 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 10557 struct hwrm_nvm_get_dir_entries_output { 10558 __le16 error_code; 10559 __le16 req_type; 10560 __le16 seq_id; 10561 __le16 resp_len; 10562 u8 unused_0[7]; 10563 u8 valid; 10564 }; 10565 10566 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 10567 struct hwrm_nvm_get_dir_info_input { 10568 __le16 req_type; 10569 __le16 cmpl_ring; 10570 __le16 seq_id; 10571 __le16 target_id; 10572 __le64 resp_addr; 10573 }; 10574 10575 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 10576 struct hwrm_nvm_get_dir_info_output { 10577 __le16 error_code; 10578 __le16 req_type; 10579 __le16 seq_id; 10580 __le16 resp_len; 10581 __le32 entries; 10582 __le32 entry_length; 10583 u8 unused_0[7]; 10584 u8 valid; 10585 }; 10586 10587 /* hwrm_nvm_write_input (size:448b/56B) */ 10588 struct hwrm_nvm_write_input { 10589 __le16 req_type; 10590 __le16 cmpl_ring; 10591 __le16 seq_id; 10592 __le16 target_id; 10593 __le64 resp_addr; 10594 __le64 host_src_addr; 10595 __le16 dir_type; 10596 __le16 dir_ordinal; 10597 __le16 dir_ext; 10598 __le16 dir_attr; 10599 __le32 dir_data_length; 10600 __le16 option; 10601 __le16 flags; 10602 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 10603 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 10604 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 10605 #define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL 10606 __le32 dir_item_length; 10607 __le32 offset; 10608 __le32 len; 10609 __le32 unused_0; 10610 }; 10611 10612 /* hwrm_nvm_write_output (size:128b/16B) */ 10613 struct hwrm_nvm_write_output { 10614 __le16 error_code; 10615 __le16 req_type; 10616 __le16 seq_id; 10617 __le16 resp_len; 10618 __le32 dir_item_length; 10619 __le16 dir_idx; 10620 u8 unused_0; 10621 u8 valid; 10622 }; 10623 10624 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 10625 struct hwrm_nvm_write_cmd_err { 10626 u8 code; 10627 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10628 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10629 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10630 #define NVM_WRITE_CMD_ERR_CODE_WRITE_FAILED 0x3UL 10631 #define NVM_WRITE_CMD_ERR_CODE_REQD_ERASE_FAILED 0x4UL 10632 #define NVM_WRITE_CMD_ERR_CODE_VERIFY_FAILED 0x5UL 10633 #define NVM_WRITE_CMD_ERR_CODE_INVALID_HEADER 0x6UL 10634 #define NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 0x7UL 10635 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 10636 u8 unused_0[7]; 10637 }; 10638 10639 /* hwrm_nvm_modify_input (size:320b/40B) */ 10640 struct hwrm_nvm_modify_input { 10641 __le16 req_type; 10642 __le16 cmpl_ring; 10643 __le16 seq_id; 10644 __le16 target_id; 10645 __le64 resp_addr; 10646 __le64 host_src_addr; 10647 __le16 dir_idx; 10648 __le16 flags; 10649 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 10650 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 10651 __le32 offset; 10652 __le32 len; 10653 u8 unused_1[4]; 10654 }; 10655 10656 /* hwrm_nvm_modify_output (size:128b/16B) */ 10657 struct hwrm_nvm_modify_output { 10658 __le16 error_code; 10659 __le16 req_type; 10660 __le16 seq_id; 10661 __le16 resp_len; 10662 u8 unused_0[7]; 10663 u8 valid; 10664 }; 10665 10666 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 10667 struct hwrm_nvm_find_dir_entry_input { 10668 __le16 req_type; 10669 __le16 cmpl_ring; 10670 __le16 seq_id; 10671 __le16 target_id; 10672 __le64 resp_addr; 10673 __le32 enables; 10674 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 10675 __le16 dir_idx; 10676 __le16 dir_type; 10677 __le16 dir_ordinal; 10678 __le16 dir_ext; 10679 u8 opt_ordinal; 10680 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 10681 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 10682 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 10683 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 10684 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 10685 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 10686 u8 unused_0[3]; 10687 }; 10688 10689 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 10690 struct hwrm_nvm_find_dir_entry_output { 10691 __le16 error_code; 10692 __le16 req_type; 10693 __le16 seq_id; 10694 __le16 resp_len; 10695 __le32 dir_item_length; 10696 __le32 dir_data_length; 10697 __le32 fw_ver; 10698 __le16 dir_ordinal; 10699 __le16 dir_idx; 10700 u8 unused_0[7]; 10701 u8 valid; 10702 }; 10703 10704 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 10705 struct hwrm_nvm_erase_dir_entry_input { 10706 __le16 req_type; 10707 __le16 cmpl_ring; 10708 __le16 seq_id; 10709 __le16 target_id; 10710 __le64 resp_addr; 10711 __le16 dir_idx; 10712 u8 unused_0[6]; 10713 }; 10714 10715 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 10716 struct hwrm_nvm_erase_dir_entry_output { 10717 __le16 error_code; 10718 __le16 req_type; 10719 __le16 seq_id; 10720 __le16 resp_len; 10721 u8 unused_0[7]; 10722 u8 valid; 10723 }; 10724 10725 /* hwrm_nvm_get_dev_info_input (size:192b/24B) */ 10726 struct hwrm_nvm_get_dev_info_input { 10727 __le16 req_type; 10728 __le16 cmpl_ring; 10729 __le16 seq_id; 10730 __le16 target_id; 10731 __le64 resp_addr; 10732 u8 flags; 10733 #define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL 10734 u8 unused_0[7]; 10735 }; 10736 10737 /* hwrm_nvm_get_dev_info_output (size:768b/96B) */ 10738 struct hwrm_nvm_get_dev_info_output { 10739 __le16 error_code; 10740 __le16 req_type; 10741 __le16 seq_id; 10742 __le16 resp_len; 10743 __le16 manufacturer_id; 10744 __le16 device_id; 10745 __le32 sector_size; 10746 __le32 nvram_size; 10747 __le32 reserved_size; 10748 __le32 available_size; 10749 u8 nvm_cfg_ver_maj; 10750 u8 nvm_cfg_ver_min; 10751 u8 nvm_cfg_ver_upd; 10752 u8 flags; 10753 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 10754 char pkg_name[16]; 10755 __le16 hwrm_fw_major; 10756 __le16 hwrm_fw_minor; 10757 __le16 hwrm_fw_build; 10758 __le16 hwrm_fw_patch; 10759 __le16 mgmt_fw_major; 10760 __le16 mgmt_fw_minor; 10761 __le16 mgmt_fw_build; 10762 __le16 mgmt_fw_patch; 10763 __le16 roce_fw_major; 10764 __le16 roce_fw_minor; 10765 __le16 roce_fw_build; 10766 __le16 roce_fw_patch; 10767 __le16 netctrl_fw_major; 10768 __le16 netctrl_fw_minor; 10769 __le16 netctrl_fw_build; 10770 __le16 netctrl_fw_patch; 10771 __le16 srt2_fw_major; 10772 __le16 srt2_fw_minor; 10773 __le16 srt2_fw_build; 10774 __le16 srt2_fw_patch; 10775 u8 security_soc_fw_major; 10776 u8 security_soc_fw_minor; 10777 u8 security_soc_fw_build; 10778 u8 security_soc_fw_patch; 10779 u8 unused_0[3]; 10780 u8 valid; 10781 }; 10782 10783 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10784 struct hwrm_nvm_mod_dir_entry_input { 10785 __le16 req_type; 10786 __le16 cmpl_ring; 10787 __le16 seq_id; 10788 __le16 target_id; 10789 __le64 resp_addr; 10790 __le32 enables; 10791 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10792 __le16 dir_idx; 10793 __le16 dir_ordinal; 10794 __le16 dir_ext; 10795 __le16 dir_attr; 10796 __le32 checksum; 10797 }; 10798 10799 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10800 struct hwrm_nvm_mod_dir_entry_output { 10801 __le16 error_code; 10802 __le16 req_type; 10803 __le16 seq_id; 10804 __le16 resp_len; 10805 u8 unused_0[7]; 10806 u8 valid; 10807 }; 10808 10809 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10810 struct hwrm_nvm_verify_update_input { 10811 __le16 req_type; 10812 __le16 cmpl_ring; 10813 __le16 seq_id; 10814 __le16 target_id; 10815 __le64 resp_addr; 10816 __le16 dir_type; 10817 __le16 dir_ordinal; 10818 __le16 dir_ext; 10819 u8 unused_0[2]; 10820 }; 10821 10822 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10823 struct hwrm_nvm_verify_update_output { 10824 __le16 error_code; 10825 __le16 req_type; 10826 __le16 seq_id; 10827 __le16 resp_len; 10828 u8 unused_0[7]; 10829 u8 valid; 10830 }; 10831 10832 /* hwrm_nvm_install_update_input (size:192b/24B) */ 10833 struct hwrm_nvm_install_update_input { 10834 __le16 req_type; 10835 __le16 cmpl_ring; 10836 __le16 seq_id; 10837 __le16 target_id; 10838 __le64 resp_addr; 10839 __le32 install_type; 10840 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10841 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10842 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10843 __le16 flags; 10844 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10845 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10846 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10847 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10848 u8 unused_0[2]; 10849 }; 10850 10851 /* hwrm_nvm_install_update_output (size:192b/24B) */ 10852 struct hwrm_nvm_install_update_output { 10853 __le16 error_code; 10854 __le16 req_type; 10855 __le16 seq_id; 10856 __le16 resp_len; 10857 __le64 installed_items; 10858 u8 result; 10859 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10860 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10861 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10862 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10863 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10864 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10865 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10866 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10867 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10868 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10869 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10870 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10871 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10872 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10873 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10874 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10875 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10876 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10877 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10878 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10879 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10880 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10881 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10882 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10883 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10884 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10885 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10886 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10887 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10888 u8 problem_item; 10889 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10890 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10891 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10892 u8 reset_required; 10893 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10894 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10895 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10896 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10897 u8 unused_0[4]; 10898 u8 valid; 10899 }; 10900 10901 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10902 struct hwrm_nvm_install_update_cmd_err { 10903 u8 code; 10904 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10905 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10906 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10907 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10908 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10909 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_DEFRAG_FAILED 0x5UL 10910 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x6UL 10911 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 10912 u8 unused_0[7]; 10913 }; 10914 10915 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10916 struct hwrm_nvm_get_variable_input { 10917 __le16 req_type; 10918 __le16 cmpl_ring; 10919 __le16 seq_id; 10920 __le16 target_id; 10921 __le64 resp_addr; 10922 __le64 dest_data_addr; 10923 __le16 data_len; 10924 __le16 option_num; 10925 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10926 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10927 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10928 __le16 dimensions; 10929 __le16 index_0; 10930 __le16 index_1; 10931 __le16 index_2; 10932 __le16 index_3; 10933 u8 flags; 10934 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10935 #define NVM_GET_VARIABLE_REQ_FLAGS_VALIDATE_OPT_VALUE 0x2UL 10936 u8 unused_0; 10937 }; 10938 10939 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10940 struct hwrm_nvm_get_variable_output { 10941 __le16 error_code; 10942 __le16 req_type; 10943 __le16 seq_id; 10944 __le16 resp_len; 10945 __le16 data_len; 10946 __le16 option_num; 10947 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10948 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10949 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10950 u8 flags; 10951 #define NVM_GET_VARIABLE_RESP_FLAGS_VALIDATE_OPT_VALUE 0x1UL 10952 u8 unused_0[2]; 10953 u8 valid; 10954 }; 10955 10956 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10957 struct hwrm_nvm_get_variable_cmd_err { 10958 u8 code; 10959 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10960 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10961 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10962 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10963 #define NVM_GET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x4UL 10964 #define NVM_GET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x5UL 10965 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x6UL 10966 #define NVM_GET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x7UL 10967 #define NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x8UL 10968 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 10969 u8 unused_0[7]; 10970 }; 10971 10972 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10973 struct hwrm_nvm_set_variable_input { 10974 __le16 req_type; 10975 __le16 cmpl_ring; 10976 __le16 seq_id; 10977 __le16 target_id; 10978 __le64 resp_addr; 10979 __le64 src_data_addr; 10980 __le16 data_len; 10981 __le16 option_num; 10982 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10983 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10984 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10985 __le16 dimensions; 10986 __le16 index_0; 10987 __le16 index_1; 10988 __le16 index_2; 10989 __le16 index_3; 10990 u8 flags; 10991 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10992 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10993 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10994 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10995 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10996 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10997 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10998 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10999 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 11000 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 11001 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 11002 u8 unused_0; 11003 }; 11004 11005 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 11006 struct hwrm_nvm_set_variable_output { 11007 __le16 error_code; 11008 __le16 req_type; 11009 __le16 seq_id; 11010 __le16 resp_len; 11011 u8 unused_0[7]; 11012 u8 valid; 11013 }; 11014 11015 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 11016 struct hwrm_nvm_set_variable_cmd_err { 11017 u8 code; 11018 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 11019 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 11020 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 11021 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 11022 #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACTION_NOT_SUPPORTED 0x4UL 11023 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x5UL 11024 #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x6UL 11025 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x7UL 11026 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL 11027 #define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL 11028 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 11029 u8 unused_0[7]; 11030 }; 11031 11032 /* hwrm_nvm_defrag_input (size:192b/24B) */ 11033 struct hwrm_nvm_defrag_input { 11034 __le16 req_type; 11035 __le16 cmpl_ring; 11036 __le16 seq_id; 11037 __le16 target_id; 11038 __le64 resp_addr; 11039 __le32 flags; 11040 #define NVM_DEFRAG_REQ_FLAGS_DEFRAG 0x1UL 11041 u8 unused_0[4]; 11042 }; 11043 11044 /* hwrm_nvm_defrag_output (size:128b/16B) */ 11045 struct hwrm_nvm_defrag_output { 11046 __le16 error_code; 11047 __le16 req_type; 11048 __le16 seq_id; 11049 __le16 resp_len; 11050 u8 unused_0[7]; 11051 u8 valid; 11052 }; 11053 11054 /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ 11055 struct hwrm_nvm_defrag_cmd_err { 11056 u8 code; 11057 #define NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN 0x0UL 11058 #define NVM_DEFRAG_CMD_ERR_CODE_FAIL 0x1UL 11059 #define NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 0x2UL 11060 #define NVM_DEFRAG_CMD_ERR_CODE_LAST NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 11061 u8 unused_0[7]; 11062 }; 11063 11064 /* hwrm_selftest_qlist_input (size:128b/16B) */ 11065 struct hwrm_selftest_qlist_input { 11066 __le16 req_type; 11067 __le16 cmpl_ring; 11068 __le16 seq_id; 11069 __le16 target_id; 11070 __le64 resp_addr; 11071 }; 11072 11073 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 11074 struct hwrm_selftest_qlist_output { 11075 __le16 error_code; 11076 __le16 req_type; 11077 __le16 seq_id; 11078 __le16 resp_len; 11079 u8 num_tests; 11080 u8 available_tests; 11081 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 11082 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 11083 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 11084 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 11085 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 11086 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 11087 u8 offline_tests; 11088 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 11089 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 11090 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 11091 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 11092 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 11093 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 11094 u8 unused_0; 11095 __le16 test_timeout; 11096 u8 unused_1[2]; 11097 char test_name[8][32]; 11098 u8 eyescope_target_BER_support; 11099 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 11100 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 11101 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 11102 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 11103 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 11104 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 11105 u8 unused_2[6]; 11106 u8 valid; 11107 }; 11108 11109 /* hwrm_selftest_exec_input (size:192b/24B) */ 11110 struct hwrm_selftest_exec_input { 11111 __le16 req_type; 11112 __le16 cmpl_ring; 11113 __le16 seq_id; 11114 __le16 target_id; 11115 __le64 resp_addr; 11116 u8 flags; 11117 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 11118 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 11119 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 11120 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 11121 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 11122 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 11123 u8 unused_0[7]; 11124 }; 11125 11126 /* hwrm_selftest_exec_output (size:128b/16B) */ 11127 struct hwrm_selftest_exec_output { 11128 __le16 error_code; 11129 __le16 req_type; 11130 __le16 seq_id; 11131 __le16 resp_len; 11132 u8 requested_tests; 11133 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 11134 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 11135 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 11136 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 11137 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 11138 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 11139 u8 test_success; 11140 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 11141 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 11142 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 11143 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 11144 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 11145 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 11146 u8 unused_0[5]; 11147 u8 valid; 11148 }; 11149 11150 /* hwrm_selftest_irq_input (size:128b/16B) */ 11151 struct hwrm_selftest_irq_input { 11152 __le16 req_type; 11153 __le16 cmpl_ring; 11154 __le16 seq_id; 11155 __le16 target_id; 11156 __le64 resp_addr; 11157 }; 11158 11159 /* hwrm_selftest_irq_output (size:128b/16B) */ 11160 struct hwrm_selftest_irq_output { 11161 __le16 error_code; 11162 __le16 req_type; 11163 __le16 seq_id; 11164 __le16 resp_len; 11165 u8 unused_0[7]; 11166 u8 valid; 11167 }; 11168 11169 /* dbc_dbc (size:64b/8B) */ 11170 struct dbc_dbc { 11171 __le32 index; 11172 #define DBC_DBC_INDEX_MASK 0xffffffUL 11173 #define DBC_DBC_INDEX_SFT 0 11174 #define DBC_DBC_EPOCH 0x1000000UL 11175 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 11176 #define DBC_DBC_TOGGLE_SFT 25 11177 __le32 type_path_xid; 11178 #define DBC_DBC_XID_MASK 0xfffffUL 11179 #define DBC_DBC_XID_SFT 0 11180 #define DBC_DBC_PATH_MASK 0x3000000UL 11181 #define DBC_DBC_PATH_SFT 24 11182 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 11183 #define DBC_DBC_PATH_L2 (0x1UL << 24) 11184 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 11185 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 11186 #define DBC_DBC_VALID 0x4000000UL 11187 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 11188 #define DBC_DBC_TYPE_MASK 0xf0000000UL 11189 #define DBC_DBC_TYPE_SFT 28 11190 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 11191 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 11192 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 11193 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 11194 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 11195 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 11196 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 11197 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 11198 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 11199 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 11200 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 11201 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 11202 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 11203 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 11204 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 11205 }; 11206 11207 /* db_push_start (size:64b/8B) */ 11208 struct db_push_start { 11209 u64 db; 11210 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 11211 #define DB_PUSH_START_DB_INDEX_SFT 0 11212 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 11213 #define DB_PUSH_START_DB_PI_LO_SFT 24 11214 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 11215 #define DB_PUSH_START_DB_XID_SFT 32 11216 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 11217 #define DB_PUSH_START_DB_PI_HI_SFT 52 11218 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 11219 #define DB_PUSH_START_DB_TYPE_SFT 60 11220 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 11221 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 11222 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 11223 }; 11224 11225 /* db_push_end (size:64b/8B) */ 11226 struct db_push_end { 11227 u64 db; 11228 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 11229 #define DB_PUSH_END_DB_INDEX_SFT 0 11230 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 11231 #define DB_PUSH_END_DB_PI_LO_SFT 24 11232 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 11233 #define DB_PUSH_END_DB_XID_SFT 32 11234 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 11235 #define DB_PUSH_END_DB_PI_HI_SFT 52 11236 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 11237 #define DB_PUSH_END_DB_PATH_SFT 56 11238 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 11239 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 11240 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 11241 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 11242 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 11243 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 11244 #define DB_PUSH_END_DB_TYPE_SFT 60 11245 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 11246 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 11247 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 11248 }; 11249 11250 /* db_push_info (size:64b/8B) */ 11251 struct db_push_info { 11252 u32 push_size_push_index; 11253 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 11254 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 11255 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 11256 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 11257 u32 reserved32; 11258 }; 11259 11260 /* fw_status_reg (size:32b/4B) */ 11261 struct fw_status_reg { 11262 u32 fw_status; 11263 #define FW_STATUS_REG_CODE_MASK 0xffffUL 11264 #define FW_STATUS_REG_CODE_SFT 0 11265 #define FW_STATUS_REG_CODE_READY 0x8000UL 11266 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 11267 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 11268 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 11269 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 11270 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 11271 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 11272 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 11273 #define FW_STATUS_REG_RECOVERING 0x400000UL 11274 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 11275 }; 11276 11277 /* hcomm_status (size:64b/8B) */ 11278 struct hcomm_status { 11279 u32 sig_ver; 11280 #define HCOMM_STATUS_VER_MASK 0xffUL 11281 #define HCOMM_STATUS_VER_SFT 0 11282 #define HCOMM_STATUS_VER_LATEST 0x1UL 11283 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 11284 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 11285 #define HCOMM_STATUS_SIGNATURE_SFT 8 11286 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 11287 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 11288 u32 fw_status_loc; 11289 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 11290 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 11291 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 11292 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 11293 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 11294 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 11295 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 11296 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 11297 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 11298 }; 11299 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 11300 11301 #endif /* _BNXT_HSI_H_ */ 11302