Searched refs:fclks (Results 1 – 3 of 3) sorted by relevance
1317 struct dm_pp_clock_levels_with_voltage *fclks) in dcn_bw_update_from_pplib_fclks() argument1321 ASSERT(fclks->num_levels); in dcn_bw_update_from_pplib_fclks()1324 vmid0p72_idx = fclks->num_levels > 2 ? fclks->num_levels - 3 : 0; in dcn_bw_update_from_pplib_fclks()1325 vnom0p8_idx = fclks->num_levels > 1 ? fclks->num_levels - 2 : 0; in dcn_bw_update_from_pplib_fclks()1326 vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; in dcn_bw_update_from_pplib_fclks()1329 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; in dcn_bw_update_from_pplib_fclks()1332 (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()1336 (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()1340 (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()
1355 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; in dcn10_resource_construct() local1544 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); in dcn10_resource_construct()1549 res = verify_clock_values(&fclks); in dcn10_resource_construct()1552 dcn_bw_update_from_pplib_fclks(dc, &fclks); in dcn10_resource_construct()
635 struct dm_pp_clock_levels_with_voltage *fclks);