| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 326 if (max_clk_limit->fclk_mhz != 0) in override_max_clk_values()
327 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz; in override_max_clk_values()
367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) in build_synthetic_soc_states()
368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
385 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
387 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
407 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) in build_synthetic_soc_states()
408 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; in build_synthetic_soc_states()
416 if (max_clk_data.fclk_mhz == 0) in build_synthetic_soc_states()
417 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz * in build_synthetic_soc_states()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/ |
| H A D | dcn401_soc_and_ip_translator.c | 71 if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
72 dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
73 if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
74 dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
81 dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 326 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz) || in dcn401_is_dc_mode_present()
449 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000; in dcn401_auto_dpm_test_log()
689 params->update_idle_hardmin_params.fclk_mhz); in dcn401_execute_block_sequence()
695 params->update_idle_hardmin_params.fclk_mhz); in dcn401_execute_block_sequence()
701 params->update_idle_hardmin_params.fclk_mhz); in dcn401_execute_block_sequence()
836 …table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence()
985 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence()
993 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence()
1001 block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz; in dcn401_build_update_bandwidth_clocks_sequence()
1400 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, in dcn401_get_memclk_states_from_smu()
[all …]
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| H A D | dcn401_clk_mgr.h | 32 uint16_t fclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 498 .fclk_mhz = 400,
505 .fclk_mhz = 800,
512 .fclk_mhz = 1067,
519 .fclk_mhz = 1333,
600 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
609 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 582 .fclk_mhz = 400,
589 .fclk_mhz = 800,
596 .fclk_mhz = 1067,
603 .fclk_mhz = 1333,
667 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 2679 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) in dcn32_patch_dpm_table()
2680 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in dcn32_patch_dpm_table()
2784 if (max_clk_limit->fclk_mhz != 0) in override_max_clk_values()
2785 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz; in override_max_clk_values()
2825 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) in build_synthetic_soc_states()
2826 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
2843 if (bw_params->clk_table.entries[i].fclk_mhz > 0) { in build_synthetic_soc_states()
2845 if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz) in build_synthetic_soc_states()
2865 if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz) in build_synthetic_soc_states()
2866 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz; in build_synthetic_soc_states()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 1102 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]); in dcn35_clk_mgr_helper_populate_bw_params()
1110 bw_params->clk_table.entries[i].fclk_mhz = max_fclk; in dcn35_clk_mgr_helper_populate_bw_params()
1132 bw_params->clk_table.entries[i].fclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1150 if (!bw_params->clk_table.entries[i].fclk_mhz) { in dcn35_clk_mgr_helper_populate_bw_params()
1151 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
1163 if (!bw_params->clk_table.entries[i].fclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1164 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 630 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn31_update_bw_bounding_box()
698 dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn315_update_bw_bounding_box()
770 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn316_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 282 clk_table->entries[i].fclk_mhz; in dcn35_update_bw_bounding_box_fpu()
360 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn35_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 316 clk_table->entries[i].fclk_mhz; in dcn351_update_bw_bounding_box_fpu()
394 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz = in dcn351_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 118 unsigned int fclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 547 … fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000; in dcn32_auto_dpm_test_log()
1046 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, in dcn32_get_memclk_states_from_smu()
1048 …clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCL… in dcn32_get_memclk_states_from_smu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 237 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn314_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 361 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_fpu_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 525 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn316_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 596 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 2381 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz; in construct_low_pstate_lvl()
2434 s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn21_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_translation_helper.c | 535 dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz; in dml2_init_soc_states()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 2666 double fclk_mhz, in dml_get_return_bandwidth_available() argument
2671 double ideal_fabric_bandwidth = fclk_mhz * (double)soc->fabric_datapath_to_dcn_data_return_bytes; in dml_get_return_bandwidth_available()
2736 DML_LOG_VERBOSE("DML::%s: fclk_mhz = %f\n", __func__, fclk_mhz); in dml_get_return_bandwidth_available()
2758 double fclk_mhz, in calculate_bandwidth_available() argument
2764 DML_LOG_VERBOSE("DML::%s: fclk_mhz = %f\n", __func__, fclk_mhz); in calculate_bandwidth_available()
2777 fclk_mhz, in calculate_bandwidth_available()
2780 …_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_bw_mbps); in calculate_bandwidth_available()
2790 …_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 1, dcfclk_mhz, fclk_mhz, dram_bw_mbps); in calculate_bandwidth_available()
2791 …_get_return_bandwidth_available(soc, m, n, 0, HostVMEnable, 0, dcfclk_mhz, fclk_mhz, dram_bw_mbps); in calculate_bandwidth_available()
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