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Searched refs:enable_reg (Results 1 – 25 of 371) sorted by relevance

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/linux/drivers/clk/qcom/
H A Dgcc-msm8660.c45 .enable_reg = 0x34c0,
124 .enable_reg = 0x29d4,
140 .enable_reg = 0x29d4,
175 .enable_reg = 0x29f4,
191 .enable_reg = 0x29f4,
226 .enable_reg = 0x2a14,
242 .enable_reg = 0x2a14,
277 .enable_reg = 0x2a34,
293 .enable_reg = 0x2a34,
328 .enable_reg = 0x2a54,
[all …]
H A Dgcc-sm8250.c39 .enable_reg = 0x52018,
78 .enable_reg = 0x52018,
95 .enable_reg = 0x52018,
1062 .enable_reg = 0x9000c,
1077 .enable_reg = 0x750cc,
1097 .enable_reg = 0x770cc,
1115 .enable_reg = 0xf080,
1133 .enable_reg = 0x10080,
1153 .enable_reg = 0x52000,
1166 .enable_reg = 0xb02c,
[all …]
H A Dgcc-ipq806x.c49 .enable_reg = 0x34c0,
78 .enable_reg = 0x34c0,
107 .enable_reg = 0x34c0,
214 .enable_reg = 0x34c0,
432 .enable_reg = 0x29d4,
448 .enable_reg = 0x29d4,
483 .enable_reg = 0x29f4,
499 .enable_reg = 0x29f4,
534 .enable_reg = 0x2a34,
550 .enable_reg = 0x2a34,
[all …]
H A Dgcc-mdm9615.c64 .enable_reg = 0x34c0,
77 .enable_reg = 0x34c0,
106 .enable_reg = 0x34c0,
135 .enable_reg = 0x34c0,
206 .enable_reg = 0x29d4,
222 .enable_reg = 0x29d4,
257 .enable_reg = 0x29f4,
273 .enable_reg = 0x29f4,
308 .enable_reg = 0x2a14,
324 .enable_reg = 0x2a14,
[all …]
H A Dgcc-sm8150.c39 .enable_reg = 0x52000,
82 .enable_reg = 0x52000,
100 .enable_reg = 0x52000,
1113 .enable_reg = 0x90018,
1128 .enable_reg = 0x750c0,
1147 .enable_reg = 0x750c0,
1166 .enable_reg = 0x770c0,
1185 .enable_reg = 0x770c0,
1202 .enable_reg = 0xf07c,
1219 .enable_reg = 0x1007c,
[all …]
H A Dgcc-sc8180x.c52 .enable_reg = 0x52000,
94 .enable_reg = 0x52000,
113 .enable_reg = 0x52000,
132 .enable_reg = 0x52000,
149 .enable_reg = 0x52000,
1399 .enable_reg = 0x90018,
1414 .enable_reg = 0x750c0,
1434 .enable_reg = 0x750c0,
1454 .enable_reg = 0x770c0,
1474 .enable_reg = 0x770c0,
[all …]
H A Dgcc-sc7180.c39 .enable_reg = 0x52010,
92 .enable_reg = 0x52010,
110 .enable_reg = 0x52010,
128 .enable_reg = 0x52010,
146 .enable_reg = 0x52010,
832 .enable_reg = 0x82024,
850 .enable_reg = 0x8201c,
870 .enable_reg = 0x52000,
883 .enable_reg = 0xb020,
898 .enable_reg = 0xb080,
[all …]
H A Dgcc-msm8960.c47 .enable_reg = 0x34c0,
78 .enable_reg = 0x34c0,
277 .enable_reg = 0x34c0,
369 .enable_reg = 0x29d4,
385 .enable_reg = 0x29d4,
420 .enable_reg = 0x29f4,
436 .enable_reg = 0x29f4,
471 .enable_reg = 0x2a14,
487 .enable_reg = 0x2a14,
522 .enable_reg = 0x2a34,
[all …]
H A Dgcc-sc8280xp.c116 .enable_reg = 0x52028,
153 .enable_reg = 0x52028,
168 .enable_reg = 0x52028,
183 .enable_reg = 0x52028,
198 .enable_reg = 0x52028,
213 .enable_reg = 0x52028,
2528 .enable_reg = 0x52018,
2543 .enable_reg = 0x52018,
2558 .enable_reg = 0x52000,
2573 .enable_reg = 0x52018,
[all …]
H A Dmmcc-msm8960.c208 .enable_reg = 0x0140,
223 .enable_reg = 0x0140,
259 .enable_reg = 0x0154,
274 .enable_reg = 0x0154,
310 .enable_reg = 0x0220,
325 .enable_reg = 0x0220,
367 .enable_reg = 0x0040,
382 .enable_reg = 0x0040,
400 .enable_reg = 0x0040,
435 .enable_reg = 0x0024,
[all …]
H A Dgcc-sm6350.c38 .enable_reg = 0x52010,
99 .enable_reg = 0x52010,
138 .enable_reg = 0x52010,
804 .enable_reg = 0x3e014,
824 .enable_reg = 0x3e014,
844 .enable_reg = 0x3e014,
864 .enable_reg = 0x3e010,
884 .enable_reg = 0x52000,
899 .enable_reg = 0x17008,
915 .enable_reg = 0x17018,
[all …]
H A Decpricc-qdu1000.c66 .enable_reg = 0x0,
96 .enable_reg = 0x0,
744 .enable_reg = 0x900c,
762 .enable_reg = 0x902c,
780 .enable_reg = 0xf004,
798 .enable_reg = 0x9014,
816 .enable_reg = 0x901c,
834 .enable_reg = 0xf008,
852 .enable_reg = 0x9004,
870 .enable_reg = 0x9024,
[all …]
H A Dgcc-msm8996.c52 .enable_reg = 0x52000,
94 .enable_reg = 0x5200c,
111 .enable_reg = 0x5200c,
129 .enable_reg = 0x52000,
1180 .enable_reg = 0x0f03c,
1197 .enable_reg = 0x75038,
1214 .enable_reg = 0x6010,
1231 .enable_reg = 0x9008,
1244 .enable_reg = 0x9010,
1257 .enable_reg = 0x0f008,
[all …]
H A Dgcc-msm8998.c41 .enable_reg = 0x52000,
112 .enable_reg = 0x52000,
183 .enable_reg = 0x52000,
254 .enable_reg = 0x52000,
325 .enable_reg = 0x52000,
1221 .enable_reg = 0x8202c,
1234 .enable_reg = 0x82028,
1252 .enable_reg = 0x82024,
1270 .enable_reg = 0x48090,
1283 .enable_reg = 0x48094,
[all …]
H A Dgcc-sm6125.c45 .enable_reg = 0x79000,
88 .enable_reg = 0x79000,
105 .enable_reg = 0x79000,
122 .enable_reg = 0x79000,
139 .enable_reg = 0x79000,
169 .enable_reg = 0x79000,
199 .enable_reg = 0x79000,
229 .enable_reg = 0x79000,
1362 .enable_reg = 0x1d004,
1377 .enable_reg = 0x1d008,
[all …]
H A Dgcc-sm7150.c45 .enable_reg = 0x52000,
100 .enable_reg = 0x52000,
117 .enable_reg = 0x52000,
972 .enable_reg = 0x2800c,
987 .enable_reg = 0x82024,
1007 .enable_reg = 0x82024,
1025 .enable_reg = 0x8201c,
1043 .enable_reg = 0x7a050,
1063 .enable_reg = 0x52004,
1076 .enable_reg = 0xb020,
[all …]
H A Dgcc-qcs615.c48 .enable_reg = 0x52000,
79 .enable_reg = 0x52000,
110 .enable_reg = 0x52000,
127 .enable_reg = 0x52000,
166 .enable_reg = 0x52000,
183 .enable_reg = 0x52000,
1055 .enable_reg = 0x770c0,
1073 .enable_reg = 0xa6084,
1091 .enable_reg = 0xf07c,
1111 .enable_reg = 0x6a008,
[all …]
H A Dgcc-msm8976.c74 .enable_reg = 0x45000,
107 .enable_reg = 0x45000,
144 .enable_reg = 0x45000,
191 .enable_reg = 0x45000,
222 .enable_reg = 0x45000,
1657 .enable_reg = 0x78004,
1674 .enable_reg = 0x79004,
1692 .enable_reg = 0x2008,
1710 .enable_reg = 0x2004,
1728 .enable_reg = 0x3010,
[all …]
H A Dgcc-qcs8300.c63 .enable_reg = 0x4b028,
102 .enable_reg = 0x4b028,
119 .enable_reg = 0x4b028,
136 .enable_reg = 0x4b028,
153 .enable_reg = 0x4b028,
1348 .enable_reg = 0x4b000,
1363 .enable_reg = 0x830d4,
1383 .enable_reg = 0x1c05c,
1403 .enable_reg = 0x1b084,
1423 .enable_reg = 0x76004,
[all …]
H A Dgcc-sa8775p.c77 .enable_reg = 0x4b028,
114 .enable_reg = 0x4b028,
129 .enable_reg = 0x4b028,
144 .enable_reg = 0x4b028,
159 .enable_reg = 0x4b028,
174 .enable_reg = 0x4b028,
1689 .enable_reg = 0x4b000,
1704 .enable_reg = 0x810d4,
1724 .enable_reg = 0x830d4,
1744 .enable_reg = 0x1c05c,
[all …]
H A Dgcc-sc7280.c48 .enable_reg = 0x52010,
109 .enable_reg = 0x52010,
126 .enable_reg = 0x52010,
143 .enable_reg = 0x52010,
160 .enable_reg = 0x52010,
176 .enable_reg = 0x52000,
1234 .enable_reg = 0x8c004,
1247 .enable_reg = 0x8c008,
1262 .enable_reg = 0x52000,
1277 .enable_reg = 0x52000,
[all …]
H A Dgcc-sdm845.c41 .enable_reg = 0x52000,
58 .enable_reg = 0x52000,
75 .enable_reg = 0x52000,
1130 .enable_reg = 0x90014,
1145 .enable_reg = 0x82028,
1165 .enable_reg = 0x82024,
1183 .enable_reg = 0x8201c,
1201 .enable_reg = 0x82020,
1219 .enable_reg = 0x7a050,
1239 .enable_reg = 0x52004,
[all …]
H A Dgcc-sm8350.c47 .enable_reg = 0x52018,
86 .enable_reg = 0x52018,
104 .enable_reg = 0x52018,
1243 .enable_reg = 0x52000,
1257 .enable_reg = 0x52000,
1272 .enable_reg = 0x52000,
1287 .enable_reg = 0x750cc,
1307 .enable_reg = 0x750cc,
1327 .enable_reg = 0x770cc,
1347 .enable_reg = 0x770cc,
[all …]
/linux/arch/arm/mach-omap1/
H A Dclock.c49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
194 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_is_enabled()
196 regval32 = __raw_readw(clk->enable_reg); in omap1_clk_is_enabled()
395 val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); in omap1_set_uart_rate()
396 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
422 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
423 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
489 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
490 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
534 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
[all …]
/linux/drivers/regulator/
H A D88pm886-regulator.c66 .enable_reg = PM886_REG_LDO_EN1,
79 .enable_reg = PM886_REG_LDO_EN1,
92 .enable_reg = PM886_REG_LDO_EN1,
105 .enable_reg = PM886_REG_LDO_EN1,
118 .enable_reg = PM886_REG_LDO_EN1,
131 .enable_reg = PM886_REG_LDO_EN1,
144 .enable_reg = PM886_REG_LDO_EN1,
157 .enable_reg = PM886_REG_LDO_EN1,
170 .enable_reg = PM886_REG_LDO_EN2,
183 .enable_reg = PM886_REG_LDO_EN2,
[all …]

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