Searched refs:dtbclk (Results 1 – 12 of 12) sorted by relevance
160 dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()162 if (i < dml_clk_table->dtbclk.num_clk_values) { in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()166 dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()167 dml_clk_table->dtbclk.num_clk_values = i + 1; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()169 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()170 dml_clk_table->dtbclk.num_clk_values = i; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()173 dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()176 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in dcn401_convert_dc_clock_table_to_soc_bb_clock_table()
182 …min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbcl… in build_min_clock_table()187 …min_table->max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table->max_clocks_khz.dtbclk / (1… in build_min_clock_table()
432 int dtbclk; in dcn35_smu_get_dtbclk() local437 dtbclk = dcn35_smu_send_msg_with_param(clk_mgr, in dcn35_smu_get_dtbclk()441 smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); in dcn35_smu_get_dtbclk()442 return dtbclk * 1000; in dcn35_smu_get_dtbclk()
633 regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; in dcn35_save_clk_registers()748 clk_mgr->clks.ref_dtbclk_khz = clk_mgr->boot_snapshot.dtbclk * 10; in dcn35_init_clocks()749 if (clk_mgr->boot_snapshot.dtbclk > 59000) { in dcn35_init_clocks()
129 struct dml2_clk_table dtbclk; member
105 .dtbclk = {
35 unsigned int dtbclk; member44 unsigned int dtbclk; member
190 uint32_t dtbclk; member
385 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers()512 clk_register_dump.dtbclk, in dcn401_auto_dpm_test_log()1477 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk; in dcn401_get_dtb_ref_freq_khz()1589 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn401_clk_mgr_construct()1590 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn401_clk_mgr_construct()
934 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()1196 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct()1197 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn32_clk_mgr_construct()
420 …dtbclk_khz, &display_cfg->stream_programming[i].min_clocks.dcn4x.dtbclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm()429 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dtbrefclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm()
8754 if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_ss_clocks_khz.dtbclk / 1000)) { in dml_core_mode_support()