| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-novatek-nt36523.c | 64 struct mipi_dsi_multi_context dsi_ctx = { .dsi = NULL }; in elish_boe_init_sequence() local
66 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
67 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
68 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x05); in elish_boe_init_sequence()
69 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x20); in elish_boe_init_sequence()
70 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
71 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0x18, 0x40); in elish_boe_init_sequence()
72 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
73 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
74 mipi_dsi_dual_dcs_write_seq_multi(&dsi_ctx, dsi0, dsi1, 0xb9, 0x02); in elish_boe_init_sequence()
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| H A D | panel-sony-tulip-truly-nt35521.c | 30 #define nt35521_switch_page(dsi_ctx, page) \ argument
31 mipi_dsi_dcs_write_seq_multi(dsi_ctx, NT35521_DCS_SWITCH_PAGE, \
53 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in truly_nt35521_on() local
57 nt35521_switch_page(&dsi_ctx, 0x00); in truly_nt35521_on()
58 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); in truly_nt35521_on()
59 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11, 0x00); in truly_nt35521_on()
60 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x20, 0x00); in truly_nt35521_on()
61 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in truly_nt35521_on()
62 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x21); in truly_nt35521_on()
63 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x01, 0xa0, 0x10, 0x08, 0x01); in truly_nt35521_on()
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| H A D | panel-newvision-nv3051d.c | 50 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in panel_nv3051d_init_sequence() local
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); in panel_nv3051d_init_sequence()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x01); in panel_nv3051d_init_sequence()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x00); in panel_nv3051d_init_sequence()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40); in panel_nv3051d_init_sequence()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x00); in panel_nv3051d_init_sequence()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x03); in panel_nv3051d_init_sequence()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x12); in panel_nv3051d_init_sequence()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x1E); in panel_nv3051d_init_sequence()
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| H A D | panel-visionox-rm692e5.c | 57 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_rm692e5_on() local
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); in visionox_rm692e5_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07); in visionox_rm692e5_on()
63 mipi_dsi_usleep_range(&dsi_ctx, 17000, 18000); in visionox_rm692e5_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2); in visionox_rm692e5_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11); in visionox_rm692e5_on()
66 mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ab); in visionox_rm692e5_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30); in visionox_rm692e5_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x09); in visionox_rm692e5_on()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60); in visionox_rm692e5_on()
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| H A D | panel-raydium-rm692e5.c | 43 static void rm692e5_on(struct mipi_dsi_multi_context *dsi_ctx) in rm692e5_on() argument
45 dsi_ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; in rm692e5_on()
47 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x41); in rm692e5_on()
48 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xd6, 0x00); in rm692e5_on()
49 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x16); in rm692e5_on()
50 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x8a, 0x87); in rm692e5_on()
51 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfe, 0x71); in rm692e5_on()
52 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x82, 0x01); in rm692e5_on()
53 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc6, 0x00); in rm692e5_on()
54 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc7, 0x2c); in rm692e5_on()
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| H A D | panel-himax-hx83112b.c | 71 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in hx83112b_on() local
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETEXTC, 0x83, 0x11, 0x2b); in hx83112b_on()
74 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x01); in hx83112b_on()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISMO, 0x08, 0x70); in hx83112b_on()
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x03); in hx83112b_on()
77 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, 0x04, 0x38, 0x08, 0x70); in hx83112b_on()
78 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETBANK, 0x00); in hx83112b_on()
79 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER1, in hx83112b_on()
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETPOWER2, 0x2d, 0x2d); in hx83112b_on()
83 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112B_SETDISP, in hx83112b_on()
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| H A D | panel-sitronix-st7703.c | 72 void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
80 static void jh057n_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in jh057n_init_sequence() argument
87 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, in jh057n_init_sequence()
89 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, in jh057n_init_sequence()
92 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, in jh057n_init_sequence()
95 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E); in jh057n_init_sequence()
96 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B); in jh057n_init_sequence()
97 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80); in jh057n_init_sequence()
98 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30); in jh057n_init_sequence()
99 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, in jh057n_init_sequence()
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| H A D | panel-leadtek-ltk050h3146w.c | 29 void (*init)(struct mipi_dsi_multi_context *dsi_ctx);
246 static void ltk050h3148w_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in ltk050h3148w_init_sequence() argument
252 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb9, 0xff, 0x83, 0x94); in ltk050h3148w_init_sequence()
253 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, 0x50, 0x15, 0x75, 0x09, 0x32, 0x44, in ltk050h3148w_init_sequence()
255 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xba, 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); in ltk050h3148w_init_sequence()
256 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd2, 0x88); in ltk050h3148w_init_sequence()
257 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb2, 0x00, 0x80, 0x64, 0x10, 0x07); in ltk050h3148w_init_sequence()
258 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb4, 0x05, 0x70, 0x05, 0x70, 0x01, 0x70, in ltk050h3148w_init_sequence()
261 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd3, 0x00, 0x00, 0x07, 0x07, 0x40, 0x1e, in ltk050h3148w_init_sequence()
266 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd5, 0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, in ltk050h3148w_init_sequence()
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| H A D | panel-samsung-s6e3fc2x01.c | 67 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in s6e3fc2x01_on() local
69 s6e3fc2x01_test_key_on_lvl1(&dsi_ctx); in s6e3fc2x01_on()
71 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in s6e3fc2x01_on()
73 mipi_dsi_usleep_range(&dsi_ctx, 10000, 11000); in s6e3fc2x01_on()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x0a); in s6e3fc2x01_on()
76 mipi_dsi_usleep_range(&dsi_ctx, 10000, 11000); in s6e3fc2x01_on()
78 s6e3fc2x01_test_key_off_lvl1(&dsi_ctx); in s6e3fc2x01_on()
80 s6e3fc2x01_test_key_on_lvl2(&dsi_ctx); in s6e3fc2x01_on()
81 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x01); in s6e3fc2x01_on()
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x01); in s6e3fc2x01_on()
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| H A D | panel-himax-hx8394.c | 83 void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
91 static void hsd060bhw4_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in hsd060bhw4_init_sequence() argument
94 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
98 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
102 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
106 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
110 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
116 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
123 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
131 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
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| H A D | panel-boe-th101mb31ig002-28a.c | 63 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in boe_th101mb31ig002_enable() local
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); in boe_th101mb31ig002_enable()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); in boe_th101mb31ig002_enable()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); in boe_th101mb31ig002_enable()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14); in boe_th101mb31ig002_enable()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); in boe_th101mb31ig002_enable()
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); in boe_th101mb31ig002_enable()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10, in boe_th101mb31ig002_enable()
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, in boe_th101mb31ig002_enable()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x65, 0x55, 0x49, 0x46, 0x36, in boe_th101mb31ig002_enable()
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| H A D | panel-himax-hx83112a.c | 61 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in hx83112a_on() local
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETEXTC, 0x83, 0x11, 0x2a); in hx83112a_on()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER1, in hx83112a_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDISP, in hx83112a_on()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, in hx83112a_on()
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x02); in hx83112a_on()
77 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, in hx83112a_on()
80 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x00); in hx83112a_on()
81 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETBANK, 0x03); in hx83112a_on()
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDGCLUT, in hx83112a_on()
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| H A D | panel-asus-z00t-tm5p5-n35596.c | 36 static void tm5p5_nt35596_on(struct mipi_dsi_multi_context *dsi_ctx) in tm5p5_nt35596_on() argument
38 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x05); in tm5p5_nt35596_on()
39 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xfb, 0x01); in tm5p5_nt35596_on()
40 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xc5, 0x31); in tm5p5_nt35596_on()
41 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0xff, 0x04); in tm5p5_nt35596_on()
42 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x01, 0x84); in tm5p5_nt35596_on()
43 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x05, 0x25); in tm5p5_nt35596_on()
44 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x06, 0x01); in tm5p5_nt35596_on()
45 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x07, 0x20); in tm5p5_nt35596_on()
46 mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x08, 0x06); in tm5p5_nt35596_on()
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| H A D | panel-visionox-vtdr6130.c | 49 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_vtdr6130_on() local
53 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in visionox_vtdr6130_on()
55 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x09); in visionox_vtdr6130_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x01); in visionox_vtdr6130_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); in visionox_vtdr6130_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in visionox_vtdr6130_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x12, 0x00, 0x00, 0xab, in visionox_vtdr6130_on()
78 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x10); in visionox_vtdr6130_on()
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| H A D | panel-samsung-s6d7aa0.c | 37 void (*init_func)(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx);
38 void (*off_func)(struct mipi_dsi_multi_context *dsi_ctx);
65 static void s6d7aa0_lock(struct s6d7aa0 *ctx, struct mipi_dsi_multi_context *dsi_ctx, bool lock) in s6d7aa0_lock() argument
68 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5); in s6d7aa0_lock()
69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5); in s6d7aa0_lock()
71 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD3, 0x5a, 0x5a); in s6d7aa0_lock()
73 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a); in s6d7aa0_lock()
74 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a); in s6d7aa0_lock()
76 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_PASSWD3, 0xa5, 0xa5); in s6d7aa0_lock()
83 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in s6d7aa0_on() local
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| H A D | panel-novatek-nt37801.c | 51 #define novatek_nt37801_switch_page(dsi_ctx, page) \ argument
52 mipi_dsi_dcs_write_seq_multi((dsi_ctx), NT37801_DCS_SWITCH_PAGE, \
58 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in novatek_nt37801_on() local
62 novatek_nt37801_switch_page(&dsi_ctx, 0x01); in novatek_nt37801_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in novatek_nt37801_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc5, 0x0b, 0x0b, 0x0b); in novatek_nt37801_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); in novatek_nt37801_on()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); in novatek_nt37801_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf5, 0x10); in novatek_nt37801_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1b); in novatek_nt37801_on()
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| H A D | panel-visionox-r66451.c | 45 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_r66451_on() local
49 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x00); in visionox_r66451_on()
50 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, in visionox_r66451_on()
53 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, in visionox_r66451_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x80); in visionox_r66451_on()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, in visionox_r66451_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x04); in visionox_r66451_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe8, 0x00, 0x02); in visionox_r66451_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe4, 0x00, 0x08); in visionox_r66451_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x00); in visionox_r66451_on()
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| H A D | panel-xinpeng-xpp055c272.c | 62 static void xpp055c272_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in xpp055c272_init_sequence() argument
68 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEXTC, 0xf1, 0x12, 0x83); in xpp055c272_init_sequence()
69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
74 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER_EXT, 0x25); in xpp055c272_init_sequence()
75 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPCR, 0x02, 0x11, 0x00); in xpp055c272_init_sequence()
76 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
79 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
82 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
83 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
84 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
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| H A D | panel-jdi-fhd-r63452.c | 44 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in jdi_fhd_r63452_on() local
48 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00); in jdi_fhd_r63452_on()
49 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01); in jdi_fhd_r63452_on()
50 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, in jdi_fhd_r63452_on()
53 mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03); in jdi_fhd_r63452_on()
55 mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in jdi_fhd_r63452_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in jdi_fhd_r63452_on()
59 mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); in jdi_fhd_r63452_on()
60 mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x0437); in jdi_fhd_r63452_on()
61 mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x077f); in jdi_fhd_r63452_on()
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| H A D | panel-samsung-ams639rq08.c | 58 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in ams639rq08_on() local
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a); in ams639rq08_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a); in ams639rq08_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x0c); in ams639rq08_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_FF, 0x10); in ams639rq08_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x2f); in ams639rq08_on()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_BIAS_CURRENT_CTRL, 0x01); in ams639rq08_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5); in ams639rq08_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5); in ams639rq08_on()
71 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in ams639rq08_on()
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| H A D | panel-elida-kd35t133.c | 53 static void kd35t133_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) in kd35t133_init_sequence() argument
59 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
62 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
65 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_POWERCONTROL1, 0x18, 0x17); in kd35t133_init_sequence()
66 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
67 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_VCOMCONTROL, 0x00, 0x1a, 0x80); in kd35t133_init_sequence()
68 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
70 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
71 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
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| H A D | panel-boe-tv101wum-ll2.c | 48 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in boe_tv101wum_ll2_on() local
52 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); in boe_tv101wum_ll2_on()
54 mipi_dsi_msleep(&dsi_ctx, 120); in boe_tv101wum_ll2_on()
56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e); in boe_tv101wum_ll2_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22, in boe_tv101wum_ll2_on()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23); in boe_tv101wum_ll2_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00); in boe_tv101wum_ll2_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00); in boe_tv101wum_ll2_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19); in boe_tv101wum_ll2_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38); in boe_tv101wum_ll2_on()
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| H A D | panel-visionox-g2647fb105.c | 50 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in visionox_g2647fb105_on() local
52 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x04); in visionox_g2647fb105_on()
53 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); in visionox_g2647fb105_on()
54 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x32); in visionox_g2647fb105_on()
55 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); in visionox_g2647fb105_on()
56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbe, 0x17); in visionox_g2647fb105_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbf, 0xbb); in visionox_g2647fb105_on()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0xdd); in visionox_g2647fb105_on()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0xff); in visionox_g2647fb105_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd0); in visionox_g2647fb105_on()
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| H A D | panel-novatek-nt35950.c | 107 static void nt35950_set_cmd2_page(struct mipi_dsi_multi_context *dsi_ctx, in nt35950_set_cmd2_page() argument
113 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, mauc_cmd2_page, in nt35950_set_cmd2_page()
115 if (!dsi_ctx->accum_err) in nt35950_set_cmd2_page()
125 static void nt35950_set_data_compression(struct mipi_dsi_multi_context *dsi_ctx, in nt35950_set_data_compression() argument
135 nt35950_set_cmd2_page(dsi_ctx, nt, 0); in nt35950_set_data_compression()
137 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_data_compression, in nt35950_set_data_compression()
139 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_on, in nt35950_set_data_compression()
143 nt35950_set_cmd2_page(dsi_ctx, nt, 4); in nt35950_set_data_compression()
146 mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_setting, in nt35950_set_data_compression()
150 nt35950_set_cmd2_page(dsi_ctx, nt, last_page); in nt35950_set_data_compression()
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| H A D | panel-novatek-nt35560.c | 151 struct mipi_dsi_multi_context dsi_ctx = { in nt35560_set_brightness() local
161 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in nt35560_set_brightness()
164 return dsi_ctx.accum_err; in nt35560_set_brightness()
185 mipi_dsi_dcs_write_var_seq_multi(&dsi_ctx, in nt35560_set_brightness()
189 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0xaa); in nt35560_set_brightness()
190 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x01); in nt35560_set_brightness()
191 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x01); in nt35560_set_brightness()
193 mipi_dsi_dcs_write_var_seq_multi(&dsi_ctx, 0x22, pwm_div); in nt35560_set_brightness()
195 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0xaa); in nt35560_set_brightness()
198 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, in nt35560_set_brightness()
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