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Searched refs:dsc (Results 1 – 25 of 134) sorted by relevance

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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc_1_2.c88 struct drm_dsc_config *dsc, in dpu_hw_dsc_config_1_2() argument
99 if (!hw_dsc || !dsc) in dpu_hw_dsc_config_1_2()
112 num_active_slice_per_enc = dsc->slice_count; in dpu_hw_dsc_config_1_2()
114 num_active_slice_per_enc = dsc->slice_count / 2; in dpu_hw_dsc_config_1_2()
129 data = (dsc->dsc_version_minor & 0xf) << 28; in dpu_hw_dsc_config_1_2()
130 if (dsc->dsc_version_minor == 0x2) { in dpu_hw_dsc_config_1_2()
131 if (dsc->native_422) in dpu_hw_dsc_config_1_2()
133 if (dsc->native_420) in dpu_hw_dsc_config_1_2()
137 bpp = dsc->bits_per_pixel; in dpu_hw_dsc_config_1_2()
141 if (dsc->native_422 || dsc->native_420) in dpu_hw_dsc_config_1_2()
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H A Ddpu_hw_dsc.c38 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) in dpu_hw_dsc_disable() argument
40 struct dpu_hw_blk_reg_map *c = &dsc->hw; in dpu_hw_dsc_disable()
46 struct drm_dsc_config *dsc, in dpu_hw_dsc_config() argument
55 bool input_10_bits = dsc->bits_per_component == 10; in dpu_hw_dsc_config()
62 slice_last_group_size = (dsc->slice_width + 2) % 3; in dpu_hw_dsc_config()
67 data |= (dsc->bits_per_pixel << 8); in dpu_hw_dsc_config()
68 data |= (dsc->block_pred_enable << 7); in dpu_hw_dsc_config()
69 data |= (dsc->line_buf_depth << 3); in dpu_hw_dsc_config()
70 data |= (dsc->simple_422 << 2); in dpu_hw_dsc_config()
71 data |= (dsc->convert_rgb << 1); in dpu_hw_dsc_config()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
43 dsc->ctx->logger
48 void dsc401_construct(struct dcn401_dsc *dsc, in dsc401_construct() argument
55 dsc->base.ctx = ctx; in dsc401_construct()
56 dsc->base.inst = inst; in dsc401_construct()
57 dsc->base.funcs = &dcn401_dsc_funcs; in dsc401_construct()
59 dsc->dsc_regs = dsc_regs; in dsc401_construct()
60 dsc->dsc_shift = dsc_shift; in dsc401_construct()
61 dsc->dsc_mask = dsc_mask; in dsc401_construct()
63 dsc->max_image_width = 5184; in dsc401_construct()
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H A Ddcn401_dsc.h13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
343 void dsc401_disconnect(struct display_stream_compressor *dsc);
344 void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c30 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
59 dsc->ctx->logger
61 void dsc35_construct(struct dcn20_dsc *dsc, in dsc35_construct() argument
68 dsc->base.ctx = ctx; in dsc35_construct()
69 dsc->base.inst = inst; in dsc35_construct()
70 dsc->base.funcs = &dcn35_dsc_funcs; in dsc35_construct()
72 dsc->dsc_regs = dsc_regs; in dsc35_construct()
73 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift); in dsc35_construct()
74 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask); in dsc35_construct()
76 dsc->max_image_width = 5184; in dsc35_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddsc.h106 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
107 …void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_r…
108 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
109 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
111 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
113 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
114 void (*dsc_disable)(struct display_stream_compressor *dsc);
115 void (*dsc_disconnect)(struct display_stream_compressor *dsc);
116 void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc);
118 void (*set_fgcg)(struct display_stream_compressor *dsc, bool enable);
H A DMakefile11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
59 dsc->ctx->logger
63 void dsc2_construct(struct dcn20_dsc *dsc, in dsc2_construct() argument
70 dsc->base.ctx = ctx; in dsc2_construct()
71 dsc->base.inst = inst; in dsc2_construct()
72 dsc->base.funcs = &dcn20_dsc_funcs; in dsc2_construct()
74 dsc->dsc_regs = dsc_regs; in dsc2_construct()
75 dsc->dsc_shift = dsc_shift; in dsc2_construct()
76 dsc->dsc_mask = dsc_mask; in dsc2_construct()
78 dsc->max_image_width = 5184; in dsc2_construct()
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H A Ddcn20_dsc.h31 #define TO_DCN20_DSC(dsc)\ argument
32 container_of(dsc, struct dcn20_dsc, base)
572 void dsc_config_log(struct display_stream_compressor *dsc,
575 void dsc_log_pps(struct display_stream_compressor *dsc,
594 void dsc2_construct(struct dcn20_dsc *dsc,
604 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
608 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
609 void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_…
610 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
611 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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/linux/drivers/gpu/drm/panel/
H A Dpanel-visionox-r66451.c178 if (!dsi->dsc) { in visionox_r66451_enable()
183 drm_dsc_pps_payload_pack(&pps, dsi->dsc); in visionox_r66451_enable()
255 struct drm_dsc_config *dsc; in visionox_r66451_probe() local
264 dsc = devm_kzalloc(dev, sizeof(*dsc), GFP_KERNEL); in visionox_r66451_probe()
265 if (!dsc) in visionox_r66451_probe()
269 dsc->dsc_version_major = 0x1; in visionox_r66451_probe()
270 dsc->dsc_version_minor = 0x2; in visionox_r66451_probe()
272 dsc->slice_height = 20; in visionox_r66451_probe()
273 dsc->slice_width = 540; in visionox_r66451_probe()
274 dsc->slice_count = 2; in visionox_r66451_probe()
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H A Dpanel-samsung-s6e3ha8.c22 struct drm_dsc_config dsc; member
201 drm_dsc_pps_payload_pack(&pps, &priv->dsc); in s6e3ha8_amb577px01_wqhd_prepare()
289 dsi->dsc = &priv->dsc; in s6e3ha8_amb577px01_wqhd_probe()
291 priv->dsc.dsc_version_major = 1; in s6e3ha8_amb577px01_wqhd_probe()
292 priv->dsc.dsc_version_minor = 1; in s6e3ha8_amb577px01_wqhd_probe()
294 priv->dsc.slice_height = 40; in s6e3ha8_amb577px01_wqhd_probe()
295 priv->dsc.slice_width = 720; in s6e3ha8_amb577px01_wqhd_probe()
296 WARN_ON(1440 % priv->dsc.slice_width); in s6e3ha8_amb577px01_wqhd_probe()
297 priv->dsc.slice_count = 1440 / priv->dsc.slice_width; in s6e3ha8_amb577px01_wqhd_probe()
298 priv->dsc.bits_per_component = 8; in s6e3ha8_amb577px01_wqhd_probe()
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H A Dpanel-novatek-nt37801.c23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
298 ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */ in novatek_nt37801_probe()
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H A Dpanel-raydium-rm692e5.c23 struct drm_dsc_config dsc; member
154 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in rm692e5_prepare()
321 dsi->dsc = &ctx->dsc; in rm692e5_probe()
324 ctx->dsc.dsc_version_major = 1; in rm692e5_probe()
325 ctx->dsc.dsc_version_minor = 1; in rm692e5_probe()
326 ctx->dsc.slice_height = 60; in rm692e5_probe()
327 ctx->dsc.slice_width = 1224; in rm692e5_probe()
329 ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width; in rm692e5_probe()
330 ctx->dsc.bits_per_component = 8; in rm692e5_probe()
331 ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */ in rm692e5_probe()
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H A Dpanel-visionox-rm692e5.c28 struct drm_dsc_config dsc; member
210 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in visionox_rm692e5_prepare()
397 dsi->dsc = &ctx->dsc; in visionox_rm692e5_probe()
398 ctx->dsc.dsc_version_major = 1; in visionox_rm692e5_probe()
399 ctx->dsc.dsc_version_minor = 1; in visionox_rm692e5_probe()
400 ctx->dsc.slice_height = 20; in visionox_rm692e5_probe()
401 ctx->dsc.slice_width = 540; in visionox_rm692e5_probe()
402 ctx->dsc.slice_count = 1080 / ctx->dsc.slice_width; in visionox_rm692e5_probe()
403 ctx->dsc.bits_per_component = 10; in visionox_rm692e5_probe()
404 ctx->dsc.bits_per_pixel = 8 << 4; in visionox_rm692e5_probe()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c265 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in is_dsi_dsc_1_1()
275 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
276 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in intel_dsc_compute_params()
282 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
307 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16; in intel_dsc_compute_params()
377 crtc_state->dsc.compression_enabled_on_link = true; in intel_dsc_enable_on_crtc()
378 crtc_state->dsc.compression_enable = true; in intel_dsc_enable_on_crtc()
385 drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable && in intel_dsc_enabled_on_link()
386 !crtc_state->dsc.compression_enabled_on_link); in intel_dsc_enabled_on_link()
388 return crtc_state->dsc.compression_enabled_on_link; in intel_dsc_enabled_on_link()
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H A Dintel_dp_mst.c143 bool dsc) in intel_dp_mst_max_dpt_bpp() argument
149 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) in intel_dp_mst_max_dpt_bpp()
250 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) in intel_dp_mtp_tu_compute_config() argument
265 drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) || in intel_dp_mtp_tu_compute_config()
291 crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc); in intel_dp_mtp_tu_compute_config()
299 if (crtc_state->fec_enable && dsc && in intel_dp_mtp_tu_compute_config()
303 max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc)); in intel_dp_mtp_tu_compute_config()
313 if (dsc) { in intel_dp_mtp_tu_compute_config()
330 if (dsc && !intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) { in intel_dp_mtp_tu_compute_config()
336 link_bpp_x16 = dsc ? bpp_x16 : in intel_dp_mtp_tu_compute_config()
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/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
168 struct drm_dsc_config *dsc; member
589 const struct drm_dsc_config *dsc, in dsi_adjust_pclk_for_compression() argument
604 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), in dsi_adjust_pclk_for_compression()
605 dsc->bits_per_component * 3); in dsi_adjust_pclk_for_compression()
616 const struct drm_dsc_config *dsc, bool is_bonded_dsi) in dsi_get_pclk_rate() argument
622 if (dsc) in dsi_get_pclk_rate()
623 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); in dsi_get_pclk_rate()
643 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); in dsi_byte_clk_get_rate()
662 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); in dsi_calc_pclk()
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/linux/drivers/gpu/drm/msm/
H A Dmsm_dsc_helper.h22 static inline u32 msm_dsc_get_bytes_per_line(const struct drm_dsc_config *dsc) in msm_dsc_get_bytes_per_line() argument
24 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h71 const struct display_stream_compressor *dsc,
81 const struct display_stream_compressor *dsc,
97 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
99 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
336 ASSERT(dsc); in update_dsc_on_stream()
346 if (!dsc) { in update_dsc_on_stream()
351 if (dsc->funcs->dsc_read_state) { in update_dsc_on_stream()
352 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
369 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
370 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
372 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
396 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
398 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c1564 struct display_stream_compressor *dsc; in dp_dsc_clock_en_read() local
1585 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1586 if (dsc) in dp_dsc_clock_en_read()
1587 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_clock_en_read()
1750 struct display_stream_compressor *dsc; in dp_dsc_slice_width_read() local
1771 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1772 if (dsc) in dp_dsc_slice_width_read()
1773 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_width_read()
1934 struct display_stream_compressor *dsc; in dp_dsc_slice_height_read() local
1955 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
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/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
/linux/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c773 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
780 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
837 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
840 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
846 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
852 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; in sbdma_add_rcvbuffer()
887 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
895 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
926 dsc->dscr_a = phys | in sbdma_add_txbuffer()
935 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | in sbdma_add_txbuffer()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c1022 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream() local
1040 ASSERT(dsc); in dcn32_update_dsc_on_stream()
1050 if (!dsc) { in dcn32_update_dsc_on_stream()
1055 if (dsc->funcs->dsc_read_state) { in dcn32_update_dsc_on_stream()
1056 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dcn32_update_dsc_on_stream()
1076 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in dcn32_update_dsc_on_stream()
1077 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in dcn32_update_dsc_on_stream()
1078 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in dcn32_update_dsc_on_stream()
1080 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in dcn32_update_dsc_on_stream()
1104 dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc); in dcn32_update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c751 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
758 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
808 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
825 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
848 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
849 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in link_set_dsc_on_stream()
850 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
852 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
868 dsc_optc_config_log(dsc, &dsc_optc_cfg); in link_set_dsc_on_stream()
880 dsc_optc_config_log(dsc, &dsc_optc_cfg); in link_set_dsc_on_stream()
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