Searched refs:dram_bw_table (Results 1 – 5 of 5) sorted by relevance
63 …min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_tab… in build_min_clk_table_fine_grained()65 …min_table->dram_bw_table.entries[i].min_fclk_khz = (unsigned long)((((double)min_table->dram_bw_ta… in build_min_clk_table_fine_grained()67 min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values; in build_min_clk_table_fine_grained()70 for (i = min_table->dram_bw_table.num_entries - 1; i > 0; i--) { in build_min_clk_table_fine_grained()71 prev_100 = min_table->dram_bw_table.entries[i - 1].min_fclk_khz; in build_min_clk_table_fine_grained()72 cur_50 = min_table->dram_bw_table.entries[i].min_fclk_khz / 2; in build_min_clk_table_fine_grained()73 min_table->dram_bw_table.entries[i].min_fclk_khz = prev_100 > cur_50 ? prev_100 : cur_50; in build_min_clk_table_fine_grained()76 …min_table->dram_bw_table.entries[i].min_fclk_khz = round_up_to_quantized_values(min_table->dram_bw… in build_min_clk_table_fine_grained()79 min_table->dram_bw_table.entries[0].min_fclk_khz /= 2; in build_min_clk_table_fine_grained()82 for (i = 0; i < (int)min_table->dram_bw_table.num_entries; i++) { in build_min_clk_table_fine_grained()[all …]
10 …onst struct dml2_dram_params *dram_config, struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) in dram_bw_kbps_to_uclk_khz() argument22 for (i = 0; i < dram_bw_table->num_entries; i++) in dram_bw_kbps_to_uclk_khz()23 if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { in dram_bw_kbps_to_uclk_khz()24 uclk_khz = dram_bw_table->entries[i].min_uclk_khz; in dram_bw_kbps_to_uclk_khz()44 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; in get_minimum_clocks_for_latency()45 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()46 …*uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_… in get_minimum_clocks_for_latency()47 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in get_minimum_clocks_for_latency()68 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()73 &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); in calculate_system_active_minimums()[all …]
55 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; member
15 …out->stage1.min_clk_index_for_latency = dml->min_clk_table.dram_bw_table.num_entries - 1; //dml->m… in setup_unoptimized_display_config_with_meta()1164 pmo_init_params.mcg_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries; in dml2_top_soc15_initialize_instance()
7080 …truct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) in uclk_khz_to_dram_bw_mbps() argument7088 for (i = 0; i < dram_bw_table->num_entries; i++) in uclk_khz_to_dram_bw_mbps()7089 if (dram_bw_table->entries[i].min_uclk_khz >= uclk_khz) { in uclk_khz_to_dram_bw_mbps()7090 bw_mbps = (double)dram_bw_table->entries[i].pre_derate_dram_bw_kbps / 1000.0; in uclk_khz_to_dram_bw_mbps()7971 …mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].… in dml_core_mode_support()7972 …mode_lib->ms.FabricClock = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_in… in dml_core_mode_support()7978 …mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()7980 …mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_… in dml_core_mode_support()7981 …mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_i… in dml_core_mode_support()7982 …lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_ta… in dml_core_mode_support()[all …]