Searched refs:dprefclk_ss_divider (Results 1 – 15 of 15) sorted by relevance
116 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { in dce_adjust_dp_ref_freq_for_ss()119 clk_mgr_dce->dprefclk_ss_divider), 200); in dce_adjust_dp_ref_freq_for_ss()349 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; in dce_clock_read_ss_info()373 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; in dce_clock_read_ss_info()457 clk_mgr->dprefclk_ss_divider = 1000; in dce_clk_mgr_construct()
135 if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { in clk_mgr_adjust_dp_ref_freq_for_ss()138 clk_mgr_dce->dprefclk_ss_divider), 200); in clk_mgr_adjust_dp_ref_freq_for_ss()420 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; in dce_clock_read_ss_info()444 clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; in dce_clock_read_ss_info()482 clk_mgr_dce->dprefclk_ss_divider = in dce121_clock_patch_xgmi_ss_info()831 clk_mgr_dce->dprefclk_ss_divider = 1000; in dce_clk_mgr_construct()
69 clk_mgr_dce->dprefclk_ss_divider = in dce121_clock_patch_xgmi_ss_info()
197 clk_mgr->dprefclk_ss_divider = 1000; in dcn201_clk_mgr_construct()
329 clk_mgr->dprefclk_ss_divider = 1000; in rv1_clk_mgr_construct()
408 int dprefclk_ss_divider; member
955 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider; in dcn32_clock_read_ss_info()1168 clk_mgr->dprefclk_ss_divider = 1000; in dcn32_clk_mgr_construct()
538 clk_mgr->dprefclk_ss_divider = 1000; in dcn3_clk_mgr_construct()
550 clk_mgr->dprefclk_ss_divider = 1000; in dcn20_clk_mgr_construct()
596 clk_mgr->base.dprefclk_ss_divider = 1000; in dcn316_clk_mgr_construct()
723 clk_mgr->dprefclk_ss_divider = 1000; in rn_clk_mgr_construct()
695 clk_mgr->base.dprefclk_ss_divider = 1000; in vg_clk_mgr_construct()
859 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider; in dcn35_read_ss_info_from_lut()1414 clk_mgr->base.dprefclk_ss_divider = 1000; in dcn35_clk_mgr_construct()
691 clk_mgr->base.dprefclk_ss_divider = 1000; in dcn31_clk_mgr_construct()
1288 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider; in dcn401_clock_read_ss_info()1569 clk_mgr->dprefclk_ss_divider = 1000; in dcn401_clk_mgr_construct()